CN102932696A - Satellite-borne high-speed data multiplexer system and realizing method thereof - Google Patents
Satellite-borne high-speed data multiplexer system and realizing method thereof Download PDFInfo
- Publication number
- CN102932696A CN102932696A CN2012103754660A CN201210375466A CN102932696A CN 102932696 A CN102932696 A CN 102932696A CN 2012103754660 A CN2012103754660 A CN 2012103754660A CN 201210375466 A CN201210375466 A CN 201210375466A CN 102932696 A CN102932696 A CN 102932696A
- Authority
- CN
- China
- Prior art keywords
- data
- groups
- sdram
- module
- segment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a satellite-borne high-speed data multiplexer system and a realizing method thereof. The system comprises a data grouping module, a data sub-packaging module, an SDRAM (Synchronous Dynamic random access memory) optimal control module, a virtual channel scheduling module and a channel coding module, wherein the data grouping module receives 30 paths of information source data; the 30 paths of information source data are divided into 5 groups according to a transmission priority or a strategy of balanced data volume; the data sub-packaging module is used for splitting and organizing packets in each path of the information source data in the 5 groups so as to form 5 groups of protocol unit data; the SDRAM optimal control module is used for respectively writing 5 groups of protocol unit data into 5 SDRAMs for caching and reading control so as to form 5 groups of virtual channel data; the virtual channel scheduling module is used for performing dynamic scheduling management and multiple connection on the 5 groups of virtual channel data and one group of empty frames so as to be combined to form one path of form type code flow; and the channel coding module is used for isolating the one path of form type code flow from an FIFO (first in and first out) by a local clock, and coding and scrambling the isolated form type code flow so as to form one path of data transmission frame as the output of the data multiplexer system.
Description
Technical field
The present invention relates to a kind of spaceborne high-speed data multiplexer system and implementation method, belong to the data transmission system field of spacecraft.
Background technology
The theoretical foundation of data multiplexing is the concept of pseudo channel.A physical channel is divided into a plurality of logic channels, and each logic channel is identified separately and is transmitted a kind of data flow, and each data flow can be used different business, and a logic channel is exactly a pseudo channel.Pseudo channel is so that a physical space channel is shared in time-multiplexed mode by a plurality of high level data streams, thereby the data of number of different types can be transmitted at a physical channel.
Spaceborne data multiplexing device system responsible multi-source data that receives in spatial data transmission, be the information source data (visible light packed data, spectroscopic data, SAR data, investigation load data, satellite platform data etc.) of multichannel different-format, different rates, the input form of every road information source data generally as shown in Figure 5; To every road information source data, adopt the concept of " subpackage " to organize, have the protocol element data of consolidation form according to the formation of CCSDS agreement; The protocol element data corresponding to the multichannel various information source, adopt the concept of " pseudo channel " to carry out multiple connection, the data of various information source are assembled into unified data transmission frames (frame format as shown in Figure 4), after encrypting and encoding, transmit between star-star or star-ground through the Same Physical channel.One of them requirement to spaceborne data multiplexing device system is at receiving terminal, can according to information such as the virtual channel identifier in the transfer of data frame format, frame counter, BPDU top guides, restore the complete information of each various information source.
Data multiplexing device system generally comprises data buffer storage unit, the data protocol unit, the data dispatch unit, 4 parts in chnnel coding unit, data buffer storage unit is used for the multi-source data of input is carried out clock zone switching and data buffer storage, the data protocol unit generates and meets the virtual channel data unit unit that the CCSDS agreement has specific format, the data dispatch unit carries out dynamic dispatching management and asynchronous multiplexing to a plurality of virtual channel data unit unit, the organising data frame, generate the data code flow with consolidation form, the chnnel coding unit carries out the RS/LDPC coding to above-mentioned data code flow, scrambling generates the data code flow that is fit to the physical channel transmission.
Prior art relates generally to design of hardware and software, multiple connection algorithm and the implementation strategy of multichannel data multiplexer system under 100,000,000 stage speeds.
The 3rd page of structure of having described a kind of multichannel data multiplexer of the emerging paper of Space Sci. ﹠ Application Research Center, Chinese Academy of Sciences's old sight in 2010 " based on the design of senior restructural multiplexer in the rail system ", for typical multiplexer based on prior art forms structure, as shown in Figure 1, can realize 4 circuit-switched data multiple connections.
2007 great writers' of Postgraduate School, Chinese Academy of Sciences Master's thesis " based on the configurable multiplexer design of the high speed of CCSDSAOS and FPGA " the 3rd chapter has been introduced a kind of implementation method of multichannel data multiplexer, can realize 6 circuit-switched data multiple connections, processing speed is 144Mbps, be typical multiplexer implementation method based on prior art, as shown in Figure 2.
The paper of Space Sci. ﹠ Application Research Center, Chinese Academy of Sciences's Yang Yi health in 2006 " high-speed multiplexer principle prototype and sky-ground transmission system thereof " has proposed a kind of implementation method of multichannel data multiplexer, and bit rate is 640Mbps.
Chinese patent " a kind of high-speed multiplexer and its implementation " (patent No.: CN96109329.3) provide a kind of multiplexer implementation method for spacecraft in 1996, can finish the asynchronous multiplexing of 3 tunnel input data, processing speed is 100,000,000 grades.
The multiplexer implementation method of other Introduction of Literatures, similar with implementation method in the above-mentioned document, there is following four problems:
(1) only support that burst length is less, and burst length is fixed the multi-source data multiple connection of (among Fig. 5 t1 time shorter, be generally less than 16K clock cycle, and for every circuit-switched data, t1 length immobilizes);
(2) data buffer storage unit generally selects the outer FIFO of sheet, the outer SRAM of sheet or ram in slice as buffer, and with input information source data one by one corresponding (the corresponding sheet External Registers of every road information source data), data buffer storage speed is lower, buffer memory capacity is less;
(3) attainable multiple connection object less (general realization is lower than 8 tunnel different pieces of information multiple connection);
(4) processing speed lower (being generally less than 700Mbps).
Summary of the invention
Technology of the present invention is dealt with problems: the above-mentioned deficiency that overcomes prior art, a kind of spaceborne multichannel data multiplexer system and implementation method are provided, break through the restriction of 100,000,000 grades of processing speeds, can realize the high speed multiple connection of G bit-level multichannel data, increase simultaneously the data multiplexing way, realize the real-time multiple connection of 30 tunnel different pieces of informations.
The technology of the present invention solution: a kind of spaceborne high-speed data multiplexer system, comprise: packet module, data subpackage module, SDRAM optimal control module, virtual channel schedule module, channel coding module, this system is take FPGA and SDRAM as implementation platform, buffer memory is realized by FPGA in the logic function of above-mentioned each module and the sheet, buffer memory is realized by SDRAM outside the sheet, wherein:
The packet module: receive 30 tunnel information source data, be divided into 5 groups according to the strategy of transmission priority or equilibrium criterion amount, every group of 6 circuit-switched data are inputted as data subpackage module;
Data subpackage module: 5 groups of data of receive data grouping module, every road information source number in every group according to this packet is the unit input, described packet is split, form some segment datas, produce simultaneously some segment informations in the split process, segment information comprises fragmentation count device and BPDU top guide, segment information and segment data are organized, generate the protocol element data, 5 groups of corresponding 5 groups of protocol element data of data are as the input of SDRAM optimal control module;
SDRAM optimal control module: 5 groups of protocol element data of receive data subpackage module, write respectively 5 SDRAM and carry out buffer memory, under the reading request signal of virtual channel schedule module, read 5 SDRAM data, form 5 groups of pseudo channel data, as the input of virtual channel schedule module;
Virtual channel schedule module: 5 groups of pseudo channel data that receive SDRAM optimal control module, and produce 1 group of empty frame by the infilled frame unit, above-mentioned 6 groups of data are carried out dynamic dispatching management and multiple connection, be combined into 1 road form code stream, as the input of channel coding module;
Channel coding module: 1 road form code stream that receives the virtual channel schedule module, isolate by local clock and FIFO, eliminate the shake that high frequency clock is introduced in processing and transmission course, to form code stream parallel encoding and the scrambling after the isolation, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.
Described packet module specific implementation is: when dividing into groups according to transmission priority, according to the difference of inhomogeneity information source data to requirement of real-time, the information source data that requirement of real-time is the highest are divided at the 1st group, the like, the information source data that requirement of real-time is minimum are divided at the 5th group; When dividing into groups according to the strategy of equilibrium criterion amount, add up the valid data amount of 30 tunnel information source data, according to the average amount principle, 30 tunnel information source data are divided into 5 groups of data.
Described data subpackage module specific implementation is:
(1) every road information source data of corresponding every group of data, when the packet of these information source data is split, the segment data that forms and segment information need buffer memory in the sheet, set up respectively two RAM in FPGA inside and realize buffer memory in the sheet, be segment data RAM and segment information RAM, wherein segment data RAM is used for the buffer memory segment data, segment information RAM is used for the buffer memory segment information, segment information comprises the fragmentation count device, the BPDU top guide that is used for the byte length of sign segment data, when carrying out the interior buffer memory of sheet, segment data and segment information are write respectively each self-corresponding RAM;
(2) two RAM being carried out synchrodata reads, when namely reading the data of a certain address field of segment data RAM, read simultaneously the data of segment information RAM appropriate address section, the data that read are organized, and add frame alignment word, virtual channel identifier, form the protocol element data;
5 groups of protocol element data of (3) 5 groups of data formations.
Described SDRAM optimal control module concrete grammar is:
(1) corresponding every group of protocol element data use 1 SDRAM as the outer buffer memory of sheet;
(2) behind the SDRAM power-up initializing, the control of SDRAM is optimized for the process of writing, read procedure and null process, according to refresh cycle, operating frequency and the protocol Data Unit length of SDRAM, determine a work period, switch above-mentioned writing between process, read procedure and the null process;
Carry out when (3) satisfying the SDRAM write condition and write process, the protocol element data are write SDRAM, carry out read procedure when satisfying SDRAM and reading condition, read SDRAM data generating virtual channel data, carry out null process when not satisfying the write condition of SDRAM or reading condition;
5 groups of pseudo channel data of (4) 5 groups of protocol element data formations.
Described virtual channel schedule module specific implementation is:
(1) corresponding every group of pseudo channel data, need buffer memory in the sheet when dynamic dispatching management, set up 1 formatted data RAM in FPGA inside, the data that are used for the outer buffer memory of trimmer read the frequency, and reading out data carried out buffer memory in the sheet, 5 groups of corresponding 5 formatted data RAM of pseudo channel data;
(2) according to the buffer data size of formatted data RAM the form data RAM is read and write control, read-write operation is independent, produces 5 groups of formatted datas when 5 formatted data RAM are read;
(3) produce 1 group of empty frame by the infilled frame unit;
(4) 5 groups of formatted datas and 1 group of empty frame are carried out data multiplexing, be combined into 1 road AOS form code stream.
Described channel coding module specific implementation is:
(1) receives 1 road AOS form code stream, set up FIFO in FPGA inside, synchronised clock with the form code stream writes FIFO with AOS form code stream, read FIFO with local clock, be used for eliminating high frequency clock in the shake of processing and transmission course is introduced, and improve interface adaptability and Systems balanth;
(2) for making above-mentioned FIFO isolation not affect the data structure of AOS form code stream, the formatted data that reads is carried out the frame format arrangement from FIFO, recover its data structure;
(3) formatted data is carried out chnnel coding and scrambling, the generated data transmission frame.
A kind of spaceborne high-speed data multiplexer method, performing step is as follows:
(1) receives 30 tunnel information source data, be divided into 5 groups, every group of 6 circuit-switched data according to the strategy of transmission priority or equilibrium criterion amount;
(2) 5 of the receive data grouping module groups of data, every road information source number in every group according to this packet is the unit input, described packet is split, form some segment datas, produce simultaneously some segment informations in the split process, segment information and segment data are organized, generated the protocol element data, 5 groups of corresponding 5 groups of protocol element data of data;
(3) 5 of receive data subpackage module groups of protocol element data write respectively 5 SDRAM and carry out buffer memory, under reading request signal, read 5 SDRAM data, form 5 groups of pseudo channel data;
(4) receive 5 groups of pseudo channel data, and produce 1 group of empty frame by the infilled frame unit, above-mentioned 6 groups of data are carried out dynamic dispatching management and multiple connection, be combined into 1 road form code stream;
(5) receive 1 road form code stream, isolate by local clock and FIFO, eliminate the shake that high frequency clock is introduced in processing and transmission course, to form code stream parallel encoding and the scrambling after the isolation, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.
The present invention compared with prior art has following beneficial effect:
(1) the present invention proposes the generation method of the subpackage of a kind of large burst length data and respective protocol data cell, can't realize that with prior art burst length generates greater than data subpackage and the protocol Data Unit of 1M byte, it is tens K bytes and the fixing information source data of length that prior art is only processed burst length, development along with the earth observation technology, single channel information source data for spacecraft output, its burst data length dynamically changeable, and scope be a few K bytes to tens Mbytes, the method that the present invention proposes efficiently solves the deficiencies in the prior art;
(2) optimal control of SDRAM of the present invention has reduced the complexity of SDRAM control greatly, so that SDRAM can be used for the outer buffer unit of the sheet of multiplexer, has improved buffer memory rate and buffer memory capacity, has realized high speed multiple connection and the processing of G bit-level data;
(3) the buffer unit technology of sharing of inhomogeneity data of the present invention, sheet data file of 6 kinds of inhomogeneity data sharings has reduced sheet External Registers number, greatly reduces cost, has improved level of integrated system.
(4) Clock Isolation Technique in the channel coding module of the present invention can be eliminated the shake that high frequency clock is introduced in processing and transmission course, improve interface adaptability and Systems balanth degree.
Description of drawings
Fig. 1 is multiplexer structure chart in the prior art;
Fig. 2 is the implementation method schematic diagram of multiplexer in the prior art;
Fig. 3 is the composition frame chart of system of the present invention;
Fig. 4 is the flow chart that multi-source data of the present invention is input to data transmission frames output;
Fig. 5 is the data format of data transmission frames of the present invention;
Fig. 6 is the input data mode of a certain information source of the present invention;
Fig. 7 is that fractionation and the protocol element data of a certain information source one bag data of the present invention generate schematic diagram;
Fig. 8 is the state machine diagram of SDRAM optimal control of the present invention;
Fig. 9 is pseudo channel dynamic dispatching management procedure chart of the present invention;
Figure 10 is the schematic diagram of channel coding module of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing and implementation:
As shown in Figure 3, a kind of spaceborne high-speed data multiplexer of the present invention system comprises 5 modules such as packet module, data subpackage module, SDRAM optimal control module, virtual channel schedule module, channel coding module, wherein:
Packet module: receive 30 road inhomogeneous multi-source datas, respectively with MSD1, MSD2 ..., MSD30 represents, strategy according to transmission priority or equilibrium criterion amount divides into groups, per 6 circuit-switched data are one group, be divided into 5 groups, be followed successively by the 1st group (MGD1), the 2nd group (MGD2), the 3rd group (MGD3), the 4th group (MGD4), the 5th group (MGD5); When dividing into groups according to transmission priority, according to the difference of inhomogeneity data to requirement of real-time, the information source data that requirement of real-time is the highest are divided at the 1st group, the like, the minimum information source data of requirement of real-time are divided at the 5th group; When dividing into groups according to the strategy of equilibrium criterion amount, add up the average amount of 30 circuit-switched data, according to the valid data amount of every group of data after the grouping principle near average amount, 30 road multi-source datas are divided into 5 groups of data.
Data subpackage module: 5 groups of data of receive data grouping module, every road information source data for every group, length according to data transmission frames BPDU bit stream data territory among Fig. 5, among Fig. 6 one bag data (corresponding to the t1 time) are split, form some segment datas, produce simultaneously some segment informations in the split process, segment information comprises fragmentation count device and BPDU top guide, after splitting, a complete packet is divided into some segment datas, at the anterior frame alignment word that adds of each segment data, the spacecraft identifier, virtual channel identifier, the fragmentation count device, the BPDU top guide, reserve VCDU error control territory at every segment data rear portion, position, checking symbol territory, generate the protocol element data, 5 groups of corresponding 5 groups of protocol element data of data
Wherein the generation concrete grammar of data subpackage and protocol element data is:
Every road information source data for every group, its data packet length is variable, generally from a few K bytes to tens Mbytes, for wherein bag data of appointment in certain road information source, its data length is determined, be assumed to be DP_LENTH, the maximum length in data transmission frames BPDU bit stream data territory is assumed to be DU_LENTH, and bag data are divided into M section, M=DP_LENTH/DU_LENTH+i, i equaled 0 when wherein DP_LENTH was the integral multiple of DU_LENTH, otherwise i equals 1; One bag data are divided into some segment datas, the 1st byte of the 1st segment data is corresponding to the 1st byte of these bag data, the length of the 1st segment data equals DU_LENTH, the length of M segment data is MD_LENTH, MD_LENTH=DP_LENTH%DU_LENTH, BPDU bit stream data territory corresponding to M segment data is comprised of last MD_LENTH byte and the partially filled byte (byte of padding length is DU_LENTH-MD_LENTH) of these bag data.
The generation of the segmentation of packet and protocol element data is take FPGA as realizing carrier, and FPGA has the interior storage resources of abundant sheet can be used for data buffer storage, and a large amount of trigger resources and combination logic resource can be used for realizing sequence circuit.To one tunnel information source data, set up two RAM as buffer area in FPGA inside, one is segment data RAM, be used for this circuit-switched data of input is carried out real-time segmentation and buffer memory, each segment data is buffered in respectively the different address fields of segment data RAM, and another purpose of segment data RAM is that clock zone switches; Another buffer area is segment information RAM, and the segment information that produces when being used for segmentation carries out buffer memory, and wherein the segment data counter identifies position or the order of this segment data in a complete data packet, and the BDDU top guide identifies the byte length of this segment data; In the data sectional process, in clock gap corresponding to first byte of each segment data, the fragmentation count device of this segment data is buffered in segment information RAM, in clock gap corresponding to last byte of each segment data, the BPDU top guide of this segment data is buffered in segment information RAM, for each segment data, in segment data RAM and segment information RAM, distribute corresponding address field, can carry out complete information cache (segment data and segment information), in segment data RAM and segment information RAM, be to carry out buffer memory take section as unit namely.In the packet module, every group of data comprise 6 tunnel information source data, therefore for every group of data, set up respectively 6 segment data RAM and 6 segment information RAM in FPGA inside, are used for realizing the real-time independent buffer memory of 6 tunnel information source data.In SDRAM optimal control module, produce W_req signal (written request signal of SDRAM), by the reading request signal of W_req signal formation segment data RAM and segment information RAM and read sequential, data buffer storage amount according to 6 segment data RAM, at the buffer memory that only has a segment data RAM during greater than 1 segment data, this is counted segmentation reads according to RAM,, a plurality of segment data RAM are carried out poll read during greater than 1 segment data at the buffer memory of a plurality of segment data RAM; When segment data RAM is read, read continuously 1 segment data at every turn, and from segment information RAM, read corresponding fragmentation count device, BPDU top guide, reading under the sequential, be filled in respectively corresponding time slot, simultaneously frame alignment word, spacecraft identifier, virtual channel identifier are filled in corresponding time slot, finish the generation of protocol Data Unit with this.
SDRAM optimal control module: above-mentioned the 2nd module realized the fractionation of packet, the generation of protocol element data and a data multiplexing, 6 tunnel information source data (one group of data) multiple connection is (or being combined into) 1 group of protocol element data, the data of writing as a slice SDRAM, the protocol element data have comprised the necessary information of distinguishing each road information source and each road information source subpackage, therefore 6 kinds of inhomogeneity data can use a sheet External Registers SDRAM as data buffer area, a plurality of information source data are shared a sheet External Registers, greatly reduced the number of sheet External Registers, be conducive to reduce cost and improve level of integrated system.Use SDRAM as the sheet External Registers, SDRAM has at a high speed and jumbo characteristics, with FIFO, the sheets such as SRAM store comparison outward, the control of SDRAM is comparatively complicated, therefore the control to SDRAM is optimized in this module, the data buffer storage amount of 6 segment data RAM is the controlled condition of writing of SDRAM in above-mentioned the 2nd module, the controlled condition of reading take the output speed of data multiplexing device system and pseudo channel priority as SDRAM, realize the optimal control of SDRAM, the outer high-speed data that reaches with process chip FPGA that stores of high-speed chip of realizing simultaneously G bit-level data exchanges, the processing speed of data multiplexing device is higher than 3.6Gbps among the present invention
Wherein to the concrete grammar of SDRAM optimal control be:
In the high-speed data multiplexer, the read-write of SDRAM is by page operations, protocol element data in corresponding above-mentioned the 2nd module of one page data, suggestion is 1024 bytes to its length according to CCSDS, select the SDRAM of 32 bit data bit wides, then the write operation of SDRAM is, in 256 continuous clocks, each clock writes the data of 32 bits (4 byte) to SDRAM, equally, a read operation to SDRAM is, and reads 1024 bytes (data of 256 32 bit bit wides) from the SDRAM one-time continuous; The control of SDRAM is optimized for 4 kinds of operations (process) such as initialization operation, write operation, read operation, do-nothing operation, wherein initialization operation 300us after SDRAM powers on finished in the time period, comprise the wait that powers on of 200us, and preliminary filling, refresh, 3 orders such as mode register arranges, after initialization operation is finished, until before SDRAM re-powers, no longer carry out the initialization operation of SDRAM next time; The working clock frequency of SDRAM is selected greater than 50MHz, according to the space requirement of SDRAM refresh time, per 280 clocks are set all BANK of SDRAM are refreshed once (sending a refresh command to SDRAM), take 280 clocks as the cycle, selection is carried out write operation, read operation or do-nothing operation to SDRAM, after SDRAM finishes initialization operation, the operation of SDRAM to be rotated between write operation, read operation and do-nothing operation exactly, the time interval between each operation is 280 clocks; When satisfying the write operation condition, be that the protocol Data Unit number of data RAM buffer memory in above-mentioned the 2nd module is greater than 1, SDRAM is carried out write operation one time, the write pointer of SDRAM moves down 256 addresses simultaneously, a simple write operation comprises 1 line activating order, 1 write order, 1 preliminary filling order, 1 refresh command and 276 null command (280 clocks of a write operation, each the time clockwise SDRAM send a control command, when not sending effective control command, send null command to SDRAM), by a write operation, a protocol Data Unit is write SDRAM; When satisfying the read operation condition, when namely the 4th module proposes reading request signal to SDRAM, SDRAM is carried out a read operation, the read pointer of SDRAM moves down 256 addresses simultaneously, a simple read operation comprises 1 line activating order, 1 read command, 1 preliminary filling order, 1 refresh command and 276 null commands, by a read operation, read a protocol Data Unit from SDRAM; When write operation condition and the equal deficiency of read operation condition satisfy, SDRAM is carried out a do-nothing operation, a simple do-nothing operation comprises 1 refresh command and 279 null commands; When write operation condition and read operation condition satisfy simultaneously, for reducing the empty frame per second of multiplexer, preferentially carry out the read operation of SDRAM.
Virtual channel schedule module: according to the output speed requirement of data multiplexing device system, data to 5 sheet External Registers SDRAM are selected to read, select according to being transmission priority, the pseudo channel data corresponding SDRAM higher to transmission priority should preferentially select to read; Under without the transmission priority condition, for reducing the data from overflow risk of sheet External Registers, selecting the SDRAM of data buffer storage amount maximum preferentially to read, perhaps is the data distribution densities of a plurality of pseudo channel data of balance in a physical channel, can carry out poll between 5 SDRAM and read; By SDRAM is read control, can realize the dynamic dispatching management of pseudo channel data, the protocol element data corresponding to a plurality of pseudo channels of 5 SDRAM outputs be carried out multiple connection, with the empty frame data of infilled frame unit generation, generate the data code flow with consolidation form
Wherein the concrete grammar of pseudo channel Data Dynamic dispatching management is:
High-speed data multiplexer system, the outer SDRAM of corresponding 5 sheets, set up 5 formatted data RAM in FPGA inside, be respectively applied to write the output data of every SDRAM, formatted data RAM writes the working clock frequency that clock frequency equals SDRAM, determine under the condition in the output speed of data multiplexing device system, formatted data RAM reads clock RCLK, its frequency is determined, can produce the sequential of reading of formatted data RAM with this frequency, per 256 RCLK clocks are an AOS form code stream output cycle, poll to SDRAM reads, namely read with the sequential poll between 5 formatted data RAM of reading that produces, when 5 formatted data RAM all do not satisfy the read data condition, when namely the buffer data size of 5 formatted data RAM is all less than 1 pseudo channel data length, in reading sequential, insert the empty frame that the infilled frame unit produces this moment, to keep the continuity of output data (AOS form code stream); Reading under the sequential that RCLK produces, from 5 formatted data RAM, read the pseudo channel data, when between the pseudo channel data of output, having the interval (gap length is the integral multiple of 256 clock cycle), insert the empty frame that the infilled frame unit produces, with this form one take 256 clocks as the cycle, data bit width is as 32 AOS form code stream.
Channel coding module: for the AOS form code stream of above-mentioned the 4th module output, at first carry out bit width conversion, forming a data bit wide is 8,4 times of accompanying clock frequencies are to the form code stream of RCLK (this accompanying clock is designated as AOS_CLK), corresponding 1 byte data of accompanying clock in this form code stream, per 1024 bytes are called frame data; After the bit width conversion, by setting up FIFO in FPGA inside, the isolation of employing local clock, eliminate the shake that high frequency clock is introduced in processing and transmission course, afterwards VCDU data cell (referring to Fig. 4) is encrypted by byte, and carry out RS/LDPC and encode, data scrambling, select RS (255 during the RS coding, 223) or RS (255,239), select (8160 during the LDPC coding, 7136) shorten code, the check character that produces during the RS/LDPC coding is replaced the partially filled byte (the checking symbol territory in Fig. 4 frame format) of pseudo channel data, adopts parallel scrambling mode during data scrambling, processes with the high-speed data of realizing the G bit-level.
A kind of spaceborne high-speed data multiplexer system and implementation method comprise the steps:
(1) receive 30 tunnel inhomogeneity multi-source datas, divide into groups according to the strategy of transmission priority or equilibrium criterion amount, per 6 circuit-switched data are one group, are divided into 5 groups;
(2) for every group 6 circuit-switched data, use 6 segment data RAM of FPGA inside and the generation that 6 segment information RAM realize data subpackage and protocol element data, subpackage refers to a complete data packet of every road information source (data corresponding to t1 time period among Fig. 5) is divided into some segment datas, when subpackage, each segment data is buffered in the corresponding address section of corresponding segment data RAM, and with the fragmentation count device, the BPDU top guide is buffered in the corresponding address section of corresponding segment information RAM, and the method can realize the packet that comprises large burst length and variable-length packet is split; Reading under the segment data RAM sequential, to anterior frame alignment word, spacecraft identifier, virtual channel identifier, fragmentation count device, the BPDU top guide of adding of the segment data of segment data RAM output, add the part byte of padding at the segment data rear portion, can form the protocol element data;
(3) the protocol element data to generating in the step (2), under the SDRAM working clock frequency, through a data multiplexing, be combined into one group of protocol element data, as the data of writing of the outer memory cell SDRAM of a sheet, 5 groups of corresponding 5 groups of protocol element data of data;
(4) 5 groups of corresponding 5 SDRAM of protocol element data, buffer size according to data transmission frames format characteristic and data multiplexing, control to SDRAM is optimized, it is reduced to 3 fundamental modes such as write operation, read operation, do-nothing operation, and under the write operation pattern, finish the G bit-level high-speed cache to 5 groups of data;
(5) according to the output speed of data multiplexing device system, the data of 5 SDRAM are selected to read, set up 5 formatted data RAM in FPGA inside, with the SDRAM work clock for writing clock, output data with 5 SDRAM are written to 5 corresponding formatted data RAM respectively, read clock RCLK with the output speed computation scheme data RAM of data multiplexing device system, produce the sequential of reading of formatted data RAM with this frequency, reading under the sequential that RCLK produces, from 5 formatted data RAM, read the pseudo channel data, when between the pseudo channel data of output, having the interval, insert the empty frame that the infilled frame unit produces, form one take 256 clocks as the cycle with this, data bit width is 32 AOS form code stream.
(6) the AOS form type code in the step (5) is flow to the wide conversion of line position, clock isolation, error correction coding, parallel scrambling after, form the data transmission frames of data multiplexing device system, be used at the Same Physical channel,
Realize the timesharing transmission of 30 road multi-source datas.
Fig. 4 is implementation method flow chart of the present invention, and flow process of the present invention can be divided into multi-source data grouping, data subpackage, the generation of protocol element data, a multiple connection, SDRAM optimal control, infilled frame generation, pseudo channel dynamic management, chnnel coding totally 8 parts.
The specific implementation process is as follows:
(1) 30 road multi-source data is input to the data multiplexing device, is divided into 5 groups according to the strategy of transmission priority or equilibrium criterion amount;
(2) for every group 6 tunnel different pieces of informations, generate, behind data multiplexing, be combined into 1 group of protocol element data, 5 groups of corresponding 5 groups of protocol element data of data through data subpackage, protocol element data respectively;
(3) under the SDRAM written request signal, 1 group of protocol element data is carried out buffer memory as the data of writing of a slice SDRAM;
(4) according to the output speed of data multiplexing device system, calculate and generate the reading request signal of SDRAM, under reading request signal, from 5 SDRAM sense datas;
(5) when SDRAM exports without valid data, produce empty frame by the infilled frame unit;
(6) the pseudo channel data of 5 SDRAM outputs and the empty frame of infilled frame unit generation are carried out the virtual channel schedule management, generate AOS form code stream;
(7) AOS form type code stream is carried out chnnel coding, be formed for the data transmission frames of Same Physical channel.
Fig. 5 is the transfer of data frame format of data multiplexing device output of the present invention, and each explanation of field is as follows:
(1) synchronization character, 16 ary codes 1ACFFC1D are used for the receiving terminal achieve frame synchronous;
(2) virtual channel identifier is used for distinguishing 30 road multi-source datas and empty frame data;
(3) VCDU counting, i.e. fragmentation count device is used for the protocol Data Unit of every road information source after the sign subpackage in the correspondence position relation of these information source data;
(4) BPDU top guide is for the byte number of this data transmission frames of sign BPDU bit stream data territory valid data;
(5) segment data is deposited in BPDU bit stream data territory, during less than this data field length, inserts padding data in segment data, and (5 output RAM are all countless when exporting) are empty frame data without valid data the time;
(6) VCDU error control territory, be used for depositing CRC check and;
(7) checking symbol territory is used for depositing the check digit that channel coding module produces.
Fig. 6 is the input data mode of a certain information source of the present invention, an input signal corresponding to information source comprises synchronised clock, follows gate, data, wherein data bit width is indefinite, generally in 1bit～32bit scope, follow the high level sign valid data of gate, namely need the data of processing and transmitting, follow the low level sign invalid data of gate, the data that namely can abandon also can follow the low level of gate to identify valid data in actual the use, to follow the high level sign invalid data of gate; The duration of one bag data is t, comprise t1 time and t2 time, the t1 time is the valid data transmission time of information source, a complete data packet of a t1 time tranfer information source, namely one of a corresponding information source of t1 be surrounded by the effect data, the t2 time is the invalid data transmission time of information source, i.e. retrace interval, t, t1, t2 all are variable, and wherein the length range of t1 is million clock cycle of a few K clock cycle to tens.
Fig. 7 is the fractionation of a certain information source one bag data of the present invention and the generation schematic diagram of protocol element data.Multi-source data is that one is surrounded by the effect data among Fig. 5 with data transmission frames form shown in Figure 4 transmission in physical channel, i.e. data division corresponding to t1 time, and transmit in the actual physics passage as carrier in BPDU bit stream data territory in Fig. 4 data transmission frames; Because the length of bag data is far longer than the length in BPDU bit stream data territory, therefore a bag Data Division is some sections, and supplementary (frame alignment word, virtual channel identifier, fragmentation count device, BPDU top guide) the formation protocol element data necessary to each segment data interpolation, be used for follow-up data processing and transmission.
The specific implementation process is as follows:
(1) every road information source data are set up two RAM in FPGA inside, one is segment data RAM, is used for each segment data of buffer memory, and one is segment information RAM, is used for buffer memory segmentation supplementary, comprises fragmentation count device, BPDU top guide;
(2) but 4 segment datas of the capacity buffer memory of segment data RAM get final product, divide in the packet procedures in data, in 4 address fields that write segment data RAM with the circulation of each segment data, under the reading request signal of segment data RAM, from the sense data of 4 address fields circulations of segment data RAM;
(3) corresponding with segment data RAM, but the supplementary of 4 segment datas of capacity buffer memory of segment information RAM gets final product, divide in the packet procedures in data, in 4 address fields that write segment information RAM with the circulation of the supplementary of each segment data, when reading the data of a certain address field of segment data RAM, read the supplementary of segment information RAM appropriate address section;
(4) anterior in the segment data of segment data RAM output, add frame alignment word, spacecraft identifier, and to virtual channel identifier that should the road information source, fragmentation count device, the BPDU top guide of segment information RAM output, and reserve error control territory, position, checking symbol territory at the rear portion, namely form the protocol element data;
(5) corresponding 1 tunnel protocol element data of single information source, one group of multi-source data comprises 6 tunnel protocol element data, according to the work clock of SDRAM, 6 tunnel protocol element data is carried out data multiplexing one time, form one group of protocol element data, as the data of writing of 1 SDRAM.
Fig. 8 is the state machine diagram of SDRAM optimal control of the present invention.Use SDRAM as the sheet External Registers, 1 group of protocol element data of 1 SDRAM buffer memory (6 tunnel protocol element data are called 1 group of protocol element data), control to SDRAM is optimized, powering on and after initialization finishes at SDRAM, is 3 kinds of write operation, read operation and do-nothing operations to its simplified control.
The specific implementation process is as follows:
(1) carries out initialization operation after SDRAM powers on, initialization operation comprises that power on wait, 1 preliminary filling order PRE, 8 above refresh command REF, 1 mode register of 200us arranges order MRS and a plurality of null command NOP, when wherein mode register arranges, SDRAM is set for to read and write with page or leaf unit;
(2) after initialization operation is finished, use the work clock of SDRAM, generating one-period is the counter of 280 clocks, produces the control sequential with this cycle counter, and SDRAM is carried out write operation, read operation or do-nothing operation;
(3) after the written request signal of SDRAM sends, and receive the protocol Data Unit of front end input, carry out write operation, a write operation comprises 1 line activating order ACT, 1 write order WRITE, 1 preliminary filling order PRE, 1 refresh command REF, 276 null command NOP;
(4) after the reading request signal of receiving SDRAM send, and the protocol Data Unit number of buffer memory is greater than 1 among the SDRAM, carry out read operation, a read operation comprises 1 line activating order ACT, 1 read command READ, 1 preliminary filling order PRE, 1 refresh command REF, 276 null command NOP;
(5) at the write condition of SDRAM with when reading condition and all not satisfying, carry out do-nothing operation, a do-nothing operation comprises 1 refresh command REF, 279 null command NOP.
Fig. 9 is pseudo channel dynamic dispatching management procedure chart of the present invention, comprises 5 formatted data RAM, 1 infilled frame generation unit, 1 virtual channel schedule unit.
The specific implementation process is as follows:
(1) sets up 5 formatted data RAM in FPGA inside, as the output buffer of 5 SDRAM;
(2) according to the output speed of data multiplexing device system, calculate AOS formatting clock AOS_CLK;
(3) take AOS_CLK as clock, generate the counter in 256 cycles, and read to control sequential with what this counter produced formatted data RAM, between 5 formatted data RAM, read each pseudo channel data;
(4) when the data buffer storage amount of 5 formatted data RAM is lower than 2 pseudo channel data, sends and read SDRAM request signal, independently reading out data from each self-corresponding SDRAM;
(5) 5 formatted data RAM all countless according to the output situation under, export empty frame by the infilled frame generation unit;
(6) the pseudo channel data of 5 formatted data RAM and the empty frame of infilled frame generation unit output are carried out the secondary data multiple connection, form AOS form code stream.
Figure 10 is the schematic diagram of channel coding module of the present invention, this module is comprised of 5 parts such as bit width conversion, FIFO isolation, data frame format arrangement, encryption and chnnel coding, scramblings, wherein latter two part difference with the prior art is to adopt the multidiameter delay processing method, is conducive to promote the processing speed of data multiplexing device.
The specific implementation process is as follows:
(1) after reception AOS form code stream was gone forward side by side the wide conversion of line position, follow-up data was processed by byte of each clock;
(2) set up FIFO in FPGA inside, AOS form code stream writes FIFO with its synchronised clock (accompanying clock), with local clock reading out data from FIFO, is used for eliminating high frequency clock in the shake of processing and transmission course is introduced;
(3) for making above-mentioned FIFO isolation not affect the data structure of AOS form code stream, the data that read are carried out the frame format arrangement from FIFO, recover its data structure;
(4) there are frequency departure in the accompanying clock of AOS form code stream and local clock, and the infilled frame generation unit is exported empty frame, are inserted in case of necessity in the formatted data, to guarantee the continuity of formatted data;
(5) the AOS formatted data is carried out chnnel coding, scrambling after, output data transmission frames.
The above; only be the embodiment of the best of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in technical scope provided by the invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.
The content that is not described in detail in the specification of the present invention belongs to this area professional and technical personnel's known technology.
Claims (7)
1. spaceborne high-speed data multiplexer system, it is characterized in that comprising: packet module, data subpackage module, SDRAM optimal control module, virtual channel schedule module, channel coding module, this system is take FPGA and SDRAM as implementation platform, buffer memory is realized by FPGA in the logic function of above-mentioned each module and the sheet, buffer memory is realized by SDRAM outside the sheet, wherein:
The packet module: receive 30 tunnel information source data, be divided into 5 groups according to the strategy of transmission priority or equilibrium criterion amount, every group of 6 circuit-switched data are inputted as data subpackage module;
Data subpackage module: 5 groups of data of receive data grouping module, every road information source number in every group according to this packet is the unit input, described packet is split, form some segment datas, produce simultaneously some segment informations in the split process, segment information comprises fragmentation count device and BPDU top guide, segment information and segment data are organized, generate the protocol element data, 5 groups of corresponding 5 groups of protocol element data of data are as the input of SDRAM optimal control module;
SDRAM optimal control module: 5 groups of protocol element data of receive data subpackage module, write respectively 5 SDRAM and carry out buffer memory, under the reading request signal of virtual channel schedule module, read 5 SDRAM data, form 5 groups of pseudo channel data, as the input of virtual channel schedule module;
Virtual channel schedule module: 5 groups of pseudo channel data that receive SDRAM optimal control module, and produce 1 group of empty frame by the infilled frame unit, above-mentioned 6 groups of data are carried out dynamic dispatching management and multiple connection, be combined into 1 road form code stream, as the input of channel coding module;
Channel coding module: 1 road form code stream that receives the virtual channel schedule module, isolate by local clock and FIFO, eliminate the shake that high frequency clock is introduced in processing and transmission course, to form code stream parallel encoding and the scrambling after the isolation, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.
2. a kind of spaceborne high-speed data multiplexer according to claim 1 system, it is characterized in that: described packet module specific implementation is: when dividing into groups according to transmission priority, according to the difference of inhomogeneity information source data to requirement of real-time, the information source data that requirement of real-time is the highest are divided at the 1st group, the like, the information source data that requirement of real-time is minimum are divided at the 5th group; When dividing into groups according to the strategy of equilibrium criterion amount, add up the valid data amount of 30 tunnel information source data, according to the average amount principle, 30 tunnel information source data are divided into 5 groups of data.
3. a kind of spaceborne high-speed data multiplexer according to claim 1 system, it is characterized in that: described data subpackage module specific implementation is:
(1) every road information source data of corresponding every group of data, when the packet of these information source data is split, the segment data that forms and segment information need buffer memory in the sheet, set up respectively two RAM in FPGA inside and realize buffer memory in the sheet, be segment data RAM and segment information RAM, wherein segment data RAM is used for the buffer memory segment data, segment information RAM is used for the buffer memory segment information, segment information comprises the fragmentation count device, the BPDU top guide that is used for the byte length of sign segment data, when carrying out the interior buffer memory of sheet, segment data and segment information are write respectively each self-corresponding RAM;
(2) two RAM being carried out synchrodata reads, when namely reading the data of a certain address field of segment data RAM, read simultaneously the data of segment information RAM appropriate address section, the data that read are organized, and add frame alignment word, virtual channel identifier, form the protocol element data;
5 groups of protocol element data of (3) 5 groups of data formations.
4. a kind of spaceborne high-speed data multiplexer according to claim 1 system, it is characterized in that: SDRAM optimal control module concrete grammar is:
(1) corresponding every group of protocol element data use 1 SDRAM as the outer buffer memory of sheet;
(2) behind the SDRAM power-up initializing, the control of SDRAM is optimized for the process of writing, read procedure and null process, according to refresh cycle, operating frequency and the protocol Data Unit length of SDRAM, determine a work period, switch above-mentioned writing between process, read procedure and the null process;
Carry out when (3) satisfying the SDRAM write condition and write process, the protocol element data are write SDRAM, carry out read procedure when satisfying SDRAM and reading condition, read SDRAM data generating virtual channel data, carry out null process when not satisfying the write condition of SDRAM or reading condition;
5 groups of pseudo channel data of (4) 5 groups of protocol element data formations.
5. a kind of spaceborne high-speed data multiplexer according to claim 1 system, it is characterized in that: described virtual channel schedule module specific implementation is:
(1) corresponding every group of pseudo channel data, need buffer memory in the sheet when dynamic dispatching management, set up 1 formatted data RAM in FPGA inside, the data that are used for the outer buffer memory of trimmer read the frequency, and reading out data carried out buffer memory in the sheet, 5 groups of corresponding 5 formatted data RAM of pseudo channel data;
(2) according to the buffer data size of formatted data RAM the form data RAM is read and write control, read-write operation is independent, produces 5 groups of formatted datas when 5 formatted data RAM are read;
(3) produce 1 group of empty frame by the infilled frame unit;
(4) 5 groups of formatted datas and 1 group of empty frame are carried out data multiplexing, be combined into 1 road AOS form code stream.
6. a kind of spaceborne high-speed data multiplexer according to claim 1 system, it is characterized in that: described channel coding module specific implementation is:
(1) receives 1 road AOS form code stream, set up FIFO in FPGA inside, synchronised clock with the form code stream writes FIFO with AOS form code stream, read FIFO with local clock, be used for eliminating high frequency clock in the shake of processing and transmission course is introduced, and improve interface adaptability and Systems balanth;
(2) for making above-mentioned FIFO isolation not affect the data structure of AOS form code stream, the formatted data that reads is carried out the frame format arrangement from FIFO, recover its data structure;
(3) formatted data is carried out chnnel coding and scrambling, the generated data transmission frame.
7. spaceborne high-speed data multiplexer implementation method is characterized in that performing step is as follows:
(1) receives 30 tunnel information source data, be divided into 5 groups, every group of 6 circuit-switched data according to the strategy of transmission priority or equilibrium criterion amount;
(2) 5 of the receive data grouping module groups of data, every road information source number in every group according to this packet is the unit input, described packet is split, form some segment datas, produce simultaneously some segment informations in the split process, segment information and segment data are organized, generated the protocol element data, 5 groups of corresponding 5 groups of protocol element data of data;
(3) 5 of receive data subpackage module groups of protocol element data write respectively 5 SDRAM and carry out buffer memory, under reading request signal, read 5 SDRAM data, form 5 groups of pseudo channel data;
(4) receive 5 groups of pseudo channel data, and produce 1 group of empty frame by the infilled frame unit, above-mentioned 6 groups of data are carried out dynamic dispatching management and multiple connection, be combined into 1 road form code stream;
(5) receive 1 road form code stream, isolate by local clock and FIFO, eliminate the shake that high frequency clock is introduced in processing and transmission course, to form code stream parallel encoding and the scrambling after the isolation, generate 1 circuit-switched data transmission frame, as the output of data multiplexing device system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210375466.0A CN102932696B (en) | 2012-09-29 | 2012-09-29 | Satellite-borne high-speed data multiplexer system and realizing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210375466.0A CN102932696B (en) | 2012-09-29 | 2012-09-29 | Satellite-borne high-speed data multiplexer system and realizing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102932696A true CN102932696A (en) | 2013-02-13 |
| CN102932696B CN102932696B (en) | 2015-07-08 |
Family
ID=47647380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210375466.0A Active CN102932696B (en) | 2012-09-29 | 2012-09-29 | Satellite-borne high-speed data multiplexer system and realizing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102932696B (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103209328A (en) * | 2013-04-19 | 2013-07-17 | 中国科学院遥感与数字地球研究所 | Multi-source satellite image real-time online processing technical method and device |
| CN103441791A (en) * | 2013-08-23 | 2013-12-11 | 上海航天测控通信研究所 | Satellite-bone data transmission emitting device and selection method of input signals thereof |
| CN103957170A (en) * | 2014-03-12 | 2014-07-30 | 中国人民解放军63680部队 | IP transmission multiplexer and IP transmission multiplexing and demultiplexing method |
| CN105141352A (en) * | 2015-07-24 | 2015-12-09 | 哈尔滨工业大学 | Satellite high-speed data transmission baseband data error statistics and frame sequencing processing system and method |
| CN105321522A (en) * | 2014-08-06 | 2016-02-10 | 航天恒星科技有限公司 | Audio data processing and transmitting method and device |
| CN106341402A (en) * | 2016-08-30 | 2017-01-18 | 中国民生银行股份有限公司 | Processing method based on multi-architecture distributed caching and processing device |
| CN106603146A (en) * | 2016-12-30 | 2017-04-26 | 中国电子科技集团公司第五十四研究所 | Synchronous control method for satellite virtual channel data packet transmission delay |
| CN107329910A (en) * | 2017-06-27 | 2017-11-07 | 中南大学 | A kind of web front end data based on localStorage are locally stored and access method |
| CN107608922A (en) * | 2017-08-30 | 2018-01-19 | 西安空间无线电技术研究所 | A kind of gate-control signal cross clock domain restoration methods |
| CN107835440A (en) * | 2017-11-06 | 2018-03-23 | 上海航天测控通信研究所 | A kind of multi-channel high-speed bitstreams switching method based on FPGA |
| CN108681449A (en) * | 2018-05-17 | 2018-10-19 | 北京航空航天大学 | Digital satellite load information compresses multiple connection source code artificial intelligence Writing method |
| CN109661787A (en) * | 2016-08-10 | 2019-04-19 | Idac控股公司 | For controlling the channel coding priority-based of information |
| CN109981162A (en) * | 2019-03-27 | 2019-07-05 | 北京空间飞行器总体设计部 | Data processing and Transmission system suitable for inertial space pointing space astronomical satellite |
| CN110704133A (en) * | 2019-09-11 | 2020-01-17 | 北京控制工程研究所 | Satellite subpackage remote control receiving control method based on finite-state machine |
| CN111221378A (en) * | 2018-11-27 | 2020-06-02 | 成都鼎桥通信技术有限公司 | Clock domain conversion method and device of periodic signal and readable storage medium |
| CN111601078A (en) * | 2020-05-12 | 2020-08-28 | 西安创腾星泰电子科技有限公司 | Satellite-borne video compression system and method for video data direct transmission to ground |
| CN111813717A (en) * | 2020-06-10 | 2020-10-23 | 烽火通信科技股份有限公司 | Device and method for data frame storage switching |
| CN113992764A (en) * | 2021-10-29 | 2022-01-28 | 上海航天计算机技术研究所 | High-reliability measurement and control data transmission channel multiplexing method and system for deep space probe |
| CN115017072A (en) * | 2022-08-08 | 2022-09-06 | 北京象帝先计算技术有限公司 | Burst length splitting method and device, chip system and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986621A (en) * | 2010-11-08 | 2011-03-16 | 中兴通讯股份有限公司 | Data mapping method and device |
| EP2312780A1 (en) * | 2008-08-20 | 2011-04-20 | Huawei Technologies Co., Ltd. | A packet add/drop multiplexing device and a data transmission method of a packet add/drop multiplexing device |
| CN102238436A (en) * | 2010-04-23 | 2011-11-09 | 中兴通讯股份有限公司 | Method and device for processing data in optical transmission |
| CN102394719A (en) * | 2011-09-21 | 2012-03-28 | 浙江铭道通信技术有限公司 | Multichannel HDLC data processing method based on FPGA |
-
2012
- 2012-09-29 CN CN201210375466.0A patent/CN102932696B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2312780A1 (en) * | 2008-08-20 | 2011-04-20 | Huawei Technologies Co., Ltd. | A packet add/drop multiplexing device and a data transmission method of a packet add/drop multiplexing device |
| CN102238436A (en) * | 2010-04-23 | 2011-11-09 | 中兴通讯股份有限公司 | Method and device for processing data in optical transmission |
| CN101986621A (en) * | 2010-11-08 | 2011-03-16 | 中兴通讯股份有限公司 | Data mapping method and device |
| CN102394719A (en) * | 2011-09-21 | 2012-03-28 | 浙江铭道通信技术有限公司 | Multichannel HDLC data processing method based on FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 饶家宁等: "星载高速数据处理单元的设计与实现", 《计算机工程》 * |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103209328B (en) * | 2013-04-19 | 2017-02-22 | 中国科学院遥感与数字地球研究所 | Multi-source satellite image real-time online processing technical method and device |
| CN103209328A (en) * | 2013-04-19 | 2013-07-17 | 中国科学院遥感与数字地球研究所 | Multi-source satellite image real-time online processing technical method and device |
| CN103441791A (en) * | 2013-08-23 | 2013-12-11 | 上海航天测控通信研究所 | Satellite-bone data transmission emitting device and selection method of input signals thereof |
| CN103441791B (en) * | 2013-08-23 | 2016-09-28 | 上海航天测控通信研究所 | A kind of spaceborne data transmitting device and the system of selection of input signal thereof |
| CN103957170A (en) * | 2014-03-12 | 2014-07-30 | 中国人民解放军63680部队 | IP transmission multiplexer and IP transmission multiplexing and demultiplexing method |
| CN105321522A (en) * | 2014-08-06 | 2016-02-10 | 航天恒星科技有限公司 | Audio data processing and transmitting method and device |
| CN105141352A (en) * | 2015-07-24 | 2015-12-09 | 哈尔滨工业大学 | Satellite high-speed data transmission baseband data error statistics and frame sequencing processing system and method |
| CN109661787A (en) * | 2016-08-10 | 2019-04-19 | Idac控股公司 | For controlling the channel coding priority-based of information |
| US11431441B2 (en) | 2016-08-10 | 2022-08-30 | Idac Holdings, Inc. | Priority-based channel coding for control information |
| CN106341402A (en) * | 2016-08-30 | 2017-01-18 | 中国民生银行股份有限公司 | Processing method based on multi-architecture distributed caching and processing device |
| CN106341402B (en) * | 2016-08-30 | 2019-11-12 | 中国民生银行股份有限公司 | Treating method and apparatus based on multi rack structure distributed caching |
| CN106603146B (en) * | 2016-12-30 | 2019-03-15 | 中国电子科技集团公司第五十四研究所 | A kind of synchronisation control means for the delay of satellite virtual channel data divided stator frame |
| CN106603146A (en) * | 2016-12-30 | 2017-04-26 | 中国电子科技集团公司第五十四研究所 | Synchronous control method for satellite virtual channel data packet transmission delay |
| CN107329910A (en) * | 2017-06-27 | 2017-11-07 | 中南大学 | A kind of web front end data based on localStorage are locally stored and access method |
| CN107608922A (en) * | 2017-08-30 | 2018-01-19 | 西安空间无线电技术研究所 | A kind of gate-control signal cross clock domain restoration methods |
| CN107608922B (en) * | 2017-08-30 | 2019-10-22 | 西安空间无线电技术研究所 | A kind of gate-control signal cross clock domain restoration methods |
| CN107835440A (en) * | 2017-11-06 | 2018-03-23 | 上海航天测控通信研究所 | A kind of multi-channel high-speed bitstreams switching method based on FPGA |
| CN108681449A (en) * | 2018-05-17 | 2018-10-19 | 北京航空航天大学 | Digital satellite load information compresses multiple connection source code artificial intelligence Writing method |
| CN111221378A (en) * | 2018-11-27 | 2020-06-02 | 成都鼎桥通信技术有限公司 | Clock domain conversion method and device of periodic signal and readable storage medium |
| CN109981162B (en) * | 2019-03-27 | 2022-03-04 | 北京空间飞行器总体设计部 | Data processing and transmission system suitable for inertial space pointing space astronomical satellite |
| CN109981162A (en) * | 2019-03-27 | 2019-07-05 | 北京空间飞行器总体设计部 | Data processing and Transmission system suitable for inertial space pointing space astronomical satellite |
| CN110704133A (en) * | 2019-09-11 | 2020-01-17 | 北京控制工程研究所 | Satellite subpackage remote control receiving control method based on finite-state machine |
| CN110704133B (en) * | 2019-09-11 | 2023-03-31 | 北京控制工程研究所 | Satellite subpackage remote control receiving control method based on finite-state machine |
| CN111601078A (en) * | 2020-05-12 | 2020-08-28 | 西安创腾星泰电子科技有限公司 | Satellite-borne video compression system and method for video data direct transmission to ground |
| CN111813717A (en) * | 2020-06-10 | 2020-10-23 | 烽火通信科技股份有限公司 | Device and method for data frame storage switching |
| CN113992764A (en) * | 2021-10-29 | 2022-01-28 | 上海航天计算机技术研究所 | High-reliability measurement and control data transmission channel multiplexing method and system for deep space probe |
| CN113992764B (en) * | 2021-10-29 | 2023-04-11 | 上海航天计算机技术研究所 | High-reliability measurement and control data transmission channel multiplexing method and system for deep space probe |
| CN115017072A (en) * | 2022-08-08 | 2022-09-06 | 北京象帝先计算技术有限公司 | Burst length splitting method and device, chip system and electronic equipment |
| CN115017072B (en) * | 2022-08-08 | 2022-11-04 | 北京象帝先计算技术有限公司 | Burst length splitting method and device, chip system and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102932696B (en) | 2015-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102932696B (en) | Satellite-borne high-speed data multiplexer system and realizing method thereof | |
| CN102543162B (en) | Multi-mode memory | |
| KR101467623B1 (en) | Independently controlled virtual memory devices in memory modules | |
| CN103714038B (en) | A kind of data processing method and device | |
| CN100578485C (en) | Data synchronization method of data buffer device | |
| CN101331464A (en) | Storage region allocation system, method, and control device | |
| JPS60501528A (en) | Multi-speed voice/data digital exchange system | |
| CN109446132A (en) | A kind of interface bus device and data communication protocol | |
| CN105245759A (en) | Method and device for realizing image synchronous display | |
| CN103688499A (en) | Optical channel data unit ODU service transmission device and method thereof | |
| CN103309981B (en) | A kind of have high the adc data tissue system and the method thereof that store efficiency | |
| CN101825997A (en) | Asynchronous first-in first-out storage | |
| CN104598404B (en) | Computing device extended method and device and expansible computing system | |
| CN104461934B (en) | A kind of time solution convolutional interleave device and method of suitable DDR memory | |
| CN111966628B (en) | Multi-core combined type large-capacity data synchronous storage method | |
| CN101656586B (en) | Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy | |
| CN206431615U (en) | A kind of fifo controller of multichannel read-write multicapacity selection | |
| CN101137246B (en) | Ultralarge scale data cross connection method in synchronous digital transmission system | |
| CN103561359A (en) | Multiple connection method and device for optical channel data unit | |
| CN101883046A (en) | Data cache architecture applied to EPON terminal system | |
| CN105955901A (en) | Enhancement-type large-capacity high-speed data exchange design method | |
| CN105007151A (en) | High/low-speed bus communication method and device | |
| KR20110029220A (en) | Fast memory controller | |
| CN101136710B (en) | Data storage control method of virtual cascade recover | |
| CN103731225A (en) | Data transmission method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |