CN102929829A - Information transfer device for computer hardware experiment - Google Patents
Information transfer device for computer hardware experiment Download PDFInfo
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- CN102929829A CN102929829A CN2012104703308A CN201210470330A CN102929829A CN 102929829 A CN102929829 A CN 102929829A CN 2012104703308 A CN2012104703308 A CN 2012104703308A CN 201210470330 A CN201210470330 A CN 201210470330A CN 102929829 A CN102929829 A CN 102929829A
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Abstract
The invention belongs to the technical field of computer teaching experimental instruments, and particularly relates to an information transfer device for a computer hardware experiment. The information transfer device comprises a computer, a USB-JTAG (Universal Serial Bus-Joint Test Action Group) protocol converter, an information transfer module and an experimental circuit, wherein the experimental circuit and the information transfer module are positioned in the same FPGA (Field Programmable Gate Array); and the experimental circuit is connected with the information transfer module and used for receiving an excitation signal sent by the information transfer module and sending an output response of the experimental circuit to the information transfer module. The information transfer device can transfer information through the internal logic of the experimental circuit, only requires 4 pins instead of a console consisting of singlechips and other auxiliary chips, is simple in hardware connection, low in cost, and excellent in universality, and is suitable for any FPGA; and the degree of freedom of the design of the experimental circuit is only restricted by the size of the FPGA chips per se, and the information transfer method has no demand on the internal structure of the experimental circuit, so that the development of innovative experiments is facilitated.
Description
Technical field
The invention belongs to computer teaching experimental apparatus technical field, be specifically related to a kind of information transfer device for computer hardware experiment, the education experiment of main computer-oriented theory of constitution, Computer Systems Organization also can be used for the experiment of the computer hardware series courses such as DLC (digital logic circuit), Computer Interface Technology.
Background technology
The information transmission of computer hardware experiment mainly contains two kinds, a kind of is to adopt machinery, the electronic component (CN1312526 such as button, toggle switch, light emitting diode, seven segment digital tubes, CN101059920), the main middle and small scale digital integrated circuit that adopts consists of experimental circuit, the experimenter directly operates at experimental provision, do not need to pass through computation, this method offers experimenter's input, the design restriction that output quantity is subject to experimental provision, thereby limited dirigibility and the design scale of experimenter's design, can not support tele-experimentation.Another kind is control desk and the compunlcation that installs by experiment, experimental circuit is usually by the extensive field programmable gate array of FPGA() take on, control desk can be single-chip microcomputer (CN1741094) or custom-designed FPGA(CN101290724), control desk is by specific logical and experimental circuit exchange message, and by RS232 or usb communication interface and computer transmission input/output information, the experimenter can operate on computers, therefore also might provide support for tele-experimentation (CN101814248A), because adopt FPGA as the experiment chip, the experimental design dirigibility is compared with first method with scale and is improved a lot; But the information transmission between control desk and the experimental circuit can only be according to the mode that designs in advance, usually require the experimental circuit internal register to be connected to the FPGA pin with the form of bus, the information that can transmit is limited, structure to experimental circuit also has certain requirement, even control chip in code be to make (CN101290724) to measure for particular experiment, limited to a certain extent experimenter's design and innovation ability; In addition, additional control desk circuit has also increased cost.The inventor once proposed to adopt Boundary-scan test technology as the means (Zhao Hui of experimental provision information transmission, Xiao Tiejun, the application of Boundary-scan test technology in hardware experiments, microcomputer information (embedded and SOC), the 23rd volume 8-2 phase p279-281 in 2007), utilize boundary scan chain and the experimental circuit exchange message of experiment fpga chip itself, do not need single-chip microcomputer etc. as control desk, simplified the hardware connection, effectively reduced hardware cost, but this method requires the boundary scan chain of FPGA to support the INTEST instruction, and its boundary-scan architecture all is fixing usually, can only scan access to the pin of chip itself, be not easy to the experimental circuit internal node of autonomous Design is conducted interviews, limited its range of application.In sum, adopt FPGA as testing chip, carrying out experimental implementation by computer, it is present computer hardware experimental facility design preferably, for the experimenter provides larger design space, support in theory innovative experiment, but for the internal logic transmission of information of experimental circuit, internal logic need to be drawn out on the external pin of chip, according to the predefined bus mode transmission of information of control desk, structure to experimental circuit has caused certain constraint, limit the degree of freedom of design, be unfavorable for carrying out of innovative experiment.
Summary of the invention
The limitation and the deficiency that exist at information transmitting methods for above-mentioned prior art Computer hardware experiments device, the present invention has designed a kind of information transfer device, this device can with experimental circuit internal logic transmission of information, and only need 4 pins, the control desk that does not need the additional chips such as single-chip microcomputer to consist of, hardware connects simple, and is with low cost, versatility is good, goes for any FPGA; The degree of freedom of experimental circuit design is only tested the restriction of fpga chip self scale, and information transmitting methods has no requirement to the experimental circuit inner structure, is conducive to carrying out of innovative experiment.
To achieve these goals, the present invention proposes a kind of information transfer device for computer hardware experiment, concrete technical scheme is as follows: a kind of information transfer device for computer hardware experiment, comprise computing machine, USB-JTAG protocol converter, information transfer module and experimental circuit, described computing machine is equipped with the experimental system debugged program, the experimenter can carry out debugging operations by debugged program, and shows that the experimenter wants the operating result of observing; Described USB-JTAG protocol converter and computing machine interconnect by USB interface, the serial data that USB-JTAG protocol converter receiving computer sends, send to information transfer module after the decoding, receive simultaneously the data of information transfer module, and send to computing machine, finish communicating by letter between information transfer module and the computing machine; Described information transfer module is positioned at FPGA inside, and with the USB-JTAG protocol converter between the JTAG standard four-wire interface that consists of by the I/O signal wire link to each other; Wherein one is the JTAG clock cable, and one is the JTAG control signal wire, and two other is respectively JTAG data input/output signal line.It is inner that described experimental circuit and information transfer module are positioned at same FPGA, and link to each other with information transfer module, receives the pumping signal that information transfer module is sent here, and give information transfer module with the output response of experimental circuit.
Further, above-mentioned information transfer module is comprised of TAP controller, order register, command decoder, data register; Wherein:
The TAP controller is used for producing the control signal that order register and data register are operated;
Order register and data register exist with the form of scan chain, finish moving in and out of data serial;
Data register is that designed being used for that require for the experiment information transmission applies the data excitation or catch the custom scan chain of experimental circuit internal circuit nodes data the experimental circuit internal circuit nodes, comprise three kinds on input scan chain, output scanning chain and bilateral scanning chain, wherein, the input scan chain is used for the experimental circuit internal node is applied excitation to change the logic state of experimental circuit, the output scanning chain is used for reading the information of experimental circuit internal node, and the bilateral scanning chain is used for both can applying excitation to the inside circuit node also can read its information;
Command decoder is deciphered the content of order register, produces the selection signal for different scanning chain in the data register.
Further, above-mentioned USB-JTAG protocol converter is made of main control chip and level switch module, and main control chip can be MCU(Micro Control Unit microcontroller) or CPLD (Complex Programmable Logic Device CPLD).
As one embodiment of the present of invention, when above-mentioned USB-JTAG protocol converter uses MCU as main control chip, the JTAG signaling interface of USB-JTAG protocol converter is comprised of two synchronous serial interfaces of MCU, one of them synchronous serial interface is as main equipment, another synchronous serial interface is finished reception and the transmission of JTAG signal as from equipment by its collaborative work.Wherein, the MCU in house software comprises usb data transceiver module, usb data parsing module and JTAG data transmit-receive module.Wherein, the usb data transceiver module is responsible for the data that receiving computer sends by USB interface, and when needs return experimental circuit node data information, sends and receives the experimental circuit node data information that self-information is transmitted module by USB interface to computing machine; The usb data parsing module is responsible for the Data Analysis that is received from computing machine is become the JTAG signal, and Data Analysis is to determine according to the data create-rule of experimental system debugging software in calculating; The JTAG signal data that the JTAG data transmit-receive module transmits the usb data parsing module by this simulation jtag interface TCK, TMS and TDI sends to information transfer module and receive information by TDO and to transmit the data that module is returned, after receiving the JTAG return data of specified quantity, be returned to the usb data transceiver module, send to computing machine by it.
The present invention is take FPGA as experiment carrying device, adopt JTAG standard four-wire interface, be easy to realize, compare with the method for the independent control desk such as existing employing single-chip microcomputer and have greater flexibility, on computers can be easily the state of experimental circuit is read and controls; Compare with the boundary-scan architecture that adopts FPGA itself, adopt self-defining boundary-scan architecture, can directly access the internal node of experimental circuit, and not need node to be seen is guided on the chip pin.In the process that information is transmitted, information transfer module adopts the common IO mouth of fpga chip, only needs four and gets final product, adopt the method for SCM﹠FPGA control desk to greatly reduce number of leads, hardware connects simple, and is with low cost, versatility is good, goes for any FPGA.The degree of freedom of experimental circuit design is only tested the restriction of fpga chip itself, and experimental provision self has no requirement to the experimental circuit inner structure, is conducive to carrying out of innovative experiment.
Description of drawings
Fig. 1 is existing information transfer device structural drawing;
Fig. 2 is information transfer device structural drawing of the present invention;
Fig. 3 is the realization of a specific embodiment of the present invention;
Fig. 4 is MCU software programming Module Division figure in the USB-JTAG protocol converter in the present invention's specific embodiment shown in Figure 3;
Fig. 5 is MCU software flow pattern in the USB-JTAG protocol converter in the present invention's specific embodiment shown in Figure 3;
Fig. 6 is the input scan chain structure in the present invention's specific embodiment shown in Figure 3;
Fig. 7 is the input scan cellular construction in the present invention's specific embodiment shown in Figure 6;
Fig. 8 is the output scanning chain structure in the present invention's specific embodiment shown in Figure 3;
Fig. 9 is the output scan cell structure in the present invention's specific embodiment shown in Figure 8;
Figure 10 is the bilateral scanning chain structure in the present invention's specific embodiment shown in Figure 3;
Figure 11 is the bilateral scanning cellular construction in the present invention's specific embodiment shown in Figure 10.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment.
Information transfer device of the present invention as shown in Figure 2 comprises computing machine, the USB-JTAG protocol converter, information transfer module and experimental circuit four parts, use USB to carry out data communication between computing machine and the USB-JTAG protocol converter, use 4 common I/O signal wires to finish data communication as jtag interface between USB-JTAG protocol converter and the information transfer module module.The present invention utilizes the control desk (as shown in Figure 1) of the additional chips such as USB-JTAG protocol converter, the alternative single-chip microcomputer of the prior art of information transfer module.
Further, computing machine is equipped with the experimental system debugged program, and the experimenter can carry out various debugging operations by debugged program, and shows that the experimenter wants the operating result of observing.The Frame that debugged program becomes experimenter's operational processes protocol converter to identify, its content comprise command code, data length and data three parts.The effect of command code is the state transitions of control TAP controller internal control state machine; What of the data that are transferred to jtag instruction register or data register data length be used for controlling, its size determined by the length of scan chain in the data register or order register, and what of the transmission quantity that is to say information information that to be the user will obtain or revise for concrete experimental circuit are determined; Data division is transferred to order register or data register then according to the state of TAP controller.
The USB-JTAG protocol converter is made of main control chip and level switch module, main control chip can be made of MCU or CPLD, present embodiment uses MCU as main control chip, be used for the serial data that receiving computer sends, send to information transfer module after the decoding, simultaneously also can receive the data of information transfer module, and send to computing machine, finish communicating by letter between information transfer module and the computing machine.The Frame that protocol converter is received from computing machine is comprised of command code, data length and data three parts, and protocol converter is decoded into the JTAG control signal according to decoding rule with command code, and according to data length data division is transferred to information transfer module.The interface of protocol converter and information transfer module is comprised of four common signal wires, and wherein one as the JTAG clock cable, and one as the JTAG control signal wire, and two other is as JTAG data input/output signal line.The JTAG signaling interface of protocol converter inside uses two of the MCU synchronous serial interfaces with synchronous clock transfer function to form, one of them synchronous serial interface is as main equipment, another synchronous serial interface is finished reception and the transmission of JTAG signal as from equipment by its collaborative work.
Information transfer module is comprised of TAP controller, order register, command decoder, data register according to IEEE 1149.1 JTAG standard design.The TAP controller is used for producing the control signal that order register and data register are operated.Order register and data register exist with the form of scan chain, and the serial of finishing data moves in and out; Data register is that designed being used for that require for the experiment information transmission applies the data excitation or catch the custom scan chain of experimental circuit internal circuit nodes data the experimental circuit internal circuit nodes; Command decoder is deciphered the content of order register, produces the selection signal for different scanning chain in the data register.Information transfer module has two kinds of operational modes: normal mode and debugging mode.Under normal mode, information transfer module can not exert an influence to the running status of experimental circuit; Under debugging mode, the running status of experimental circuit is controlled by information transfer module fully.Information transfer module adopts FPGA as carries chips.
Experimental circuit by experimenter's design, is implemented in on a slice FPGA with information transfer module.It links to each other with information transfer module in FPGA inside, receives the pumping signal that information transfer module is sent here, and gives information transfer module with the output response of experimental circuit.
In a specific embodiment of the present invention shown in Figure 3, computing machine and USB-JTAG protocol converter utilize USB interface to communicate.Link to each other by common I/O pin between information transfer module and the USB-JTAG protocol converter, have four signal line, be used for respectively carrying TCK, TMS, four JTAG signals of TDI and TDO, TCK wherein, TMS and TDI resolve the data that are received from computing machine by the USB-JTAG protocol converter and produce, after send to information transfer module, the internal node information that TDO catches experimental circuit by information transfer module produces, send to afterwards the USB-JTAG protocol converter, TCK and TMS are used for controlling the transfer of TAP controller state of a control machine, and be connected with the data register data input and the data that correspond to respectively scan chain of TDI and TDO and instruction register are exported.
Further, in the embodiment shown in fig. 3, the USB-JTAG protocol converter is made of MCU and level shifting circuit, and MCU is responsible for the protocol conversion between data receiver transmission and USB and the JTAG as main control chip; Level shifting circuit carries out level conversion according to the pin level standard of MCU and FPGA to the data that send between MCU and FPGA, play the effect of protection MCU and FPGA circuit.Input signal S_TCK, S_TMS, S_TDI and the TDO of level shifting circuit is corresponding with output signal TCK, TMS, TDI and S_TDO respectively, input signal JTAG_OE is the data transmission enable signal of level shifting circuit, the turn-on data transmission is responsible for closing data transmission when the JTAG_OE signal is effective; Level shifting circuit comprises data output and data input two parts, data output is used for S_TCK, S_TMS, S_TDI signal are carried out level conversion and produce TCK, TMS, TDI signal, and the data input is used for the TDO signal is carried out level conversion and produces the S_TDO signal.MCU uses its inner USB device and computing machine to communicate, MCU utilizes two interface SPI or USART simulation jtag interfaces with synchronous serial function, this routine USART is as main equipment, the SPI conduct is from equipment, finish reception and the transmission of JTAG signal by its collaborative work, this moment, USART-CK, SPI-SCK were connected to TCK, and USART-TX is connected to TMS, SPI-MISO is connected to TDI, and SPI-MOSI is connected to TDO.
Further, as shown in Figure 4, the MCU in house software comprises usb data transceiver module, usb data parsing module and JTAG data transmit-receive module.Wherein, the usb data transceiver module is responsible for the data that receiving computer sends by USB interface, and when needs return experimental circuit node data information, sends and receives the experimental circuit node data information that self-information is transmitted module by USB interface to computing machine; The usb data parsing module is responsible for the Data Analysis that is received from computing machine is become the JTAG signal, and Data Analysis is to determine according to the data create-rule of experimental system debugging software in calculating; The JTAG signal data that the JTAG data transmit-receive module transmits the usb data parsing module by this simulation jtag interface TCK, TMS and TDI sends to information transfer module and receive information by TDO and to transmit the data that module is returned, after receiving the JTAG return data of specified quantity, be returned to the usb data transceiver module, send to computing machine by it.The software flow of MCU is as shown in Figure 5:
The first step, system powers on, and MCU carries out initialization, comprises USB, SPI, USART and common I/O pin etc.
Second step judges whether USB device receives data, if the data of receiving entered for the 3rd step; If do not receive data, judge whether the JTAG data transmission is in opening, not when opening, reenter second step, if the JTAG data transmission is in opening, the beginning timing, and whether cycle detection receives data, if overtimely then set out mismark and entered for the 4th step, if do not have overtimely, then reenter second step.
In the 3rd step, judge whether the data frame type that receives is correct, if correctly entered for the 5th step, otherwise error flag is set and entered for the 4th step.
The 4th step entered the correction process program, carried out mistake according to error flag and processed.
The 5th step according to the difference of Frame sign, entered different Frame handling procedures, if start frame enables the JTAG data transmission and data passback sign is set; If the JTAG Frame sends the JTAG data, and reception information is transmitted the data of logic output when sending data; If end frame is closed the JTAG data transmission, select whether return data according to data passback sign, and the passback sign that clears data.Frame is disposed, and enters second step.
Further, as shown in Figure 3, information transfer module is by the TAP controller, order register, and command decoder, data register consists of.TAP controller in the information transfer module produces ClockIR, ShiftIR, UpdateIR, ClockDR, six control signals of ShiftDR, UpdateDR, and these six control signals are used for control instruction register and data register and carry out the operation that moves in and out of data.Order register and data register all are that the form with scan chain exists, and data move in and out in the mode of serial, and it all is take TDI as the input endpoint that data serial moves in and out, and TDO is exit point.Data register is that designed being used for that require for the experiment information transmission applies excitation or catch the self-defining data scan chain of experimental circuit internal circuit nodes state the experimental circuit internal circuit nodes, is divided into input scan chain, output scanning chain and bilateral scanning chain.The input scan chain is used for the experimental circuit internal node is applied excitation to change the logic state of experimental circuit, the output scanning chain is used for reading the information of experimental circuit internal node to be observed for the experimenter, and the bilateral scanning chain both can be used for that the inside circuit node was applied excitation and also can read its information and observe for the experimenter.Command decoder is deciphered the content of order register, produces the selection signal for different scanning chain in the data register.
Further, Figure 6 shows that the structural relation figure of input scan chain and experimental circuit, the input scan chain is by a plurality of input scan cell formations.When needs were revised the information of certain experimental circuit node, the output DataOut of input scan unit was connected to the input end of this node, and under debugging mode, the data of this node are provided by scan chain, thereby revised the information of this experimental circuit node.
Figure 7 shows that the input scan cellular construction.Under debugging mode, be that the MODE signal is when effective, the output of No. two selector switch MUX1 is data and the output after d type flip flop D2 latchs that moves into from the TDI serial under the effect of UpdateDR and ClockDR, the excited data that input scan this moment chain blocking experiment circuit applies this node, namely block the data input of DataIn, its excited data DataOut is applied by this input scan chain, thereby changes the logic state of experimental circuit; Under normal mode, the excited data DataOut of the corresponding experimental circuit node of input scan chain is directly transmitted by DataIn, and namely the input scan chain can not exert an influence to the experimental circuit operation.
Figure 8 shows that the structural relation figure of output scanning chain and experimental circuit, the output scanning chain is made of a plurality of output scan cells.When needs obtained the information of certain experimental circuit node, the input DataIn of output scan cell was connected on this node, and under debugging mode, this nodal information enters scan chain through DataIn, thereby obtained the information of this experimental circuit node.
Figure 9 shows that the output scan cell structure.Under debugging mode, the value of d type flip flop D1 is directly transmitted by DataIn under the effect of ClockDR and ShiftDR, and under displaced condition by TDO shifting out its serial, thereby the information of the experimental circuit node that acquisition will be obtained, no matter namely be at debugging mode or normal mode, the output scanning chain can not exert an influence to the logic state of experimental circuit.
Figure 10 shows that the structural relation figure of bilateral scanning chain and experimental circuit, the bilateral scanning chain is by a plurality of bilateral scanning cell formations.When the port that obtains or revise the experimental circuit node of information at needs is bidirectional port, use the bilateral scanning chain, the position of the experimental circuit node of bilateral scanning unit between the experimental circuit logical block, data terminal Data2 is connected on the experimental circuit node that needs modification or obtaining information, and data terminal Data1 is connected on the bidirectional port of another experimental circuit logical block that originally was connected to this experimental circuit node in the experimental circuit.
Figure 11 shows that the bilateral scanning cellular construction, Data1 and Data2 have realized the transmitted in both directions of data under the control of direction control signal Direction and scan chain mode signal MODE, the bilateral scanning chain both can apply the data excitation to the experimental circuit node at its place by Data2, has the function of input scan chain this moment, also can read from Data2 the data message of its place experimental circuit node, have the function of output scanning chain this moment.Under debugging mode, when bilateral scanning chain during as the input scan chain, the excited data of its place experimental circuit node and write control signal are moved into by the TDI serial, under the effect of ClockDR, latched by d type flip flop D1, under the UpdataDR effect, again latch through d type flip flop D2, after select and directly be delivered to Data2 by triple gate 2 through MUX2, thereby realize this experimental circuit node is applied excitation, finish debugging; When bilateral scanning chain during as the output scanning chain, the data message of its place experimental circuit node directly passes through DataIn by Data2, under the effect of ClockDR, enter d type flip flop D1, under the displaced condition in debugging mode by TDO the shifting out of its serial, thereby obtain the information of the experimental circuit node that will obtain.Under normal mode, the direct UNICOM of the DataIn of bilateral scanning chain and DataOut, at this moment, the bilateral scanning chain can not exert an influence to the experimental circuit operation.
The described embodiment of Fig. 3, its course of work is as follows:
At first, be installed in the Frame that the experimental system debugging software in the computing machine can be identified its operation generation USB-JTAG protocol converter according to the experimenter, and utilizing USB interface to send to the USB-JTAG protocol converter, these Frames comprise command code, data length and data three partial contents; Then, after the usb data transceiver module of USB-JTAG protocol converter receives these data that sent by USB interface by computing machine, according to the data layout resolution rules it is resolved to the JTAG signal by the usb data parsing module, comprise TCK, TMS and TDI signal, these signals send to information transfer module by the JTAG data transmit-receive module by the simulation jtag interface that SPI and USART synchronous serial interface form; The TAP controller of information transfer module is shifting between 16 TAP states under the control of the TCK that is received from the USB-JTAG protocol converter and tms signal, and can produce ClockIR at corresponding state TAP controller, ShiftIR, UpdateIR, ClockDR, ShiftDR, UpdateDR and Mode signal, order register can be at corresponding ClockIR, ShiftIR, receive jtag instruction by TDI under the UpdateIR signal controlling, data register then can be at ClockDR, ShiftDR, UpdateDR and Mode signal, under the control of command decoder by the TDI receive data and be moved into experimental circuit, receive simultaneously the data that shift out from experimental circuit, and by the counter JTAG data transmit-receive module of giving the USB-JTAG protocol converter of TDO; The JTAG data transmit-receive module of USB-JTAG protocol converter is after receiving the JTAG data of specified quantity, it is sent to the usb data transceiver module, the usb data transceiver module sends to computing machine to these data by USB interface, the experimental system debugging software receives these echo back datas and feeds back on the user interface, is beneficial to the experimenter and observes.
Claims (6)
1. information transfer device that is used for computer hardware experiment, it is characterized in that comprising computing machine, USB-JTAG protocol converter, information transfer module and experimental circuit, described computing machine is equipped with the experimental system debugged program, the experimenter can carry out debugging operations by debugged program, and shows that the experimenter wants the operating result of observing; Described USB-JTAG protocol converter and computing machine interconnect by USB interface, the serial data that USB-JTAG protocol converter receiving computer sends, send to information transfer module after the decoding, receive simultaneously the data of information transfer module, and send to computing machine, finish communicating by letter between information transfer module and the computing machine; Described information transfer module is positioned at FPGA inside, and with the USB-JTAG protocol converter between the JTAG standard four-wire interface that consists of by the I/O signal wire link to each other; It is inner that described experimental circuit and information transfer module are positioned at same FPGA, and link to each other with information transfer module, receives the pumping signal that information transfer module is sent here, and give information transfer module with the output response of experimental circuit.
2. the information transfer device for computer hardware experiment as claimed in claim 1 is characterized in that, described information transfer module is comprised of TAP controller, order register, command decoder, data register; Wherein:
The TAP controller is used for producing the control signal that order register and data register are operated;
Order register and data register exist with the form of scan chain, finish moving in and out of data serial;
Data register is that designed being used for that require for the experiment information transmission applies the data excitation or catch the custom scan chain of experimental circuit internal circuit nodes data the experimental circuit internal circuit nodes, comprise three kinds on input scan chain, output scanning chain and bilateral scanning chain, wherein, the input scan chain is used for the experimental circuit internal node is applied excitation to change the logic state of experimental circuit, the output scanning chain is used for reading the information of experimental circuit internal node, and the bilateral scanning chain is used for both can applying excitation to the inside circuit node also can read its information;
Command decoder is deciphered the content of order register, produces the selection signal for different scanning chain in the data register.
3. the information transfer device for computer hardware experiment as claimed in claim 1 is characterized in that, described USB-JTAG protocol converter is made of main control chip and level switch module, and main control chip can be MCU or CPLD.
4. the information transfer device for computer hardware experiment as claimed in claim 3, it is characterized in that, when the USB-JTAG protocol converter uses MCU as main control chip, the JTAG signaling interface of USB-JTAG protocol converter is comprised of two synchronous serial interfaces of MCU, one of them synchronous serial interface is as main equipment, another synchronous serial interface is finished reception and the transmission of JTAG signal as from equipment by its collaborative work.
5. such as claim 3 or 4 described information transfer devices for computer hardware experiment, it is characterized in that as MCU during as main control chip, the MCU in house software comprises usb data transceiver module, usb data parsing module and JTAG data transmit-receive module.Wherein, the usb data transceiver module is responsible for the data that receiving computer sends by USB interface, and when needs return experimental circuit node data information, sends and receives the experimental circuit node data information that self-information is transmitted module by USB interface to computing machine; The usb data parsing module is responsible for the Data Analysis that is received from computing machine is become the JTAG signal, and Data Analysis is to determine according to the data create-rule of experimental system debugging software in the computing machine; The JTAG signal data that the JTAG data transmit-receive module transmits the usb data parsing module by this simulation jtag interface TCK, TMS and TDI sends to information transfer module and receive information by TDO and to transmit the data that module is returned, after receiving the JTAG return data of specified quantity, be returned to the usb data transceiver module, send to computing machine by it.
6. the information transfer device for computer hardware experiment as claimed in claim 1, it is characterized in that, the JTAG standard four-wire interface that consists of by the I/O signal wire between described information transfer module and the USB-JTAG protocol converter links to each other, wherein one is the JTAG clock cable, article one, be the JTAG control signal wire, two other is respectively JTAG data input/output signal line.
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| CN103293992B (en) * | 2013-05-30 | 2015-08-05 | 徐渊 | USB flash disk formula FPGA development board |
| WO2016127953A1 (en) * | 2015-02-15 | 2016-08-18 | 浪潮电子信息产业股份有限公司 | Debugging method specifically for fpga of high-end fault-tolerant computer based on software-hardware architecture, and device thereof |
| CN108267681A (en) * | 2016-12-30 | 2018-07-10 | 上海复旦微电子集团股份有限公司 | A kind of module test system of programmable circuit |
| CN108267681B (en) * | 2016-12-30 | 2020-07-17 | 上海复旦微电子集团股份有限公司 | Module test system of programmable circuit |
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| CN112506832A (en) * | 2020-12-07 | 2021-03-16 | 天津津航计算技术研究所 | USB JTAG acquisition and downloading integrated device |
| CN112506832B (en) * | 2020-12-07 | 2023-03-10 | 天津津航计算技术研究所 | USB JTAG acquisition and downloading integrated device |
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