CN102929056A - Array substrate and manufacturing method and display device thereof - Google Patents
Array substrate and manufacturing method and display device thereof Download PDFInfo
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- CN102929056A CN102929056A CN2012104486857A CN201210448685A CN102929056A CN 102929056 A CN102929056 A CN 102929056A CN 2012104486857 A CN2012104486857 A CN 2012104486857A CN 201210448685 A CN201210448685 A CN 201210448685A CN 102929056 A CN102929056 A CN 102929056A
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Abstract
An embodiment of the invention provides an array substrate and a manufacturing method and a display device thereof, relates to the technical field of display and solves the problems that in the prior art, a public electrode line of a liquid crystal display device array substrate is large in resistance, and the liquid crystal display device s poor in display quality. The array substrate comprises a transparent substrate, a grid metal layer and a source leakage metal layer, wherein the grid metal layer and the source leakage metal layer are positioned on the transparent substrate, the grid metal layer comprises a grid line and a grid electrode, and the source leakage metal layer comprises a data line, a source electrode and a leakage electrode. The array substrate further comprises a public electrode line metal layer and an insulation layer, wherein the insulation layer is positioned between the public electrode line metal layer and the grid metal layer or between the public electrode line metal layer and the source leakage metal layer. The public electrode line metal layer comprises a plurality of public electrode lines which are arranged in a cross mode. The array substrate, the manufacturing method of the array substrate and the display device of the array substrate are suitable for designing and manufacturing array substrates and display devices.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of array base palte and manufacture method thereof, display device.
Background technology
In TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD) demonstration field, along with the continuous renewal of technology, display panels develops rapidly towards maximization at present.
Existing display panels, comprise array base palte, color membrane substrates and be arranged on array base palte and color membrane substrates between liquid crystal.As shown in Figure 1, the array base palte that is applied in TN (Twist Nematic, twisted-nematic) the type liquid crystal display comprises: grid line 1, data line 2, thin film transistor (TFT) 3, public electrode wire 4 and pixel electrode 5; Wherein, thin film transistor (TFT) 3 comprises grid 31, source electrode 32 and drains 33, and grid 31 links to each other with grid line 1, and source electrode 32 links to each other with data line 2, and drain electrode 33 links to each other with pixel electrode 5, public electrode wire 4 and be arranged on public electrode electrical connection on the color membrane substrates.
Above-mentioned public electrode wire 4 is divided into two kinds according to the direction of arranging, and a kind of is the first horizontal public electrode wire 41 and the second public electrode wire 42 longitudinally.Public electrode wire 4 common and above-mentioned grid lines 1 arrange with layer, and are electrically connected with grid line 1 nothing; In order to guarantee that public electrode wire 4 does not contact with grid line 1, the first horizontal public electrode wire 41 is parallel with grid line 1, and longitudinally the second public electrode wire 42 owing to can not contact with grid line 1, therefore be interrupted.In order to realize the longitudinally conducting of the second public electrode wire 42, need to be connected by connecting line 6 by via hole.Further in order to reduce the step in the manufacture craft, connecting line 6 and pixel electrode 5 arrange with layer usually, and the material of connecting line 6 is the same with the material of pixel electrode like this, is ITO (Indium tin oxide, tin indium oxide).
Yet, because ITO resistance is larger, add via hole technique and have certain bad factor, thereby, be easy to make the resistance value of public electrode wire integral body to increase, cause easily that display frame is partially green, the harmful effect of the aspects such as flicker and image retention, final so that the display quality of display panels is relatively poor.Especially for the display panels of large-size, the resistance of public electrode wire increases, and can have a strong impact on the display quality of display panels.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method thereof, display device, can reduce the resistance of public electrode wire on the array base palte, thereby improve the display quality of the display of using this array base palte.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The embodiment of the invention provides a kind of array base palte, comprising: transparency carrier, and metal level is leaked in the grid metal level, the source that are arranged on the described transparency carrier; Wherein, described grid metal level comprises: grid line and grid, described source leak metal level and comprise: data line, source electrode and drain electrode; Also comprise: public electrode wire metal level and insulation course; Described insulation course perhaps leaks between the metal level at described public electrode wire metal level and described source between described public electrode wire metal level and described grid metal level; Described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner.
Optionally, described public electrode wire metal level comprises: many first public electrode wires that are parallel to each other, and many second public electrode wires that are parallel to each other; Wherein, described the first public electrode wire and described the second public electrode wire intersect.
Optionally, the distance between two whenever adjacent the first public electrode wires equates, and the distance between two whenever adjacent the second public electrode wires equates.
Optionally, described the first public electrode wire is parallel with described grid line, and described the second public electrode wire is parallel with described data line.
Optionally, described array base palte also comprises: with the transparency conducting layer of the adjacent setting of described public electrode wire metal level, described transparency conducting layer comprises: the pattern of public electrode; Described public electrode directly contacts with described public electrode wire.
Optionally, there are the overlapping region in described public electrode and described public electrode wire.
Optionally, described transparency conducting layer also comprises: the pattern of pixel electrode, described pixel electrode and described drain electrode are electrically connected by via hole.
The embodiment of the invention provides a kind of display device, comprising: the array base palte that the embodiment of the invention provides.
The embodiment of the invention provides a kind of manufacture method of array base palte, comprise: the step that the grid metal level is set at transparency carrier, and the step that leakage metal level in source is set at transparency carrier, also comprise: the step that the public electrode wire metal level is set at transparency carrier; Wherein, described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner;
Between the described step and the described step that the grid metal level is set at transparency carrier that the public electrode wire metal level is set at transparency carrier, perhaps, describedly the step of public electrode wire metal level is set and describedly at transparency carrier the source is set and leaks between the step of metal level at transparency carrier, described manufacture method also comprises: the step that insulation course is set at transparency carrier.
Optionally, before or after the described step that the public electrode wire metal level is set at transparency carrier, also comprise: in the step of transparency carrier setting with the transparency conducting layer of the adjacent setting of described public electrode wire metal level, described transparency conducting layer comprises: the pattern of public electrode; Described public electrode directly contacts with described public electrode wire.
Optionally, described transparency conducting layer also comprises: the pattern of pixel electrode.
A kind of array base palte that the embodiment of the invention provides and manufacture method thereof, display device, in array base palte, public electrode wire is arranged on the public electrode wire metal level, in other words, be that public electrode wire is arranged on independent one deck, and do not arrange with layer with grid line or data line; Like this, public electrode wire connects by via hole and the connecting line that is arranged on interlayer with regard to need not, thereby can reduce the resistance of public electrode wire on the array base palte, and then improves the display quality of the display of using this array base palte.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the plan structure schematic diagram of a kind of array base palte of TN type liquid crystal display in the prior art;
Fig. 2 provides the plan structure schematic diagram of array base palte in a kind of ADS type liquid crystal display for the embodiment of the invention;
The plan structure schematic diagram of array base palte in a kind of IPS type liquid crystal display that Fig. 3 provides for the embodiment of the invention;
The plan structure schematic diagram of array base palte in a kind of TN type liquid crystal display that Fig. 4 provides for the embodiment of the invention;
Fig. 5-Fig. 8 is for making the plan structure schematic diagram in the array base palte process shown in Figure 2;
Fig. 9 is the plan structure schematic diagram of public electrode wire on the array base palte shown in Figure 4;
Figure 10 is the a-a` cross-sectional schematic of a kind of array base palte shown in Figure 2;
The method schematic diagram of a kind of manufacturing array substrate that Figure 11 provides for the embodiment of the invention.
Reference numeral:
The 1-grid line; The 2-data line; The 3-thin film transistor (TFT); The 4-public electrode wire; The 5-pixel electrode; The 6-connecting line; The 7-public electrode; The 8-transparency carrier; The 9-insulation course; The 10-gate insulation layer; The 11-active layer; The 12-protective seam; The 31-grid; The 32-source electrode; The 33-drain electrode; 41-the first public electrode wire; 42-the second public electrode wire.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.
In the embodiment of the invention " on ", the sequencing of D score during with the manufacturing array substrate be as the criterion, and for example, refers to relatively pattern in rear formation at upper pattern, under pattern refer to the pattern that relatively formerly forms.
The array base palte that the embodiment of the invention provides goes for organic light-emitting display device (OLED, Organic Light Emitting Display), also goes for liquid crystal indicator.Wherein, liquid crystal indicator utilizes electric field to control translucidus to show image by liquid crystal.According to the direction of an electric field that drives liquid crystal, liquid crystal indicator roughly is divided into vertical electric field driving driving with horizontal component of electric field.The vertical electric field electric field type liquid crystal display device is public electrode positioned opposite to each other and pixel electrode on upper and lower base plate, between described public electrode and pixel electrode, form vertical electric field to drive liquid crystal, such as TN (TwistNematic, twisted-nematic) type, VA (Vertical Alignment, multi-domain vertical alignment) type liquid crystal indicator.The horizontal component of electric field electric field type liquid crystal display device arranges public electrode and pixel electrode at infrabasal plate, between described public electrode and pixel electrode, form the electric field of level to drive liquid crystal, such as ADS (Advanced-Super Dimensional Switching, senior super dimension field switch) type, IPS (In Plane Switch, transverse electric field effect) type liquid crystal indicator.
In order to reduce the resistance of public electrode wire, with reference to the arbitrary accompanying drawing of figure 2-Fig. 4, the embodiment of the invention provides a kind of array base palte, comprising: transparency carrier, and metal level is leaked in the grid metal level, the source that are arranged on the described transparency carrier; Wherein, described grid metal level comprises: grid line 1 and grid 31, described source leak metal level and comprise: data line 2, source electrode 32 and drain 33; Also comprise: public electrode wire metal level and insulation course; Described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner 4.
In embodiments of the present invention, metal level, public electrode wire metal level and insulation course are leaked in above-mentioned grid metal level, source, are independent layer.The thin film that the implication of " layer " can refer to utilize a certain material to utilize the technique such as deposition to produce at substrate; Example insulation course described above can be that to deposit SiNx (silicon nitride) at transparency carrier prepared.The implication of " layer " can also refer to utilize a certain material to produce thin film in techniques such as substrate utilization depositions, and by the formed layer structure that comprises a plurality of patterns of composition technique; For example, above-mentioned grid metal level can refer to deposit molybdenum at transparency carrier, makes metallic film, and forms the layer structure that comprises grid line, grid by a composition technique; For another example, above-mentioned source is leaked metal level and can be referred to deposit molybdenum at transparency carrier, makes metallic film, and forms the layer structure that comprises data line, source electrode and drain electrode by a composition technique; And for example, above-mentioned public electrode wire metal level can be deposit metallic material on transparency carrier, makes metallic film, and forms the layer structure that comprises public electrode wire by a composition technique; And for example, above-mentioned insulation course can be made insulation film at transparency carrier deposition SiNx first according to actual needs, is removing part by composition technique at insulation film, forms via hole at ad-hoc location, makes insulation course.That is to say, in embodiments of the present invention, different layers are to be formed by different film (material is identical or different).
Above-mentioned source electrode, drain and gate are three electrodes of thin film transistor (TFT), according to the position relationship of electrode thin film transistor (TFT) are divided into two classes.One class grid is positioned at below source electrode and the drain electrode, and this class is referred to as bottom gate thin film transistor; One class grid is positioned at source electrode and above the drain electrode, this class is referred to as top gate type thin film transistor.
Because public electrode wire is for to the public electrode input voltage, so public electrode wire need to be electrically connected with public electrode.And public electrode wire does not generally link to each other with other conductive patterns, for example public electrode wire can not be electrically connected with the pattern on the grid metal level, can not be electrically connected with the pattern on the metal level of source, connect with the mistake of avoiding public electrode wire and other conductive patterns so insulation course need to be set.Below, in connection with two types of concrete positions of setting forth insulation course of thin film transistor (TFT).
At first, for the array base palte that is provided with bottom gate thin film transistor, if the public electrode wire metal level be arranged on the grid metal level below, then this insulation course need to be arranged between public electrode wire metal level and the grid metal level; If the public electrode wire metal level be arranged on the source leak metal level above, then insulation course need to be arranged on the public electrode wire metal level and the source is leaked between the metal level.
Secondly, for the array base palte that is provided with the top gate type thin film crystal, if the public electrode wire metal level be arranged on the source leak metal level below, then this insulation course need to be arranged on the public electrode wire metal level and the source is leaked between the metal level; If the public electrode wire metal level be arranged on the grid metal level above, then insulation course need to be arranged between public electrode wire metal level and the grid metal level.Described electrical connection is for realizing the conducting of circuit by modes such as direct contact, wire, via holes.
The array base palte that the embodiment of the invention provides is arranged on public electrode wire on the public electrode wire metal level, in other words, is that public electrode wire is arranged on independent one deck, and does not arrange with layer with grid line or data line; Like this, public electrode wire connects by via hole and the connecting line that is arranged on interlayer with regard to need not, thereby can reduce the resistance of public electrode wire on the array base palte, and then improves the display quality of the display device of using this array base palte.
In addition, the insulation course on the above-mentioned array base palte so that public electrode wire be not electrically connected with other conductive patterns, thereby guaranteed that the display that comprises above-mentioned array base palte can work.Moreover, because grid line and public electrode wire are arranged on the different layers, can shorten as required like this distance of grid line and public electrode wire, thereby can suitably increase pixel aperture ratio.
Preferably, such as the arbitrary accompanying drawing of Fig. 2-4, described public electrode wire metal level comprises: many first public electrode wires 41 that are parallel to each other, and many second public electrode wires 42 that are parallel to each other; Wherein, described the first public electrode wire 41 intersects with described the second public electrode wire 42.
Further, described the first public electrode wire 41 is parallel with described grid line 42, and described the second public electrode wire 42 is parallel with described data line.Public electrode wire the first public electrode wire 41 and the second public electrode wire 42 that form like this are orthogonal, as shown in Figure 6.Whole like this public electrode wire is as a whole, does not need to connect through via hole and the connecting line that is arranged on interlayer, can reduce the resistance of public electrode wire on the array base palte, and then improve the display quality of the display of using this array base palte.
Further, the distance between two whenever adjacent the first public electrode wires equates, and the distance between two whenever adjacent the second public electrode wires equates.The public electrode wire that arranges like this, since between every adjacent two the first public electrode wires with whenever adjacent two the second public electrode wires between distance all equate, the cancellated sizing grid of the public electrode wire that then forms is identical, public electrode wire has preferably homogeneity, can avoid significantly the skew of common electric voltage, thereby further improve the display quality of the display of using this array base palte.
Below, the structure the when embodiment of the invention will be applied to dissimilar display device for the above-mentioned array base palte that provides describes in detail.
The embodiment of the invention provides a kind of array base palte of the TN of being applied to type display device, and as shown in Figure 4, described array base palte comprises: transparency carrier, and metal level is leaked in the grid metal level, the source that are arranged on the described transparency carrier; Wherein, described grid metal level comprises: grid line 1 and grid 31, described source leak metal level and comprise: data line 2, source electrode 32 and drain 33; Also comprise: comprise the transparency conducting layer of pixel electrode pattern, and public electrode wire metal level and insulation course.
Described public electrode metal level comprises: many public electrode wires arranged in a crossed manner 4.Wherein, public electrode wire 4 can be with reference to above-mentioned description, does not add at this and gives unnecessary details.In addition, the position of insulation course equally can be with reference to above-mentioned description, does not add at this and gives unnecessary details.
Certainly, array base palte for TN type display device, in order to increase the aperture opening ratio of pixel, preferably, a lateral edges of the first public electrode wire arranges second public electrode wire on transparency carrier, the first public electrode wire and the second public electrode wire are arranged in a crossed manner, and the second public electrode wire is electrically connected with public electrode on being arranged on color membrane substrates by conducting resinl.But the resistance of public electrode wire is inhomogeneous like this, in order to obtain the public electrode wire of even resistance, further preferred, its public electrode wire 4 can also be as shown in Figure 9, the both sides of the edge of the first public electrode wire arrange respectively second public electrode wire on transparency carrier, and the second public electrode wire is electrically connected with public electrode on being arranged on color membrane substrates by conducting resinl.
Optionally, the public electrode wire metal level is positioned at below of array base palte, and this insulation course covers this public electrode wire metal level.Smaller to the change of whole manufacturing process like this, be not this kind implementation but do not limit in embodiments of the present invention.
The electrical connection of above-mentioned each pattern is: grid line 1 is electrically connected by the mode that directly contacts with grid 31, and data line 2 is electrically connected by the mode that directly contacts with source electrode 32, and drain electrode 33 can be electrically connected by via hole with pixel electrode 5.In addition, because the public electrode of TN type display device is arranged on the color membrane substrates, so the public electrode wire 4 on the above-mentioned array base palte can be electrically connected by conducting resinl and public electrode.
For the array base palte that is applied to ADS type or IPS type display device, such as Fig. 2, shown in Figure 3, need to arrange public electrode 7 and pixel electrode 5 at array base palte.Such array base palte also comprises: with the transparency conducting layer of the adjacent setting of described public electrode wire metal level, described transparency conducting layer comprises: the pattern of public electrode 7; Preferably, described public electrode 7 directly contacts with described public electrode wire 4.Like this, the conductive structure that does not need to re-use other just can directly be realized being electrically connected of public electrode 7 and public electrode wire 4, because not needing other conductive structure, therefore can reduce the step in the array base palte processing procedure.
Wherein, directly contact can be the adjacent and contacts of two patterns, can also refer to that two patterns exist partly or entirely overlapping and contact.In embodiments of the present invention, be preferably, cut-open view as shown in figure 10, there are the overlapping region in described public electrode 7 and described public electrode wire 4.Public electrode 7 can better contact with public electrode wire 4 like this, realizes the circuit turn-on between public electrode 7 and the public electrode wire 4.
Concrete, the embodiment of the invention provides a kind of array base palte of the ADS of being applied to type display device, and as shown in Figure 2, described array base palte comprises: transparency carrier, metal level is leaked in the grid metal level, the source that are arranged on the described transparency carrier; Wherein, described grid metal level comprises: grid line 1 and grid 31, described source leak metal level and comprise: data line 2, source electrode 32 and drain 33; Also comprise: public electrode wire metal level and insulation course; Described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner 4.In addition, also comprise: two-layer transparency conducting layer; Wherein a transparency conducting layer comprises the pattern of public electrode 7, and the setting adjacent with the public electrode wire metal level of this transparency conducting layer; Another transparency conducting layer comprises the pattern of pixel electrode 5.
As shown in Figure 6, described public electrode metal level comprises: many public electrode wires arranged in a crossed manner 4.Wherein, public electrode wire 4 can be with reference to above-mentioned description, does not add at this and gives unnecessary details.In addition, the position of insulation course equally can be with reference to above-mentioned description, does not add at this and gives unnecessary details.
Optionally, comprise the transparency conducting layer of public electrode 7 patterns and public electrode wire metal level and be and be positioned at below two-layer of array base palte, this is two-layer and this insulation course covers.Smaller to the change of whole manufacturing process like this.Further, as shown in figure 10, the transparency conducting layer that comprises public electrode 7 patterns is positioned at the below of array base palte, and the public electrode wire metal level is positioned on this transparency conducting layer, and insulation course covers that this is two-layer.Be not this kind implementation but do not limit in embodiments of the present invention.
The electrical connection of above-mentioned each pattern is: grid line 1 is electrically connected by the mode that directly contacts with grid 31, data line 2 is electrically connected by the mode that directly contacts with source electrode 32, drain electrode 33 can be electrically connected by via hole with pixel electrode 5, and public electrode wire 4 is electrically connected in the mode that directly contacts with public electrode 7.
For the array base palte of ADS type liquid crystal indicator, be to form multi-dimensional electric field by public electrode 7 and the pixel electrode 5 that is arranged on the described array base palte, make liquid crystal molecule can both produce rotation, realize Presentation Function.And to form multi-dimensional electric field, and being formed with a plurality of slits on the electrode above being positioned in two electrodes, the electrode that is positioned at the below can be plate shaped or be formed with a plurality of slits.If the electrode of top is electrically connected with drain electrode 33, then this electrode is pixel electrode; At this moment, the electrode of below need to be electrically connected with public electrode wire 4, and this electrode is public electrode.On the contrary, the electrode that is positioned at the top can make public electrode, at this moment, is positioned at the electrode of below as pixel electrode.
Example, as shown in Figure 2, be formed with a plurality of slits on the pixel electrode 5 above being positioned in the present embodiment, be positioned at the public electrode 7 of below for plate shaped.In the situation that circuit turn-on, pixel electrode 5 can form multi-dimensional electric field with public electrode 7.
Concrete, the embodiment of the invention provides a kind of array base palte of the IPS of being applied to type display device, and as shown in Figure 3, described array base palte comprises: transparency carrier, metal level is leaked in the grid metal level, the source that are arranged on the described transparency carrier; Wherein, described grid metal level comprises: grid line 1 and grid 31, described source leak metal level and comprise: data line 2, source electrode 32 and drain 33; Also comprise: public electrode wire metal level and insulation course; Described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner 4.In addition, also comprise: a transparency conducting layer, described transparency conducting layer comprises: the pattern of the pattern of public electrode 7 and pixel electrode 5.
As shown in Figure 3, described public electrode metal level comprises: many public electrode wires arranged in a crossed manner 4.Wherein, public electrode wire 4 can be with reference to above-mentioned description, does not add at this and gives unnecessary details.In addition, the position of insulation course equally can be with reference to above-mentioned description, does not add at this and gives unnecessary details.
Optionally, comprise the transparency conducting layer of public electrode 7 patterns and pixel electrode 5 patterns and public electrode wire metal level and be and be positioned at below two-layer of array base palte, this is two-layer and this insulation course covers.Smaller to the change of whole manufacturing process like this.Further, this transparency conducting layer is positioned at the below of array base palte, and the public electrode wire metal level is positioned on this transparency conducting layer, and insulation course covers that this is two-layer.Be not this kind implementation but do not limit in embodiments of the present invention.
The electrical connection of above-mentioned each pattern is: grid line 1 is electrically connected by the mode that directly contacts with grid 31, data line 2 is electrically connected by the mode that directly contacts with source electrode 32, drain electrode 33 can be electrically connected by via hole with pixel electrode 5, and public electrode wire 4 is electrically connected in the mode that directly contacts with public electrode 7.
Different from the displaying principle of ADS type liquid crystal indicator, IPS type liquid crystal indicator is the electric field driven liquid crystal by the public electrode 7 on the array base palte and pixel electrode 5 formation levels, thereby realizes Presentation Function.And to form the electric field of level, public electrode 7 and pixel electrode 5 need be arranged on same layer, as shown in Figure 3, described pixel electrode 5 comprise respectively a plurality of electrical connection strip electrodes with described public electrode 7, form pectination as shown in Figure 3, the strip electrode of pixel electrode 5 and the parallel alternative arrangement of the strip electrode of public electrode 7 and between have the slit not contact with assurance adjacent bar electrode.Be pixel electrode with drain electrode 33 electrodes that are electrically connected wherein; At this moment, the electrode relative with this electrode need to be electrically connected with public electrode wire 4, is public electrode.
Need to prove, show emphatically part related to the present invention in institute's drawings attached of the embodiment of the invention, other parts are not shown.
In addition, array base palte provided by the invention can also be applied to VA type display device, and among the OLED, those skilled in the art are by the description of various embodiments of the present invention and in conjunction with prior art, can clearly understand the structure of the array base palte that is applied to these two kinds of display device, therefore do not describe in detail one by one in embodiments of the present invention.
Below, the embodiment of the invention also provides a kind of manufacture method of making above-mentioned array base palte, need to prove, the layer structure of above-mentioned array base palte finished by following steps, is not described in detail therefore in the following embodiments the concrete pattern of each layer and circuit are connected.
The embodiment of the invention provides a kind of manufacture method of array base palte, comprising: the step (S101) of grid metal level is set at transparency carrier, and at transparency carrier the step (S102) that metal level is leaked in the source is set; Also comprise: the step (S103) that the public electrode wire metal level is set at transparency carrier; Wherein, described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner.
For any liquid crystal indicator, public electrode wire is the public electrode input voltage, so public electrode wire need to be electrically connected with public electrode, and does not link to each other with other conductive patterns, then described manufacture method also comprises: the step (S104) that insulation course is set at transparency carrier.
In addition, no matter for the array base palte of which kind of type, also need between step S101 and step S102, at transparency carrier active layer be set.And, for so that not conducting between the conductive pattern that need not be electrically connected may also need to arrange other insulation courses on transparency carrier.The manufacturing step that those skilled in the art can clearly also need in conjunction with prior art does not elaborate in the present embodiment.
The sequencing of above-mentioned four steps can be decided according to the actual requirements, and the structure of the array base palte that different sequencings produces can be different.
Concrete, as shown in figure 11, for the array base palte that is provided with the bottom gate thin film crystal, described manufacture method can may further comprise the steps successively: step S103, step S104, step S101, step S102.Carry out successively the array base palte that above step forms, the public electrode wire metal level is positioned at the orlop of array base palte, insulation course is positioned at the last layer of public electrode wire metal level, and the grid metal level is positioned at the last layer of insulation course, and the upper strata that metal level is positioned at the grid metal level is leaked in the source.Described last layer can be adjacent two-layer, is positioned at top one deck and is referred to as last layer; Described upper strata can be for also being provided with other layers between the two-layer pattern, the one deck that is positioned at above other layers is referred to as the upper strata.
Like this, insulation course is between public electrode wire metal level and grid metal level, and then public electrode wire and grid can not form electrical connection, thereby guarantees that the display that comprises above-mentioned array base palte can work.
Optionally, for the array base palte that is provided with the bottom gate thin film crystal, described manufacture method can may further comprise the steps successively: step S101, step S102, step S104, step S103.Carry out successively on the array base palte of above step formation, the grid metal level is positioned at the orlop of array base palte, and the upper strata that metal level is positioned at the grid metal level is leaked in the source, and insulation course is positioned at the last layer that metal level is leaked in the source, and the public electrode wire metal level is positioned at the last layer of insulation course.Like this, insulation course leaks between metal level and the public electrode wire metal level in the source, and then source electrode, drain electrode and data line can not form with public electrode wire and be electrically connected, thereby guarantee that the display that comprises above-mentioned array base palte can work.
Optionally, for the array base palte that is provided with the top gate type thin film crystal, described manufacture method can may further comprise the steps successively: step S103, step S104, step S102, step S101.Carry out successively the array base palte that above step forms, the public electrode wire metal level is positioned at the orlop of array base palte, insulation course is positioned at the last layer of public electrode wire metal level, and the last layer that metal level is positioned at insulation course is leaked in the source, and the grid metal level is positioned at the upper strata that metal level is leaked in the source.Like this, insulation course is between public electrode wire metal level and grid metal level, and then public electrode wire and grid can not form electrical connection, thereby guarantees that the display that comprises above-mentioned array base palte can work.
Optionally, for the array base palte that is provided with the top gate type thin film crystal, described manufacture method can may further comprise the steps successively: step S101, step S102, step S103, step S104.Carry out successively the array base palte that above step forms, the grid metal level is positioned at the orlop of array base palte, and the upper strata that metal level is positioned at the grid metal level is leaked in the source, and insulation course is positioned at the last layer that metal level is leaked in the source, and the public electrode wire metal level is positioned at the last layer of insulation course.Like this, insulation course leaks between metal level and the public electrode wire metal level in the source, and then source electrode, drain electrode and data line can not form with public electrode wire and be electrically connected, thereby guarantee that the display that comprises above-mentioned array base palte can work.
Above-mentioned manufacture method can be applicable to the liquid crystal indicator of any type, and further, the embodiment of the invention also is elaborated for the setting of pixel electrode or public electrode in the different type arrays substrates.
If make the array base palte in the TN type display device, also need to arrange the transparency conducting layer that one deck comprises pixel electrode pattern.Example; can after finishing above-mentioned four steps, layer protective layer (also being the layer structure that plays insulating effect) be set, and this protective seam is provided with the via hole that is communicated with drain electrode; the transparency conducting layer that comprises pixel electrode pattern is set again, so that pixel electrode links to each other with drain electrode.
If make the array base palte in the ADS type display device, also need two-layer transparency conducting layer is set, wherein one deck includes pixel electrode pattern, and another layer includes the public electrode pattern.If want so that public electrode directly contacts with public electrode wire, optionally, before or after the described step (S103) that the public electrode wire metal level is set at transparency carrier, also comprise: in the step of transparency carrier setting with the transparency conducting layer of the adjacent setting of described public electrode wire metal level, this transparency conducting layer comprises: the pattern of public electrode.Further, example, finish above-mentioned institute in steps after, layer protective layer is set, and this protective seam is provided with the via hole that is communicated with drain electrode, the transparency conducting layer that comprises pixel electrode pattern is set again, so that pixel electrode links to each other with drain electrode.
If make the array base palte in the IPS type display device, also need to arrange the transparency conducting layer that one deck had not only included the public electrode pattern but also included pixel electrode pattern.Optionally, before or after the described step (S103) that the public electrode wire metal level is set at transparency carrier, also comprise: in the step of transparency carrier setting with the transparency conducting layer of the adjacent setting of described public electrode wire metal level, this transparency conducting layer comprises: the pattern of public electrode and the pattern of pixel electrode, at this moment, pixel electrode can make pixel electrode be electrically connected with drain electrode by the via hole that arranges on the insulation course.
Below, take ADS type liquid crystal indicator as example in detail, the manufacture method of the array base palte of described device is described in detail, wherein, the thin film transistor (TFT) of described array base palte be bottom gate type and public electrode metal level be arranged on the grid metal level below.
Concrete, the method for making this array base palte may further comprise the steps:
Example, deposit transparent conductive material on transparency carrier, for example tin indium oxide ITO, form transparent conductive film, according to pixel distribution, form transparency conducting layer by a composition technique, this transparency conducting layer comprises among Fig. 4 public electrode 7 patterns with array format.
Example, make a metallic film at transparency carrier, form at least public electrode wire 4 among Fig. 6 by composition technique, and public electrode wire 4 comprises the first horizontal public electrode wire 41 and the second public electrode wire 42 longitudinally.For the good contact of public electrode 7 and public electrode wire 4, there is the overlapping region in both, and are preferred, and all there are the overlapping region in the first public electrode wire 41 and the second public electrode wire 42 with public electrode 7.
Described grid metal level comprises: the pattern of grid line 3 and grid 31, wherein grid 31 can be the part of grid line 3.
Example, make metallic film at insulation course 9, and by a composition technique, form the grid metal level.
Example, on the transparency carrier 8 that is formed with the grid metal level, make semiconductive thin film, and above grid, form active layer 11 by a composition technique.
Described source is leaked metal level and comprised: data line 2, source electrode 32 and 33 the pattern of draining, wherein, source electrode 32 links to each other with data line 2.
Example, on the transparency carrier 8 that is formed with active layer 11, metallic film is leaked in the making source, and leaks metal level by a composition technique formation source.
Step 8, as shown in figure 10 arranges protective seam 12 at transparency carrier 8.
Example, make insulation film at transparency carrier 8, and by composition technique, remove the part that is positioned in the drain electrode, form the protective seam 12 that is provided with via hole.
Step 9, such as Fig. 2, shown in Figure 10, the transparency conducting layer of the pattern include pixel electrode 5 is set at transparency carrier.
Example, to make transparent conductive film at transparency carrier 8, and by a composition technique, form the pattern of pixel electrode 5, this pixel electrode 5 links to each other with described drain electrode 33 by via hole.
The step of above-mentioned making array base palte is also not only limited to above-mentioned description, for example, can also carry out first step S102 and carry out step S101 again, as long as realize the conducting of public electrode and public electrode wire.
The manufacture method of a kind of array base palte that the embodiment of the invention provides, described manufacture method comprises: the step of public electrode wire metal level is set, and public electrode wire is separately one deck like this, and does not arrange with layer with grid line or data line; Public electrode wire connects by via hole and the connecting line that is arranged on interlayer with regard to need not, thereby can reduce the resistance of public electrode wire on the array base palte, and then improves the display quality of the display device of using this array base palte.In addition, connect for fear of the mistake of public electrode wire and other conductive patterns, thereby guaranteed that the display that comprises above-mentioned array base palte can work, described manufacture method also comprises: the step that insulation course is set.Moreover, since grid line and public electrode wire at twice step arrange respectively, can shorten as required like this distance of grid line and public electrode wire, thereby can suitably increase pixel aperture ratio.
The embodiment of the invention also provides a kind of display device, comprising: any array base palte that the embodiment of the invention provides, described array base palte can be obtained by the method for making that the embodiment of the invention provides.Described display device can be any product or parts with Presentation Function such as liquid crystal display, LCD TV, digital camera, mobile phone, panel computer.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (11)
1. array base palte comprises: transparency carrier, and metal level is leaked in the grid metal level, the source that are arranged on the described transparency carrier; Wherein, described grid metal level comprises: grid line and grid, described source leak metal level and comprise: data line, source electrode and drain electrode; It is characterized in that, also comprise: public electrode wire metal level and insulation course; Described insulation course perhaps leaks between the metal level at described public electrode wire metal level and described source between described public electrode wire metal level and described grid metal level;
Described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner.
2. array base palte according to claim 1 is characterized in that, described public electrode wire metal level comprises: many first public electrode wires that are parallel to each other, and many second public electrode wires that are parallel to each other; Wherein, described the first public electrode wire and described the second public electrode wire intersect.
3. array base palte according to claim 2 is characterized in that, the distance between two whenever adjacent the first public electrode wires equates, and the distance between two whenever adjacent the second public electrode wires equates.
4. array base palte according to claim 2 is characterized in that, described the first public electrode wire is parallel with described grid line, and described the second public electrode wire is parallel with described data line.
5. each described array base palte is characterized in that according to claim 1-4, and described array base palte also comprises: with the transparency conducting layer of the adjacent setting of described public electrode wire metal level, described transparency conducting layer comprises: the pattern of public electrode;
Described public electrode directly contacts with described public electrode wire.
6. array base palte according to claim 5 is characterized in that, there are the overlapping region in described public electrode and described public electrode wire.
7. array base palte according to claim 5 is characterized in that, described transparency conducting layer also comprises: the pattern of pixel electrode, described pixel electrode and described drain electrode are electrically connected by via hole.
8. a display device is characterized in that, comprising: each described array base palte of claim 1-7.
9. the manufacture method of an array base palte comprises: the step of grid metal level is set at transparency carrier, and at transparency carrier the step that metal level is leaked in the source is set, it is characterized in that, also comprise: the step that the public electrode wire metal level is set at transparency carrier; Wherein, described public electrode wire metal level comprises: many public electrode wires arranged in a crossed manner;
Between the described step and the described step that the grid metal level is set at transparency carrier that the public electrode wire metal level is set at transparency carrier, perhaps, describedly the step of public electrode wire metal level is set and describedly at transparency carrier the source is set and leaks between the step of metal level at transparency carrier, described manufacture method also comprises: the step that insulation course is set at transparency carrier.
10. according to 9 described manufacture methods, it is characterized in that, before or after the described step that the public electrode wire metal level is set at transparency carrier, also comprise:
In the step of transparency carrier setting with the transparency conducting layer of the adjacent setting of described public electrode wire metal level, described transparency conducting layer comprises: the pattern of public electrode; Described public electrode directly contacts with described public electrode wire.
11. according to 10 described manufacture methods, it is characterized in that, described transparency conducting layer also comprises: the pattern of pixel electrode.
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