CN102928761B - Wafer sort system and crystal round test approach - Google Patents
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Abstract
A kind of wafer sort system and crystal round test approach, wherein, wafer sort system comprises: probe card and probe sanding apparatus; Wafer test machine, described wafer test machine comprises control module; Described probe card receives the test signal that described wafer test machine sends, and the chip to be measured in wafer is tested, and after test, test result is fed back to described wafer test machine, and described test result comprises the source leakage forward conduction voltage drop VFSD of chip to be measuredTo be measured; When occurring continuously VFSDTo be measuredLeak the standard pressure drop VFSD of forward conduction higher or lower than sourceStandardTime, stopping test, probe sanding apparatus is polished to described probe card described in described control module control; After polishing, carry out the test of next chip to be measured. The present invention, by the precision on opportunity of probe polishing, more accurately evades the impact of probe oxide layer on test result, and has further improved accuracy and the authenticity of wafer sort result, and improved testing efficiency.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to wafer sort field.
Background technology
Semiconductor test technique belongs to the key area of semiconductor industry, and semiconductor test comprises CP(CircuitProbe) test, CP(CircuitProbe) test also claims wafer sort (wafertest), is semiconductorThe first step of road packaging and testing after device, object is that the bad chip in wafer is picked out.
Conventionally, wafer refers to make the silicon chip of used in integrated circuits, and the integrated circuit on wafer has all been madeCheng Hou, comprises several chips on wafer. In On-Wafer Measurement step, just need to carry out described chipTesting electrical property, to guarantee that the chip on wafer is qualified products before encapsulation, therefore wafer sort isImprove one of committed step of semiconductor devices yield.
In the prior art, normally utilize a probe card with some probes, by described probe cardChip on probe and wafer electrically contacts to carry out testing electrical property. Particularly, on described chip, be provided with surveyTest weld point (pad), described probe and pad need to be in contact with one another, and just can complete testing electrical property.
But, in probe card long process, there is maximum error compared with between test result and predetermined result,Reduce true rate and the accuracy rate of wafer sort result, when serious, even chip can have been burnt out. If willInaccurate test data offers client, finally can bring prestige and economic loss to chip maker.
It is CN that more information about probe please refer on November 25th, 2009 disclosed publication numberThe Chinese patent literature of 101587165A.
Summary of the invention
The problem that the present invention solves is that the accuracy rate of wafer sort result of prior art is lower.
For addressing the above problem, the invention provides a kind of new wafer sort system, comprising:
Probe card and probe sanding apparatus;
Wafer test machine, described wafer test machine comprises control module;
Described probe card receives the test signal that described wafer test machine sends, to the chip to be measured in waferTest, after test, test result is fed back to described wafer test machine, described test result comprises to be treatedForward conduction voltage drop VFSD is leaked in the source of surveying chipTo be measured；
When occurring continuously VFSDTo be measuredLeak the standard pressure drop VFSD of forward conduction higher or lower than sourceStandardTime,Stop test, probe sanding apparatus is polished to described probe card described in described control module control; BeatAfter mill, carry out the test of next chip to be measured.
Optionally, described wafer test machine also comprises comparing unit;
Described comparing unit is by described VFSDStandardWith VFSDTo be measuredCompare output comparison signal;
Described control module, obtains and records described comparison signal, when occurring continuously VFSDTo be measuredHigher than orLower than VFSDStandardComparison signal time, output control signal, control described probe sanding apparatus to describedProbe card is polished.
Optionally, described wafer test machine also comprises memory cell, stores the VFSD of described probe card testTo be measured, described standard pressure drop VFSDStandard；
Described control module also comprises: reading unit reads described VFSD from described memory cellTo be measured、Described standard pressure drop VFSDStandard；
Described comparing unit obtains VFSD from described reading unitTo be measured, described standard pressure drop VFSDStandardAfter,Relatively VFSDTo be measuredWith described standard pressure drop VFSDStandard。
Optionally, described probe sanding apparatus comprises sand paper.
Optionally, the described VFSD that occurs continuouslyTo be measuredHigher or lower than standard pressure drop VFSDStandardCore to be measuredThe number range of sheet is: account for 2%～4% of all core numbers in wafer.
Optionally, described VFSDTo be measuredHigher or lower than described VFSDStandard, comprise scope: higher than or lowIn VFSDStandard3%
Optionally, described wafer test machine also comprises input block and display unit;
Described input block is for input test parameter, described wafer test machine according to described test parameter toDescribed probe card is sent test signal;
Described display unit is used for showing described test result.
Optionally, described test parameter comprises: described standard pressure drop VFSDStandard, source drain breakdown voltage,Ratio between regulation drain voltage and leakage current.
The present invention also provides a kind of crystal round test approach, comprising:
Wafer is provided, and described wafer comprises some chips to be measured;
Send test signal to probe card, described probe card receives some in wafer of described test signalChip to be measured is tested successively;
After each chip testing to be measured, output test result, described test result comprises chip to be measuredSource leak forward conduction voltage drop VFSDTo be measured；
When occurring continuously VFSDTo be measuredHigher or lower than standard pressure drop VFSDStandardTime, stop test, to instituteStating probe card polishes; After having polished, continue chip to be measured to test.
Optionally, also comprise: by described VFSDStandardWith VFSDTo be measuredCompare output comparison signal;
Obtain and record described comparison signal, when occurring continuously VFSDTo be measuredPress higher or lower than described standardVFSD fallsStandardComparison signal time, described probe card is polished.
Optionally, also comprise, store described standard pressure drop VFSDStandard; Often complete once test, by instituteState VFSDStandardWith VFSDTo be measuredBefore comparing, also comprise: the pressure drop of storing described probe card testVFSDTo be measured；
Obtain the described VFSD of storageStandard、VFSDTo be measuredAfterwards, by described VFSDStandardWith VFSDTo be measuredCompare.
Optionally, the described pressure drop VFSD that occurs continuouslyTo be measuredHigher or lower than standard pressure drop VFSDStandardTreatThe number range of surveying chip is: account for all chip count objects 2%～4% in wafer.
Optionally, described VFSDTo be measuredHigher or lower than described VFSDStandard, comprise scope: higher than or lowIn VFSDStandard3%.
Compared with prior art, the present invention has the following advantages:
Wafer sort system of the present invention arranges control module, for controlling probe sanding apparatus to probe cardAutomatically polish. When forward conduction voltage drop VFSD is leaked in the source of continuous appearance chip to be measuredTo be measuredWith establish in advanceThe standard pressure drop VFSD of forward conduction is leaked in the source of fixed qualified chipStandardTime, stop test, described controlUnit controls probe sanding apparatus carries out automatically grinding to the probe in probe card, removes the oxygen of detecting probe surfaceChange layer. Compared with setting fixing polishing frequency with prior art, the precision on opportunity that the present invention polishes probe,More accurately evade probe oxide layer and stain the impact on test result. Eliminate the shadow that probe oxide layer is stainRing, further improved accuracy and the authenticity of wafer sort result, and improved testing efficiency.
In specific embodiment, set 2%～4% the chip to be measured that occurs continuously accounting for all chips of waferVFSDTo be measuredHigher or lower than VFSDStandardTime, control module is just controlled probe polishing unit to probe cardPolish. In view of the detecting probe surface of probe card occurs that it is successional that oxide layer is stain, therefore, this realityExecute the quantity of setting the chip to be measured that occurs continuously oxide layer contamination in example, can further improve test effectRate, reduces the wafer sort time. And, also further avoid the waste of chip, cost-saving.
Brief description of the drawings
Fig. 1 is the structural representation of the wafer sort system of the specific embodiment of the invention;
Fig. 2 is the structural representation of the wafer test machine of the specific embodiment of the invention;
Fig. 3 is the schematic flow sheet of the crystal round test approach of the specific embodiment of the invention.
Detailed description of the invention
Inventor is studied for the inaccurate problem of wafer sort result, finds: in the prior art,Pass through long-time use, probe, especially needle point are exposed in air, understand by airborne dioxygen oxidation,And form layer of oxide layer on the surface of probe. Use this probe with oxide layer to proceed electrical surveyExamination, causes test result to occur maximum error. Therefore,, for above shortcoming, in the prior art, depositProbe is being polished, to remove the improvement of the oxide layer on probe. In concrete production, conventionally establishA fixed fixing probe polishing frequency, completes after the chip or wafer sort of some, such asCompleting after 100 chips or wafer sort, probe is polished. But, to fixing probe polishingThe setting of frequency, not an accurate standard. That is to say, survey at the wafer that carries out how many numbersExamination, or carry out after the chip testing of how many numbers on wafer, carry out probe technique for grinding No. one time,Just a random process of selecting, is not deterministic. This will cause: if probe polishing frequentlyRate is lower, and probe polishing step does not just have the effect that will improve wafer sort data accuracy rate; If crossedHeight, meeting greatly reduces the efficiency of wafer sort, also can affect the service life of probe. In practice, onState the accuracy rate that improvement does not promote wafer sort result. And, because capping oxidation layer on probe isA continuous process, stains oxidation if go out the oxide layer of detecting probe surface between the twice probe polishing in front and backLayer affect meeting long lasting effect test result, that is to say before and after may occurring between twice probe polishingThere is maximum error in the test result of some chips to be measured.
Therefore, fixing polishing frequency does not solve the problem that test result accuracy rate is lower. Inventor's warpCross creative work, invented a kind of new wafer sort system and crystal round test approach.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawingThe specific embodiment of the present invention is described in detail.
Fig. 1 is the structural representation of the wafer sort system of the specific embodiment of the invention. With reference to Fig. 1, waferTest macro comprises: probe card 101 and probe sanding apparatus 102, described probe sanding apparatus 102 forProbe card 101 is carried out to surface finish, be specially the probe in probe card is polished; Wafer sortMachine 200, wafer test machine 200 comprises control module 201. Wherein, probe card 101 is for receiving waferThe test signal that test machine 200 sends, tests the chip to be measured in wafer, after test, and probeTest result is fed back to wafer test machine 200 by card 101, and described test result comprises the source leakage of chip to be measuredForward conduction voltage drop VFSDTo be measured. As the pressure drop VFSD of continuous appearance chip to be measuredTo be measuredHigher or lower than sourceLeak the standard pressure drop VFSD of forward conductionStandardTime, wafer test machine is confirmed probe card Surface Creation oxide layerStain, then stop carrying out the test of follow-up chip to be measured, control module 201 is controlled probe sanding apparatus102 pairs of probe card 101 are carried out surface finish, remove the oxide layer of detecting probe surface, after polishing finishes, enterThe test of the next chip to be measured of row. The test signal that wafer test machine 200 sends comprise act on to be measuredThe data such as the voltage on chip or the electric current by chip to be measured.
In the present invention, select the source of chip to leak forward conduction voltage drop as judging whether that carrying out probe card beatsThe comparative parameter of mill is based on following consideration: all test parameters of chip to be measured, and as source drain breakdown electricityPress ratio (Rds), source between (BVdss), regulation drain voltage (Vds) and leakage current (Ids) to leakForward conduction voltage drops (VFSD) etc. are subject to the impact of the oxide layer contamination of probe card in test process,There will be test parameter numerical value to float. Wherein, You Yiyuan leaks the reaction sensitivity the most of forward conduction voltage drop,Once there is oxide layer in the detecting probe surface of probe card, the VFSD of chip to be measuredTo be measuredThere will be and float high phenomenon,This is mainly that this resistance makes the actual VFSD recording because oxide layer is equivalent to a resistanceTo be measuredNumberValue increases. Therefore, the present invention selects VFSDTo be measuredParameter as a comparison, can more accurately judge that probe beatsThe opportunity of mill.
In specific embodiment, described probe card 101 is as between wafer test machine 200 and waferInterface, probe card 101 is the printed circuit board (PCB)s with a lot of probes, in described probe and waferChip to be measured carries out physics and contacts with electricity. In test process, probe card 101 and wafer test machine 200Electrical connection, probe contacts with the test solder joint (pad) of the chip to be measured on wafer. By wafer test machine 200The test signal of sending, acts on chip to be measured by the probe of probe card 101. In specific embodiment,Automatically grinding device comprises sand paper, uses sand paper directly the probe of probe card to be carried out to surface finish.
In specific embodiment, wafer test machine 200 also comprises comparing unit 202, comparing unit 202 useIn by the pressure drop VFSD of chip to be measuredTo be measuredWith VFSDStandardCompare, and export comparison signal. DescribedComparison signal controlled unit 201 is obtained and record, when occurring continuously treating VFSDTo be measuredHigher or lower thanStandard pressure drop VFSDStandardComparison signal time, control module 201 is exported control signal, control probe beatMill apparatus 102 carries out automatically grinding to probe card 101; If there is not " VFSDTo be measuredHigher or lower than standardPressure drop VFSDStandardComparison signal " and the situation of " continuously ", without probe card 101 is beatenMill. This just makes the probe of probe card carry out the precision on opportunity of surface finish, but not a random choosingSelect process. So not only can reach the object of in time probe card being polished, and avoid not going outThe inessential work of the probe polishing that existing oxide layer is stain.
In specific embodiment, with reference to Fig. 2, wafer test machine 200 also comprises memory cell 203, forStorage probe card 101 is tested the pressure drop VFSD of obtained chip to be measuredTo be measured, standard pressure drop VFSDStandard；Wherein, control module 201 also comprises reading unit 211, and reading unit 211 is for reading chip to be measuredPressure drop VFSDTo be measured, standard pressure drop VFSDStandard. Afterwards, comparing unit 202 is from reading unit 211Obtain the pressure drop VFSD of chip to be measuredTo be measured, standard pressure drop VFSDStandard, and compare VFSDTo be measuredAnd standardPressure drop VFSDStandard。
In specific embodiment, to there is continuously pressure drop VFSDTo be measuredHigher or lower than standard VFSDStandard'sThe number range of chip to be measured is: account for 2%～4% of all core numbers in wafer, for example, at a plateletCircle comprises 500 chips, ought occur continuously 10(500 × 2%) VFSD of individual chip to be measuredTo be measuredHighIn or lower than VFSDStandardTime, just stop detecting, automatically carry out probe polishing. That is to say, in a sliceIn wafer, allow at most to occur continuously that 2%～4% chip occurs because the surface oxide layer of probe stainsThe test problem causing. In reality is produced, be to allow the oxide layer that occurs certain limitation ratio to stain surveyMay well ask and topic can improve like this efficiency of wafer sort, save the wafer sort time.
In specific embodiment, in comparing unit, set: VFSDTo be measuredHigher or lower than VFSDStandardModelEnclose for higher or lower than VFSDStandard3%. This is mainly to consider VFSDTo be measuredEqual VFSDStandardFeelingsShape, just a Utopian state. Reality produce in, chip production technique always there will be objective because of, and there is error in the interference of element, if this error in can allowed band, this chip is exactly qualified.So, in On-Wafer Measurement process, set ± 3% scope, can avoid a large amount of chips to be abandoned,Reduce production costs.
In specific embodiment, wafer test machine 200 also comprises input block and display unit (not shown).Wherein, input block is used for to wafer test machine 200 input test parameters, and described test parameter is sameThe supplemental characteristic of type qualified chip, leaks forward conduction voltage drop VFSD standard as source, and the standard that can be considered is surveyedExamination parameter. Afterwards, wafer test machine 200 sends test signal according to test parameter to probe card 101,As voltage or electric current. Display unit is used for showing test results, and described test result comprises: with defeated in advanceThe actual test parameter value of the corresponding chip to be measured of the test parameter of the qualified chip entering. If chip to be measuredThe test parameter scope of actual test parameter value in qualified chip, show that result is qualified, thenSystem can be carried out the test of next chip; If the not survey in qualified chip of chip testing parameter value to be measuredExamination parameter area, shows that result is defective, and this chip to be measured is identified as inefficacy, then system meetingCarry out the test of next chip.
Fig. 3 is the schematic flow sheet of the crystal round test approach of the specific embodiment of the invention.
With reference to Fig. 3, execution step S31, provides wafer, comprises some chips to be measured at wafer.
With reference to Fig. 3, execution step S32, sends test signal to probe card, probe card Acceptance Tests signalChip some to be measured in wafer is tested successively. Wherein, described test signal comprises and can make to treatSurvey chip and make voltage or the electric current of electrical reactions.
In specific embodiment, after each chip testing to be measured, can output test result, wherein, instituteState the source leakage forward conduction voltage drop VFSD that test result comprises chip to be measuredTo be measured. When continuous appearance core to be measuredThe pressure drop VFSD of sheetTo be measuredStandard pressure drop VFSD while leaking forward conduction higher or lower than sourceStandardTime, assertStain with oxide layer on probe card surface, now stops test, and probe card is carried out to surface finish, removesOxide layer is stain. Afterwards, after having polished, continue to test remaining chip to be measured.
In specific embodiment, the pressure drop VFSD when source leakage conductance of chip is logical is the probe that judges probe cardWhether capping oxidation layer and whether need the foundation that probe is polished of surface. In the prior art,Set fixing polishing frequency, after the chip to be measured of some to be tested, then probe card is polishedCompare. By comparison, whether the solution of the present invention can automatically judge and probe card be polished,The oxide layer that can eliminate more in time, exactly detecting probe surface is stain problem, eliminates oxide layer and stains problemOn the impact of test result. Polish by the detecting probe surface to probe card, remove surperficial oxide layer,Avoid detecting probe surface to stain the impact of the parameters numerical value on wafer sort, ensured every test parameterThe accuracy of value.
In specific embodiment, crystal round test approach, also comprises: by chip VFSD to be measuredTo be measuredWith standardPressure drop VFSDStandardCompare, and export comparison signal; Afterwards, obtain and record this comparison signal.When occurring continuously VFSDTo be measuredHigher or lower than standard pressure drop VFSDStandardComparison signal time, to described spyPin card is polished automatically.
In specific embodiment, crystal round test approach, also comprises: before On-Wafer Measurement starts, and storageStandard pressure drop VFSDStandard; Often completing once after chip testing to be measured, by the VFSD of chip to be measuredTo be measuredWith VFSDStandardBefore comparing, also comprise: storage probe card is tested the VFSD obtainingTo be measured; Afterwards,Obtain the VFSD of storageTo be measured、VFSDStandard, and both are compared, make and whether probe card being madeThe judgement of polishing.
In specific embodiment, consider that reality occurs that the problem that probe stains is successional in producing,In order to ensure the efficiency of wafer sort, reduce the testing time, setting occurs accounting in wafer all to be measured continuouslyWhen chip count object 2%～4% chip to be measured, just probe is stain and removed. That is to say,During reality is produced, in a wafer, the chip to be measured of permission 2%～4% occurs what probe contamination caused at mostTest problem.
In specific embodiment, to the VFSD of chip to be measuredTo be measuredHigher or lower than VFSDStandardScope bagDraw together: higher or lower than VFSDStandard3%. Reality is produced and is subject to the impact such as technique, environment, chip to be measuredPerformance occur that slightly deviation is in can allowed band, as long as can be applied to specific environment, all closesLattice product. The parameters value that this is reflected to chip to be measured, be also limited in can allowed band in. Otherwise,To have large quantities of chips and be abandoned, and can significantly increase production cost. To VFSDTo be measuredAlso like this, when connectingThe continuous VFSD that occurs some (as account for all chips in wafer 2%～4%) chips to be measuredTo be measuredHighIn or lower than VFSDStandardTime, just can polish to probe. This has just further improved testing efficiency,Save the testing time.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, appointsWhat those skilled in the art without departing from the spirit and scope of the present invention, can utilize above-mentioned announcementMethod and technology contents are made possible variation and amendment to technical solution of the present invention, therefore, every not de-From the content of technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done is anySimple modification, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (13)
1. a wafer sort system, is characterized in that, comprising:
Probe card and probe sanding apparatus;
Wafer test machine, described wafer test machine comprises control module;
Described probe card receives the test signal that described wafer test machine sends, to the chip to be measured in waferTest, after test, test result is fed back to described wafer test machine, described test result comprises to be treatedForward conduction voltage drop VFSD is leaked in the source of surveying chipTo be measured；
Leak forward conduction voltage drop VFSD when there is continuously sourceTo be measuredLeak the standard of forward conduction higher or lower than sourcePressure drop VFSDStandardTime, stopping test, probe sanding apparatus is to described spy described in described control module controlPin card is polished; After polishing, carry out the test of next chip to be measured.
2. wafer sort system as claimed in claim 1, is characterized in that, described wafer test machine also comprisesComparing unit;
Described comparing unit leaks described source the standard pressure drop VFSD of forward conductionStandardLeak forward conduction with sourcePressure drop VFSDTo be measuredCompare output comparison signal;
Described control module, obtains and records described comparison signal, when occurring continuously source leakage forward conduction pressureVFSD fallsTo be measuredLeak the standard pressure drop VFSD of forward conduction higher or lower than sourceStandardComparison signal time, defeatedGo out control signal, control described probe sanding apparatus described probe card is polished.
3. wafer sort system as claimed in claim 2, is characterized in that, described wafer test machine also comprisesMemory cell, forward conduction voltage drop VFSD is leaked in the source of storing described probe card testTo be measuredLeak with described sourceThe standard pressure drop VFSD of forward conductionStandard；
Described control module also comprises: reading unit reads described source and leaks forward from described memory cellConduction voltage drop VFSDTo be measuredStandard pressure drop VFSD with described source leakage forward conductionStandard；
Described comparing unit leaks forward conduction voltage drop VFSD from the described reading unit source that obtainsTo be measuredWith described sourceLeak the standard pressure drop VFSD of forward conductionStandardAfter, reference source leaks forward conduction voltage drop VFSDTo be measuredWith describedThe standard pressure drop VFSD of forward conduction is leaked in sourceStandard。
4. wafer sort system as claimed in claim 1, is characterized in that, described probe sanding apparatus comprisesSand paper.
5. wafer sort system as claimed in claim 1, is characterized in that, the described source leakage forward that occurs continuouslyConduction voltage drop VFSDTo be measuredLeak the standard pressure drop VFSD of forward conduction higher or lower than sourceStandardCore to be measuredThe number range of sheet is: account for 2%～4% of all core numbers in wafer.
6. wafer sort system as claimed in claim 1, is characterized in that, forward conduction voltage drop is leaked in described sourceVFSDTo be measuredLeak the standard pressure drop VFSD of forward conduction higher or lower than described sourceStandard, comprise scope:Leak the standard pressure drop VFSD of forward conduction higher or lower than sourceStandard3%.
7. wafer sort system as claimed in claim 1, is characterized in that, described wafer test machine also comprisesInput block and display unit;
Described input block is for input test parameter, described wafer test machine according to described test parameter toDescribed probe card is sent test signal;
Described display unit is used for showing described test result.
8. wafer sort system as claimed in claim 7, is characterized in that, described test parameter comprises: instituteThe standard pressure drop VFSD of forward conduction is leaked in the source of statingStandard, source drain breakdown voltage and regulation drain voltage and electric leakageRatio between stream.
9. a crystal round test approach, is characterized in that, comprising:
Wafer is provided, and described wafer comprises some chips to be measured;
Send test signal to probe card, described probe card receives some in wafer of described test signalChip to be measured is tested successively;
After each chip testing to be measured, output test result, described test result comprises chip to be measuredSource leak forward conduction voltage drop VFSDTo be measured；
Leak forward conduction voltage drop VFSD when there is continuously sourceTo be measuredLeak the standard of forward conduction higher or lower than sourcePressure drop VFSDStandardTime, stop test, described probe card is polished; After having polished, it is right to continueChip to be measured is tested.
10. method of testing as claimed in claim 9, is characterized in that, also comprises: positive guide is leaked in described sourceLogical standard pressure drop VFSDStandardLeak forward conduction voltage drop VFSD with sourceTo be measuredCompare, output relativelySignal;
Obtain and record described comparison signal, when occurring continuously source leakage forward conduction voltage drop VFSDTo be measuredHigher thanOr leak the standard pressure drop VFSD of forward conduction lower than described sourceStandardComparison signal time, to described probe cardPolish.
11. method of testings as claimed in claim 10, is characterized in that, also comprise, store described source and leak forwardThe standard pressure drop VFSD of conductingStandard; Often complete once test, the standard of described source being leaked to forward conductionPressure drop VFSDStandardLeak forward conduction voltage drop VFSD with sourceTo be measuredBefore comparing, also comprise: storageForward conduction voltage drop VFSD is leaked in the source of described probe card testTo be measured；
The standard pressure drop VFSD of forward conduction is leaked in the described source that obtains storageStandardLeak forward conduction voltage drop with sourceVFSDTo be measuredAfterwards, described source is leaked to the standard pressure drop VFSD of forward conductionStandardLeak forward conduction voltage drop with sourceVFSDTo be measuredCompare.
12. method of testings as claimed in claim 9, is characterized in that, the described source leakage forward conduction that occurs continuouslyPressure drop VFSDTo be measuredLeak the standard pressure drop VFSD of forward conduction higher or lower than sourceStandardChip to be measuredNumber range is: account for all chip count objects 2%～4% in wafer.
13. method of testings as claimed in claim 9, is characterized in that, forward conduction voltage drop VFSD is leaked in described sourceTo be measuredLeak the standard pressure drop VFSD of forward conduction higher or lower than described sourceStandard, comprise scope: higher than orLeak the standard pressure drop VFSD of forward conduction lower than sourceStandard3%.
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| CN111293048B (en) * | 2018-12-07 | 2024-07-02 | 紫光同芯微电子有限公司 | Wafer testing system and method thereof |
| CN109814025A (en) * | 2019-03-18 | 2019-05-28 | 烟台睿创微纳技术股份有限公司 | Equipment that a kind of pair of wafer is tested, method and system |
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