CN102916915A - Method for transmitting ultra-high-speed signal between stacked chips - Google Patents

Method for transmitting ultra-high-speed signal between stacked chips Download PDF

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Publication number
CN102916915A
CN102916915A CN2012104101055A CN201210410105A CN102916915A CN 102916915 A CN102916915 A CN 102916915A CN 2012104101055 A CN2012104101055 A CN 2012104101055A CN 201210410105 A CN201210410105 A CN 201210410105A CN 102916915 A CN102916915 A CN 102916915A
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CN
China
Prior art keywords
speed signal
high speed
ultra high
stacked chips
chip
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Pending
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CN2012104101055A
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Chinese (zh)
Inventor
景蔚亮
陈邦明
亢勇
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Shanghai Xinchu Integrated Circuit Co Ltd
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Shanghai Xinchu Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to CN2012104101055A priority Critical patent/CN102916915A/en
Publication of CN102916915A publication Critical patent/CN102916915A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a method for transmitting an ultra-high-speed signal between stacked chips. The method comprises the steps that a sender chip divides the ultra-high-speed signal to be transmitted into two paths of signals and negates the polarity of one path of signal; the sender chip respectively transmits the two paths of signals to a receiver chip through two interconnected wires; and the receiver chip reduces the two paths of signals into the ultra-high-speed signal through differential processing. By adopting the method, the ultra-high-speed signal is transmitted in a differential manner, so that the ultra-high-speed signal can be directly transmitted between the stacked chips without undergoing frequency reduction, and the performance of the chips cannot be lost after the stacked interconnected wires are encapsulated.

Description

A kind of method of between stacked chips, transmitting ultra high speed signal
Technical field
The present invention relates to the stacked chips technical field, relate in particular to a kind of method of between stacked chips, transmitting ultra high speed signal.
Background technology
Along with constantly dwindling of integrated circuit technology size, the operating rate of chip is more and more faster, even can reach several GHz, if these ultra high speed signals of interconnection line transmission especially can run into a lot of problems when wire-bonded (wire bonding) interconnection line transmits between stacked chips, such as, because frequency is too high, will become very poor so hold the ability of making an uproar, must transmit by reducing work frequency when causing transmitting ultra high speed signal, thereby the performance of chip has been reduced.
Summary of the invention
The present invention has overcome can't be transmitted in the stacked chips in the background technology or the defective of frequency reducing transmission ultra high speed signal, proposed a kind of between stacked chips the method for transmission ultra high speed signal.
The method of transmitting ultra high speed signal between stacked chips of the present invention comprises:
Step 1: the transmit leg chip is divided into two paths of signals with ultra high speed signal waiting for transmission, and with the wherein polarity negate of one road signal;
Step 2: described transmit leg chip transfers to respectively recipient's chip with described two paths of signals by two interconnection lines;
Step 3: recipient's chip is reduced into described ultra high speed signal with described two paths of signals by difference processing.
Wherein, described step 1 takes a step forward and comprises: described transmit leg chip reduces the voltage of described ultra high speed signal.
Wherein, the interconnection line between the described stacked chips is that wire-bonded interconnection line or silicon through hole connect interconnection line.
Wherein, the voltage of described ultra high speed signal can be reduced at most the minimum of the device that adopts minimum process manufacturing in the described stacked chips ± 10%.
The present invention can be by carrying out reduced pressure operation with ultra high speed signal, and convert ultra high speed signal to differential signal, transmit at two interconnection lines, solved the defective of the signal integrity reduction that when stacked chips transmission ultra high speed signal, brings, improve the transmission rate of ultra high speed signal in the stacked chips, improved the performance of chip.
Description of drawings
Fig. 1 is the method for ultra high speed signal is transmitted in the present invention between stacked chips flow chart.
Fig. 2 is the schematic diagram that ultra high speed signal is transmitted in the present invention.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the following content of mentioning specially, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
As shown in Figure 1, the method for transmitting ultra high speed signal between stacked chips of the present invention comprises:
Step 1: the transmit leg chip is divided into two paths of signals with ultra high speed signal waiting for transmission, and with the wherein polarity negate of one road signal;
Step 2: the transmit leg chip transfers to respectively recipient's chip with two paths of signals by two interconnection lines;
Step 3: recipient's chip is reduced into ultra high speed signal with two paths of signals by difference processing.
The method of ultra high speed signal is transmitted in the present invention between stacked chips, the interconnection line between the stacked chips is that wire-bonded interconnection line or silicon through hole connect interconnection line.
The present invention is when the ultra high speed signal of transmission higher frequency, need to carry out step-down to sent ultra high speed signal processes, voltage can be down at most ± 10%Core Voltage (Core Voltage: on the stacked chips with the minimum of the produced device of minimum process) after, transmit with differential mode by two interconnection lines.
Embodiment 1:
When between the stacked on top chip, passing through wire-bonded (wire bonding) interconnection line transmission ultra high speed signal, first at signal sending end 1 ultra high speed signal to be sent is divided into two-way, transmit by two interconnection lines, one the tunnel keeps original signal polarity constant, and other one the tunnel the signal negate.Signal sending end 1 sends to respectively (wire bonding) transmission transmission on two interconnection lines to this two paths of signals.Being integrated into a ultra high speed signal after signal that signal receiving end 2 transmits on two interconnection lines is through the contrast divisional processing uses to subsequent element (for example internal logic).
In the present embodiment, transmit ultra high speed signal by differential mode at wire-bonded (wire bonding) interconnection line between the stacked chips, can subtract each other and cancel being superimposed upon respectively two noise sources on the interconnection line, hold the ability of making an uproar thereby improved widely, so that the frequency of ultra high speed signal remains unchanged when transmitting by wire-bonded (wire bonding) interconnection line between stacked chips.
By the method for transmitting signals in the present embodiment, so that ultra high speed signal in stacked chips can with hundreds of megahertzes or on the speed of GHz transmit, solved can not transmit in the prior art or must frequency reducing the problem of transmission ultra high speed signal, and the appearance that the has improved ultra high speed signal ability of making an uproar has improved the transmittability of ultra high speed signal.
Embodiment 2:
As shown in Figure 2, when between the stacked on top chip, transmitting more ultra high speed signal (more the ultra high speed signal frequency is more than the 1GHz) by wire-bonded (wire bonding) interconnection line, as shown in Figure 1, when wire-bonded (wire bonding) interconnection line transmits more ultra high speed signal, first more ultra high speed signal voltage to be sent is carried out step-down at signal sending end 1, such as, be reduced to 1.1V (Core Voltage) from 3.3V (IO Voltage, input and output voltage) or 1.8v (IO Voltage).Then the more ultra high speed signal behind the lower voltage is divided into two-way, one the tunnel keeps the more ultra high speed signal polarity behind the lower voltage constant, other one the tunnel the more ultra high speed signal negate behind the lower voltage, then this two paths of signals is sent to respectively (wire bonding) transmission transmission on two interconnection lines.At signal receiving end 2, the signal that transmits on two interconnection lines be integrated into after through the contrast divisional processing one more ultra high speed signal use to internal logic.After more under the voltage drop of ultra high speed signal, so that the conversion rates of signal becomes faster, both the speed of from " 0 " to " 1 " or from " 1 " to " 0 " variation accelerated, thereby guaranteed to pass through between the stacked on top chip the more superfast signal of wire-bonded (wire bonding) interconnection line transmission.
By the method for transmitting signals in the present embodiment, so that ultra high speed signal can transmit with the speed more than the 1GHz in stacked chips, solved and to have transmitted in the prior art or must frequency reducing transmit the more problem of ultra high speed signal, and the appearance that the has improved ultra high speed signal ability of making an uproar has improved the transmittability of ultra high speed signal.
Protection content of the present invention is not limited to above embodiment.Under the spirit and scope that do not deviate from inventive concept, those skilled in the art can to variation and advantage all be included in the present invention, and take appending claims as protection range.

Claims (4)

1. the method for a transmission ultra high speed signal between stacked chips is characterized in that, comprising:
Step 1: the transmit leg chip is divided into two paths of signals with ultra high speed signal waiting for transmission, and with the wherein polarity negate of one road signal;
Step 2: described transmit leg chip transfers to respectively recipient's chip with described two paths of signals by two interconnection lines;
Step 3: recipient's chip is reduced into described ultra high speed signal with described two paths of signals by difference processing.
2. the method for transmitting ultra high speed signal between stacked chips as claimed in claim 1 is characterized in that, described step 1 takes a step forward and comprises: described transmit leg chip reduces the voltage of described ultra high speed signal.
3. the method for transmitting ultra high speed signal between stacked chips as claimed in claim 1 is characterized in that, the interconnection line between the described stacked chips is that wire-bonded interconnection line or silicon through hole connect interconnection line.
As claimed in claim 2 between stacked chips the transmission ultra high speed signal method, it is characterized in that, the voltage of described ultra high speed signal can be reduced at most in the described stacked chips minimum that adopts the device that minimum process makes ± 10%.
CN2012104101055A 2012-10-24 2012-10-24 Method for transmitting ultra-high-speed signal between stacked chips Pending CN102916915A (en)

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CN2012104101055A CN102916915A (en) 2012-10-24 2012-10-24 Method for transmitting ultra-high-speed signal between stacked chips

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105071913A (en) * 2015-07-23 2015-11-18 柳州一合科技有限公司 Method of synchronizing multiple user signals
US10381330B2 (en) 2017-03-28 2019-08-13 Silicon Storage Technology, Inc. Sacrificial alignment ring and self-soldering vias for wafer bonding

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US20040105627A1 (en) * 2002-11-15 2004-06-03 Jds Uniphase Corporation Receiver optical sub-assembly
CN101621060A (en) * 2008-06-30 2010-01-06 海力士半导体有限公司 Semiconductor package, stacked semiconductor package having the same, and a method for selecting one semiconductor chip in a stacked semiconductor package
US7969193B1 (en) * 2010-07-06 2011-06-28 National Tsing Hua University Differential sensing and TSV timing control scheme for 3D-IC
CN102385911A (en) * 2010-09-03 2012-03-21 三星电子株式会社 Semiconductor memory device
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105071913A (en) * 2015-07-23 2015-11-18 柳州一合科技有限公司 Method of synchronizing multiple user signals
US10381330B2 (en) 2017-03-28 2019-08-13 Silicon Storage Technology, Inc. Sacrificial alignment ring and self-soldering vias for wafer bonding

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