CN102915959B - Method for simplifying etching and forming techniques for word line dielectric film in storage - Google Patents
Method for simplifying etching and forming techniques for word line dielectric film in storage Download PDFInfo
- Publication number
- CN102915959B CN102915959B CN201210375725.XA CN201210375725A CN102915959B CN 102915959 B CN102915959 B CN 102915959B CN 201210375725 A CN201210375725 A CN 201210375725A CN 102915959 B CN102915959 B CN 102915959B
- Authority
- CN
- China
- Prior art keywords
- hole
- dielectric film
- antireflective coating
- bottom antireflective
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides a method for simplifying etching and forming techniques for a word line dielectric film in a storage. With the adoption of the method, the a one-time photoresist filling line and a one-time dry etching technique link are effectively reduced in the production for each wafer, so that the cost can be well lowered, and the efficiency of producing semi-conductor can be greatly improved.
Description
Technical field
The present invention relates to the preparation technology of semiconductor device, specifically, relate to a kind ofly simplify wordline dielectric film in memory and etch shaping process.
Background technology
As shown in Figure 1, in memory, the function of wordline is extremely important, the general configuration of a memory cell as shown in the figure, the grid of transistor 3 couples together by wordline 1, by optionally opening and closing memory cell, carrys out charging and the electric discharge of control capacitance 2.Again as shown in Figure 2, be the general principle figure of memory, controlled the switch of transistor 2 by the high and low level of wordline 1, thus achieve the control to transistor switch.
Existing wordline dielectric film etching moulding process as illustrated in figs. 3a-f, as shown in Figure 3A, first at dielectric film 4 and via etch stop-layer (Contact etch stop layer, be called for short CESL, also be called contact hole etching barrier layer) in etch through hole 5, and a part of metal silicide of gate upper surface is gone out in the bottom-exposed of through hole 5, then on the dielectric film 4 comprising through hole 50 spin coating one deck encapsulant layer (it has the composition similar with anti-reflective film, there is good holes filling ability, a kind of anti-reflective film can be considered as) 19, and make it solidify.Wherein, it is inner that packing material for the formation of encapsulant layer 19 is also filled in through hole 5, method afterwards by eat-backing removes the encapsulant layer 19 above dielectric film 4, also can in the lump a part of packing material on through hole 5 top be eat-back and retain the packing material of bottom simultaneously, therefore the upper surface of upper surface lower than dielectric film 4 of the packing material of the remainder of through hole 5 its underpart is positioned at, in other words, height of formation drop between packing material and the upper surface of dielectric film 4 is remained in through hole 5.Thereafter, spin coating one deck bottom anti-reflective film 20 above dielectric film 4 again, the top of through hole 5 is filled in around here for the formation of a part of material of bottom anti-reflective film 20, and then on anti-reflective film 20 spin coating photoresist layer 21, and by defining the wordline figure in photoresist layer 21 in exposure imaging technique.Last etch dielectric plasma membrane 4, then to the photoresist of dielectric film 4 surface residual, in remaining bottom anti-reflection layer and through hole 5, remaining packing material 19 etc. carries out cineration technics and is removed, and to form groove 9, groove 9 is connected with contact hole 5.
It is evident that, existing technical scheme operation is comparatively complicated, be embodied in and need first spin coating packing material then to eat-back again, then before formation photoresist layer, also need spin coating twice antireflection material, more operation causes cost significantly to raise, and the yield of product more easily declines under the process environments of complexity.If therefore suitable optimization can be carried out to whole flow process, then can save production cost, raise the efficiency.
Summary of the invention
The invention provides a kind of method simplifying wordline dielectric film etching moulding process in memory, comprise the following steps: step one, semi-conductive substrate forms semiconductor element, and above described semiconductor element, form a via etch stop-layer, and above described via etch stop-layer, form one deck dielectric film further; Step 2, implements etching successively to form the through hole of the grid aiming at semiconductor element in described dielectric film and via etch stop-layer; Step 3, coating one deck bottom antireflective coating covers the top of described dielectric film, and described bottom antireflective coating covers the bottom not being filled in through hole compared with top to form a top filler also entering into each through hole on through hole and for the formation of the antireflection material of bottom antireflective coating simultaneously; Step 4, applies one deck photoresist layer again on bottom antireflective coating, and at least forms the wordline opening figure in photoresist layer by photoetching process; Step 5, utilize described photoresist layer as mask, etch away described bottom antireflective coating and be exposed to part in wordline opening figure and described top filler, and etching is implemented to the described dielectric film in the region comprising the region defining described through hole, with formed be positioned at described dielectric film top and be connected to the wordline groove of through hole.
Above-mentioned method, in the lithography step of step 4, the developer solution for the formation of the wordline opening figure in described photoresist layer only reacts with photoresist layer and does not react with bottom antireflective coating.
Above-mentioned method, in the step forming bottom antireflective coating, when spin-on anti-reflective coating, control the temperature value of environment residing for the rotary speed of Semiconductor substrate and antireflection material, make the antireflection material for the formation of bottom antireflective coating only enter into the bottom not entering into through hole compared with top to form described top filler of through hole, thus form a cavity in the bottom of through hole.
Above-mentioned method, after step 5, fills metal and forms embolism in described through hole, and in described wordline groove, fill metal formation metal word lines interconnection structure, is electrically connected on described grid by described embolism to make described wordline interconnection structure.
Above-mentioned method, after step 5, and fill the step of metal in through hole, wordline groove before, also comprises and removes remaining bottom antireflective coating, the step of photoresist layer.
Above-mentioned method, the polymer formed in the etching process of step 2 is attached on the inwall at the top of through hole, can make via top reducing a little, therefore when the spin coating bottom antireflective coating of step 3, antireflection material is only filled with the top of through hole, and forms cavity in through hole bottom.
Above-mentioned method, after step 5, also comprises the step will removed together with the bottom antireflective coating of the polymer formed in etching reaction process and remainder, photoresist layer.
In one embodiment, the step utilizing dry etching to form through hole comprises: utilize the mixing etching gas of light polymer property in dielectric film, etch the top of through hole in advance, then utilize the mixing etching gas of heavy polymer characteristic in dielectric film, etch the bottom of through hole, and form the polymer be attached on the sidewall at the top of through hole, described polymer for slowing down the etching of the dielectric film of the top periphery to through hole, thus makes the top reducing slightly of through hole.
Contrast with old technology flow process, an anti-reflecting layer material fill processes is saved in technological process of the present invention and anti-reflecting layer material returns carving technology.The saving of this twice technological process can well reduce costs.Not only for the Productivity Allocation of technique board, the saving of board consumable component part, the raw-material saving of semiconductor production, semiconductor production efficiency all has greatly improved.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to following accompanying drawing, the further feature of invention, object and advantage will become more obvious.
Fig. 1 is the schematic diagram of single memory cell;
Fig. 2 is holder basic principle schematic;
Fig. 3 A-3F is that current wordline dielectric film etches shaping process flow diagram;
Fig. 4 A-4E is a kind of schematic flow sheet simplifying the method for wordline dielectric film etching moulding process in memory of the present invention.
Embodiment
The technological means realized to make invention, creating feature, reach object and effect is easy to understand, lower combination specifically illustrates, and sets forth the present invention further.
As shown in Figure 4 A, in a particular embodiment of the present invention, for the purpose of brief introduction, part semiconductor substrate 10 is only illustrated in figure, the well region 11 of P type or N-type is formed at the top of Semiconductor substrate 10, and be formed contrary with the doping type of well region 11 in well region 11 and be positioned at source region 12a and the drain region 12b of the adjacent top surface of substrate 10, and to be formed at source region 12a end face form well in electrical contact can be used for source region 12a and fall low-resistance metal silicide 12a-1, with formed at drain region 12b end face form metal silicide 12b-1 well in electrical contact with drain region 12b.Gate oxide layers 16 is formed on the upper surface of the well region 11 of the formation conductive channel between source region 12a and drain region 12b, polysilicon gate 13 is formed above gate oxide layers 16, the both sides of grid 13 are formed with the side wall 14 covered on grid 13 sidewall, wherein the end face of grid 13 is also formed and forms metal silicide 13a well in electrical contact with grid 13, and the fleet plough groove isolation structure 20 by being filled with oxide between the well region of adjacent different doping types is isolated each other, thus form the semiconductor element of N raceway groove NMOS or P channel PMOS over the substrate 10.And also forming one deck via etch stop-layer (CESL is also called contact hole etching barrier layer) 15 in the top face of substrate 10, it also covers on each grid 13 and side wall 14 thereof simultaneously.Thus make via etch stop-layer 15 wherein at least cover the top of NMOS or PMOS, and dielectric film 4(ILD, also can be referred to as interlayer dielectric layer) then cover on via etch stop-layer 15.The device architecture disclosed due to foregoing is known by those skilled in the art, and therefore, the application only slightly lays down a definition at this and repeats no more.
As shown in Figure 4 A, first deposit the top that a dielectric film 4 covers via etch stop-layer 15, usually, the upper surface of the dielectric film 4 of initial period can be rough and uneven in surface, so surperficial and then also along with the operation of cmp CMP thereon, the upper surface of dielectric film 4 to be ground to a burnishing surface (i.e. the step of planarization).Then, utilize the mask with via openings figure (such as photoresist) of anticipating out not shown in the figures successively in dielectric film 4, etching stop layer 15 etching formed run through whole dielectric film 4 and via etch stop-layer 15 separately thickness and aim at the through hole (also can be called contact hole) 5 of grid 13, through hole 5 extends downward and runs through via etch stop-layer 15, and touch the metal silicide of grid 13 upper surface, a part of metal silicide of grid 13 upper surface is namely gone out in the bottom-exposed of through hole 5.Via etch stop-layer 15 is made up of the silicon nitride film etc. of such as CVD deposit, and dielectric film 4 is made up of the silicon oxide film of such as CVD deposit, and dielectric film 4 can be made up of low dielectric insulating films such as SiO2.
Then as shown in Figure 4 B, described dielectric film 4 applies one deck for weakening the material of light reflected intensity, be called bottom antireflective coating (Bottom Anti Reflective Coating, be called for short BARC) 6, it is noted that in this step, a part of material for the formation of bottom antireflective coating 6 also can be filled in the comparatively top of through hole 5, form the top filler 6a be made up of antireflection material, its middle and upper part filler 6a and bottom antireflective coating 6 form an entirety.In order to formed through hole 5 and adopt dry etching process in, can take some specific methods, make the top of through hole 5 slightly close up and can seem than its underpart narrow, in other words, the internal diameter at its top can be slightly less than the internal diameter of through hole 5 bottom.A kind of Alternate embodiments is, the part in via etch process adopts the reacting gas that can produce compared with heteropolymer to achieve the goal.A part in described etching process needs to carry out concrete definition for different situations, normally for the definition of etch period.Formation mechenism is in dry etching process, adopt the gas that can produce compared with heteropolymer, thus forms more polymer, has high aspect ratio structure (High aspect ratio microstructures) because through hole is one.In the etching process of through hole 5, the polymer produced in through hole 5 is in the process of volatilizing outside hole, part polymer can be assembled on the sidewall at the top of through hole 5, etching barrier layer/the passivation layer (mark) being equivalent to define layer is attached on the sidewall at through hole 5 top, this weakens the etching to the dielectric film 4 be looped around around through hole 5 top to a certain extent relatively, result causes through hole 5 top can reducing slightly (or claim close up) exactly, its internal diameter can be smaller, and the internal diameter compared with bottom of through hole 5 is then slightly large.It is worth noting, the coating process that this structure is a significant benefit to bottom antireflective coating 6 forms cavity in the bottom of through hole 5, because the top of the through hole of reducing 5 (namely less internal diameter) makes the antireflection material forming bottom antireflective coating 6 can not fill very dark in through hole 5, also the under-filled process of antireflection material continuation to through hole 5 is namely blocked, thus antireflection material only can be filled in the comparatively top of through hole 5 and form a top filler 6a, the region be positioned in through hole 5 below the filler 6a of top will form a cavity be closed.
In view of whenever the sidewall profile of through hole 5 and the difference of its internal diameter not all meet our expectation, therefore, we can also to take advantage of a situation the pattern of optimization or additional adjustment through hole 5 top and its underpart by setting the etching condition of through hole 5, comprise the difference in internal diameters opposite sex of top internal diameter and its underpart, strengthen the impact that the filling characteristic of this otherness antagonistic reflex material in through hole causes.Such as all the categories that can take into account Row sum-equal matrix for parameters such as the gas pressure intensities in the constituent of hybrid reaction gas that etches and the flow proportional of often kind of gas and RF frequency, etching power and etch chamber, such as utilize gas CF4, C4F8 and Ar2(argon gas of light polymer property in advance) etc. mist under suitable frequency and pressure to dielectric film 4 implement etching, form the top of through hole 5, the polymer of the less carbon containing formed in this step can volatilize rapidly and leaves contact hole and can not be attached on the sidewall at through hole 5 top.Thereafter the gas CF4 of heavy polymer characteristic is utilized, C5F8 and Ar2(argon gas) etc. mist under suitable frequency and pressure further to dielectric film 4 implement etching, to obtain the bottom of through hole 5, until the etching depth of the through hole 5 obtained reaches the desired value of expectation, the polymer of the more carbon containing formed in this step while volatilizing in contact hole, part can be attached on the sidewall at connection top, hole 5, be equivalent to the etching barrier layer/passivation layer (mark) defining layer, fluoro free radical is made cannot significantly to pass polymer so reduce the etching effect of the dielectric film 4 around to through hole 5 top.However, need benly be, this etching process still must be controlled the degree of the generation of polymer and the via top caused thus reducing, cross and all undesirably occur with too late, so it is better to think that through hole 5 top has more polymer to exist, because too much polymer can cause the top reducing of through hole 5 to be tending towards serious in via top gathering, such via top and bottom CD(Critical Dimension) all can depart from normal value, in extreme circumstances, through hole also can be sealed completely, etching can be made to stop completely, cannot be connected with grid, finally cause the open circuit electrically.Polymer, after formation through hole 5 is shaped, need be removed by techniques such as photoresist ashing process.
In addition, in the coating process of bottom antireflective coating 6, require when being coated with antireflecting coating 6, the accurate rotary speed controlling the pedestal of carrying wafer or Semiconductor substrate, be equivalent to the rotary speed controlling substrate, and control the parameter such as temperature value of the environment residing for bottom antireflective coating 6 well, avoid antireflection material cannot enter in through hole 5 or enter excessive antireflection material and the cavity of through hole 5 bottom cannot be formed.
As shown in Figure 4 C, bottom antireflective coating 6 applies one deck photoresist layer (or claiming photoresist film) 7 again, the reflection ray that bottom antireflective coating 6 extremely effectively can weaken bottom enters at photoresist layer 7, thus avoid its resolution deteriorates, and photolithographic procedures is carried out to photoresist layer 7, after exposure imaging is implemented to it, in photoresist layer 7, at least form the wordline opening figure 8 defining position.In this step, because developer solution cannot be avoided completely to touch bottom antireflective coating 6 in the process of develop to photoresist layer 7, so necessarily require the difference to some extent of the chemical property for developer solution of bottom antireflective coating 6 and photoresist layer 7, this can be realized by the choice of material that bottom antireflective coating 6, photoresist layer 7 are respective, only reacts with photoresist layer 7 (responsive to it) and do not react (insensitive to it) with bottom antireflective coating 6 with the developer solution ensureing for photoresist layer 7.In brief, namely require that this material of bottom antireflective coating 6 can not be subject to the impact of wordline exposure imaging technique because forming wordline opening figure 8.
As shown in Figure 4 D, utilize photoresist layer 7 as etch mask, dry etching is utilized bottom antireflective coating 6 to be exposed to part in opening figure 8 and top filler 6a etches away, and further the dielectric film 4 in the region comprising the region defining through hole 5 is etched, and then form the wordline groove (also referred to as interconnection channel) 9 being connected to through hole 5 being positioned at dielectric film 4 top, form typical dual damascene openings structure 17(see Fig. 4 E), metal can be filled in through hole 5 and wordline groove 9 so that follow-up, final formation is electrically connected to grid 13 by the metal (embolism) in through hole 5 and be positioned at the metal word lines interconnection structure of groove 9.Wherein, after the dual damascene openings structure 17 described in formation, and before filling metal material in the structure shown here, also need the bottom antireflective coating 6 of remainder, photoresist layer 7 to give ashing process and removed.Because bottom antireflective coating 6, both photoresist layers 7 have similar constituent, then they can get rid of by single treatment simultaneously.
In sum, invent a kind of method simplifying wordline dielectric film etching moulding process in memory, contrast (such as can with reference to background technology part) with old technology flow process, effectively make technological process of the present invention save photoresist fill process and photoresist returns carving technology.The saving of this twice technological process, to the production cycle, production complexity, production cost is all improved effect, each wafer production minimizing photoresist can be made to fill link and a dry etch process link, can well reduce costs like this, such benefit is not only for the Productivity Allocation of technique board, the saving of board consumable component part, the raw-material saving of semiconductor production, semiconductor production efficiency all has greatly improved.
Above to the specific embodiment description of invention.It is to be appreciated that invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect essence of an invention content.
Claims (5)
1. simplify a method for wordline dielectric film etching moulding process in memory, it is characterized in that, comprise the following steps:
Step one, semi-conductive substrate forms semiconductor element, and above described semiconductor element, form a via etch stop-layer, and above described via etch stop-layer, forms one deck dielectric film further;
Step 2, implements etching successively to form the through hole of the grid aiming at semiconductor element in described dielectric film and via etch stop-layer;
Step 3, coating one deck bottom antireflective coating covers the top of described dielectric film, and described bottom antireflective coating covers the bottom not being filled in through hole compared with top to form a top filler also entering into each through hole on through hole and for the formation of the antireflection material of bottom antireflective coating simultaneously;
Step 4, applies one deck photoresist layer again on bottom antireflective coating, and at least forms the wordline opening figure in photoresist layer by photoetching process;
Step 5, utilize described photoresist layer as mask, etch away described bottom antireflective coating and be exposed to part in wordline opening figure and described top filler, and etching is implemented to the described dielectric film in the region comprising the region defining described through hole, with formed be positioned at described dielectric film top and be connected to the wordline groove of through hole;
Wherein, in the step forming bottom antireflective coating, when spin-on anti-reflective coating, control the temperature value of environment residing for the rotary speed of Semiconductor substrate and antireflection material, make the antireflection material for the formation of bottom antireflective coating only enter into the bottom not entering into through hole compared with top to form described top filler of through hole, thus form a cavity in the bottom of through hole.
2. the method for claim 1, is characterized in that, in the lithography step of step 4, the developer solution for the formation of the wordline opening figure in described photoresist layer only reacts with photoresist layer and do not react with bottom antireflective coating.
3. the method for claim 1, it is characterized in that, after step 5, in described through hole, fill metal form embolism, and in described wordline groove, fill metal formation metal word lines interconnection structure, be electrically connected on described grid by described embolism to make described wordline interconnection structure.
4. the method for claim 1, it is characterized in that, the polymer formed in the etching process of step 2 is attached on the inwall at the top of through hole, via top reducing a little can be made, therefore when the spin coating bottom antireflective coating of step 3, antireflection material is only filled with the top of through hole, and forms cavity in through hole bottom.
5. method as claimed in claim 4, is characterized in that, after step 5, also comprises the step will removed together with the bottom antireflective coating of the described polymer formed in etching reaction process and remainder, photoresist layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210375725.XA CN102915959B (en) | 2012-10-08 | 2012-10-08 | Method for simplifying etching and forming techniques for word line dielectric film in storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210375725.XA CN102915959B (en) | 2012-10-08 | 2012-10-08 | Method for simplifying etching and forming techniques for word line dielectric film in storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102915959A CN102915959A (en) | 2013-02-06 |
| CN102915959B true CN102915959B (en) | 2015-06-17 |
Family
ID=47614275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210375725.XA Active CN102915959B (en) | 2012-10-08 | 2012-10-08 | Method for simplifying etching and forming techniques for word line dielectric film in storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102915959B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1203442A (en) * | 1997-06-25 | 1998-12-30 | 三星电子株式会社 | Process and apparatus for dry-etching semiconductor layer |
| TW200428582A (en) * | 2003-06-02 | 2004-12-16 | Taiwan Semiconductor Mfg | Semiconductor fabrication method |
| CN101197311A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Metal connecting structure, semiconductor device and its manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583047B2 (en) * | 2000-12-26 | 2003-06-24 | Honeywell International, Inc. | Method for eliminating reaction between photoresist and OSG |
| JP4050631B2 (en) * | 2003-02-21 | 2008-02-20 | 株式会社ルネサステクノロジ | Manufacturing method of electronic device |
| US8124516B2 (en) * | 2006-08-21 | 2012-02-28 | Lam Research Corporation | Trilayer resist organic layer etch |
-
2012
- 2012-10-08 CN CN201210375725.XA patent/CN102915959B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1203442A (en) * | 1997-06-25 | 1998-12-30 | 三星电子株式会社 | Process and apparatus for dry-etching semiconductor layer |
| TW200428582A (en) * | 2003-06-02 | 2004-12-16 | Taiwan Semiconductor Mfg | Semiconductor fabrication method |
| CN101197311A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Metal connecting structure, semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102915959A (en) | 2013-02-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100350056B1 (en) | Method of forming a self-aligned contact pad in a damascene gate process | |
| CN103337475B (en) | The synchronous etching technics of double structure contact hole | |
| US9397004B2 (en) | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings | |
| TWI451490B (en) | Method for fabricating semiconductor device | |
| CN113644028B (en) | Split gate power device and manufacturing method thereof | |
| US20070235798A1 (en) | Method for forming self-aligned contacts and local interconnects simultaneously | |
| US10580688B2 (en) | Method of manufacturing semiconductor device | |
| TWI505455B (en) | Light sensor | |
| TWI398001B (en) | Transistor with contact over gate active area | |
| CN110875339A (en) | Image sensor and method for manufacturing the same | |
| CN102915959B (en) | Method for simplifying etching and forming techniques for word line dielectric film in storage | |
| CN114141702A (en) | Semiconductor structure and forming method thereof | |
| CN109950203B (en) | Integrated manufacturing method of semiconductor device | |
| US20230120621A1 (en) | Memory device and method of fabricating the same | |
| TW202329253A (en) | Method of forming semiconductor device | |
| CN102420174B (en) | Method for filling through hole in dual damascene process | |
| CN100369204C (en) | Method for manufacturing T type polycrystalline silicon gate through double inlaying process | |
| US20030215997A1 (en) | Method of manufacturing semiconductor device | |
| KR20180083814A (en) | Semiconductor device and method for fabricating the same | |
| US9799550B2 (en) | Manufacturing method for forming a semiconductor structure | |
| CN111128871B (en) | Etching process method of contact hole | |
| TWI469269B (en) | Method of forming word line of embedded flash memory | |
| KR100434334B1 (en) | Method for fabricating capacitor of semiconductor device using the dual mask | |
| KR100213210B1 (en) | Manufacturimg method of capacitor of semiconductor devices | |
| KR100312386B1 (en) | Method of forming a gate electrode in a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |