CN102915954B - 低k介电层和成孔剂 - Google Patents
低k介电层和成孔剂 Download PDFInfo
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- CN102915954B CN102915954B CN201210031926.8A CN201210031926A CN102915954B CN 102915954 B CN102915954 B CN 102915954B CN 201210031926 A CN201210031926 A CN 201210031926A CN 102915954 B CN102915954 B CN 102915954B
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- pore former
- dielectric layer
- layer
- dielectric
- resilient coating
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- 239000011148 porous material Substances 0.000 title claims abstract description 113
- 238000000034 method Methods 0.000 claims abstract description 98
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 21
- 125000004432 carbon atom Chemical group C* 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 98
- 239000002243 precursor Substances 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 40
- 239000011248 coating agent Substances 0.000 claims description 29
- 238000000576 coating method Methods 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 16
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- 239000004914 cyclooctane Substances 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- WJTCGQSWYFHTAC-UHFFFAOYSA-N cyclooctane Chemical compound C1CCCCCCC1 WJTCGQSWYFHTAC-UHFFFAOYSA-N 0.000 claims description 5
- 125000002837 carbocyclic group Chemical group 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 125000000640 cyclooctyl group Chemical group [H]C1([H])C([H])([H])C([H])([H])C([H])([H])C([H])(*)C([H])([H])C([H])([H])C1([H])[H] 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 147
- 239000007789 gas Substances 0.000 description 25
- 230000004888 barrier function Effects 0.000 description 10
- 230000008021 deposition Effects 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 125000003118 aryl group Chemical group 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- DMEGYFMYUHOHGS-UHFFFAOYSA-N cycloheptane Chemical compound C1CCCCCC1 DMEGYFMYUHOHGS-UHFFFAOYSA-N 0.000 description 2
- ZSWFCLXCOIISFI-UHFFFAOYSA-N cyclopentadiene Chemical compound C1C=CC=C1 ZSWFCLXCOIISFI-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- PKTOVQRKCNPVKY-UHFFFAOYSA-N dimethoxy(methyl)silicon Chemical compound CO[Si](C)OC PKTOVQRKCNPVKY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- POPACFLNWGUDSR-UHFFFAOYSA-N methoxy(trimethyl)silane Chemical compound CO[Si](C)(C)C POPACFLNWGUDSR-UHFFFAOYSA-N 0.000 description 2
- BFXIKLCIZHOAAZ-UHFFFAOYSA-N methyltrimethoxysilane Chemical compound CO[Si](C)(OC)OC BFXIKLCIZHOAAZ-UHFFFAOYSA-N 0.000 description 2
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- 150000003624 transition metals Chemical class 0.000 description 2
- CPUDPFPXCZDNGI-UHFFFAOYSA-N triethoxy(methyl)silane Chemical compound CCO[Si](C)(OCC)OCC CPUDPFPXCZDNGI-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- YHQGMYUVUMAZJR-UHFFFAOYSA-N α-terpinene Chemical compound CC(C)C1=CC=C(C)CC1 YHQGMYUVUMAZJR-UHFFFAOYSA-N 0.000 description 2
- WZJUBBHODHNQPW-UHFFFAOYSA-N 2,4,6,8-tetramethyl-1,3,5,7,2$l^{3},4$l^{3},6$l^{3},8$l^{3}-tetraoxatetrasilocane Chemical compound C[Si]1O[Si](C)O[Si](C)O[Si](C)O1 WZJUBBHODHNQPW-UHFFFAOYSA-N 0.000 description 1
- 101100504388 Arabidopsis thaliana GFS12 gene Proteins 0.000 description 1
- XDTMQSROBMDMFD-UHFFFAOYSA-N Cyclohexane Chemical compound C1CCCCC1 XDTMQSROBMDMFD-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- -1 alkoxy silane Chemical compound 0.000 description 1
- 150000001343 alkyl silanes Chemical class 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- GAURFLBIDLSLQU-UHFFFAOYSA-N diethoxy(methyl)silicon Chemical compound CCO[Si](C)OCC GAURFLBIDLSLQU-UHFFFAOYSA-N 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 125000000524 functional group Chemical group 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 125000006574 non-aromatic ring group Chemical group 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 1
- RSNQKPMXXVDJFG-UHFFFAOYSA-N tetrasiloxane Chemical compound [SiH3]O[SiH2]O[SiH2]O[SiH3] RSNQKPMXXVDJFG-UHFFFAOYSA-N 0.000 description 1
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 1
- 229940094989 trimethylsilane Drugs 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract
提供了用于低k介电层的***和方法。优选的实施例包括形成基体,以及在基体内形成成孔剂。成孔剂包含具有少于15个碳原子和大比例单键的有机环结构。另外,成孔剂可以具有大于1.3的粘度以及小于0.5的雷诺数。
Description
技术领域
本发明涉及半导体领域,具体而言,本发明涉及介电层和成孔剂。
背景技术
在微型化半导体器件的当前工艺中,为了减少在信号传播中由于电容效应引起的电阻电容(RC)延迟,期望低k介电材料作为导电互连件之间的金属层间和/或层间电介质。鉴于此,电介质的介电层常数越低,邻近导电线的寄生电容就越低,以及集成电路(IC)的RC延迟就越小。
可以通过首先形成前体膜来形成低k介电层。这种前体膜可以具有两种组分,如基体材料和在基体材料内形成的成孔剂材料。一旦在期望低k介电材料存在的区域中形成并固化了前体膜,则可以从前体膜中去除成孔剂,从而形成“孔隙”,该孔隙降低了前体膜的介电常数,并形成低k介电材料。
然而,目前正在使用中的成孔剂,如1-异丙基-4-甲基-1,3-环己二烯(ATRP)或者二环(2.2.1)-庚-2,5-二烯(BCHD),当将它们用于形成低k介电层时,通常具有较差的流动特性。具体而言,这些成孔剂可能不能有效地进行动量扩散,当运输成孔剂时引起横截面中流量改变,以及在整个低k介电层中引起分布不均匀。另外,这些成孔剂的使用还可能形成与下面各层粘合较差的低k材料,并且,为了结合至前体膜内以及在前体膜内交联可能还需要更高的能量。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种用于制造半导体器件的方法,所述方法包括:在衬底上方形成第一材料;以及在所述第一材料内形成第二材料,其中所述第二材料是成孔剂,所述成孔剂包括单键比例大于约80%的有机环结构。
在上述方法中,其中所述成孔剂包含碳原子小于15个的分子。
在上述方法中,其中所述成孔剂包含碳原子小于15个的分子,其中所述成孔剂的粘度大于1.3厘泊,以及雷诺数小于0.5。
在上述方法中,其中所述成孔剂包含碳原子小于15个的分子,其中所述成孔剂的粘度大于1.3厘泊,以及雷诺数小于0.5,其中所述成孔剂包含环辛烷。
在上述方法中,进一步包括去除至少一部分的成孔剂以形成低k介电层。
在上述方法中,进一步包括去除至少一部分的成孔剂以形成低k介电层,其中所述去除至少一部分的成孔剂进一步包括采用退火工艺加热所述成孔剂。
在上述方法中,进一步包括去除至少一部分的成孔剂以形成低k介电层,进一步包括:在所述低k介电层内形成开口;以及用导电材料填充所述开口。
在上述方法中,进一步包括在形成所述第一材料之前,在所述衬底上方形成缓冲层,所述在衬底上方形成第一材料的步骤是直接在所述缓冲层上形成所述第一材料,其中所述缓冲层和所述第一材料包含相同的化合物。
在上述方法中,进一步包括在形成所述第一材料之前,在所述衬底上方形成缓冲层,所述在衬底上方形成第一材料的步骤是直接在所述缓冲层上形成所述第一材料,其中所述缓冲层和所述第一材料包含相同的化合物,所述方法进一步包括在形成所述缓冲层之前,在所述衬底上方形成介电层,所述形成缓冲层的步骤是直接在所述介电层上形成所述缓冲层。
在上述方法中,其中形成所述第二材料进一步包括在形成所述第二材料的整个过程中在恒定流速下引入所述成孔剂。
在上述方法中,其中形成所述第二材料进一步包括在形成所述第二材料的整个过程中在恒定流速下引入所述成孔剂,其中形成所述第一材料进一步包括在形成所述第一材料的整个过程中在恒定流速下引入所述第一材料。
根据本发明的另一方面,还提供了一种用于制造半导体器件的方法,所述方法包括:通过在衬底上共同沉积基体材料和成孔剂来形成前体层,所述成孔剂包含有机分子,所述有机分子具有碳环结构和小于15个的碳原子,其中每个所述碳原子之间的键仅仅是单键;以及通过从所述前体层去除所述成孔剂由所述前体层形成第一介电层。
在上述方法中,其中所述成孔剂的粘度大于1.3厘泊。
在上述方法中,其中所述成孔剂的雷诺数小于0.5。
在上述方法中,其中所述成孔剂是环辛烷。
上述方法中进一步包括:在共同沉积所述基体材料和所述成孔剂之前,在所述衬底上方形成第二介电层,所述共同沉积基体材料和成孔剂的步骤是共同沉积与所述第二介电层物理接触的所述基体材料和所述成孔剂。
上述方法中进一步包括在共同沉积所述基体材料和所述成孔剂之前,在所述衬底上方形成第二介电层,所述共同沉积基体材料和成孔剂的步骤是共同沉积与所述第二介电层物理接触的所述基体材料和所述成孔剂,且上述方法进一步包括在形成所述第二介电层之前,在所述衬底上方形成接触蚀刻停止层,所述形成第二介电层的步骤是形成与所述接触蚀刻停止层物理接触的所述第二介电层。
上述方法中进一步包括:在共同沉积所述基体材料和所述成孔剂之前,在所述衬底上方形成第二介电层,所述共同沉积基体材料和成孔剂的步骤是共同沉积与所述第二介电层物理接触的所述基体材料和所述成孔剂,其中形成所述前体层进一步包括在形成所述前体层的整个过程中在恒定流速下引入所述成孔剂和所述基体材料。
根据本发明的又一方面,还提供了一种半导体器件,包括:衬底;以及介电层,位于所述衬底上方,所述介电层具有的硬度为至少2GPa,以及具有的k值小于约2.6。
在上述半导体器件中,其中所述介电层具有的杨氏模量大于约14GPa。
附图说明
为了更充分地理解本发明及其优点,现在将结合附图所进行的以下描述作为参考,其中:
图1示出了根据实施例的半导体器件;
图2示出了根据实施例的接触蚀刻停止层和第一介电层的形成;
图3示出了根据实施例的第二介电层的形成;
图4示出了根据实施例的用于形成第二介电层的气体分布***;
图5示出了根据实施例的穿过第二介电层的互连件的形成;以及
图6示出了根据实施例的在第二介电层和第一介电层之间形成的缓冲层。
除非另有说明,不同附图中的相应数字和符号通常是指相应的部件。绘制附图用于清楚地示出实施例的相关方面,但不是必须按比例绘制。
具体实施方式
在下面详细讨论实施例的制造和使用。然而,应该理解,实施例提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅是制造和使用实施例的示例性具体方式,并不用于限制实施例的范围。
将参考具体情况下即用成孔剂形成用于互连件的低k介电层的实施例对实施例进行描述。然而,实施例也可以应用于其他介电层。
现在参考图1,示出了具有衬底101、有源器件103、金属化层105和接触件107的半导体器件100。衬底101可以包含掺杂或未掺杂的体硅或者绝缘体上硅(SOI)衬底的有源层。一般来说,SOI衬底包括半导体材料如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)、或者其组合的层。可以使用的其他衬底包括多层衬底、梯度衬底或者混合取向衬底。
有源器件103在图1中表示为单个晶体管。然而,作为本领域技术人员将认识到,可以使用各种有源器件如电容器、电阻器、和电感器等来满足期望的半导体器件100的结构性和功能性设计需求。可以采用任何合适的方法在衬底101内或者在衬底101的表面上形成有源器件103。
金属化层105形成于衬底101和有源器件103的上方,并设计成用于连接各种有源器件103以形成功能电路。虽然在图1中示出的为单层,金属化层105可以由介电材料和导电材料的交替层形成,并可以通过任何合适的工艺(如沉积、镶嵌、双镶嵌等)形成。在实施例中,可以有一个或者多个通过至少一个层间介电层(ILD)与衬底101分开的金属化层,但是金属化层105的确切数量取决于半导体器件100的设计。此外,金属化层105可以不全都是可以用于提供到有源器件103或者来自有源器件103的互连和通路信号导电材料层。
接触件107可以延伸穿过一个或者多个单独的金属化层105以与至少一个有源器件103形成电接触。根据公知的光刻和蚀刻技术可以穿过一个或者多个单独的金属化层105形成接触件107。一般来说,光刻技术包括沉积光刻胶材料,对光刻胶材料进行掩模、暴露、以及显影以暴露部分待去除的一个或者多个单独的金属化层105。剩余的光刻胶材料保护下面的材料不进行后续加工步骤,如蚀刻。利用光刻胶材料来形成经图案化的掩模以限定接触件107。也可以使用可选的掩模,如硬掩模。
一旦已形成了经图案化的掩模,可以通过首先蚀刻经图案化的掩模下面的层,然后在经图案化的层内形成接触件107来形成接触件107。在实施例中,接触件107可以包括用于阻止扩散并在接触件107和一个或者多个单独的金属化层105之间提供更好的粘合性的阻挡/粘合层(未示出)。在实施例中,阻挡层由一层或者多层的钛、氮化钛、钽、或氮化钽等形成。可以通过化学汽相沉积形成阻挡层,但是也可以可选地采用其他技术。可以形成合并厚度为约至约的阻挡层。
接触件107也可以包含合适的导电材料,如高导电性、低电阻的金属、元素金属、或过渡金属等。在实施例中,接触件107可以由钨形成,但是可选地可以利用其他材料,如铜。在接触件107是由钨形成的实施例中,可以通过本领域中公知的化学汽相沉积(CVD)技术沉积接触件107,但是可选地可以使用任何形成方法。
图2示出了第一接触蚀刻停止层(CESL)201和第一介电层203的形成。可以在衬底101和金属化层105的上方形成第一CESL201。第一CESL201可以用于保护衬底101和金属化层105免受由于进一步加工引起的损伤,并为进一步的蚀刻工艺提供控制点。在一个实施例中,第一CESL201可以采用等离子体增强化学汽相沉积(PECVD)由氮化硅形成,但是可以可选地使用其他材料如氮化物、氮氧化物、碳化物、硼化物、或其组合等,以及形成第一CESL201的可选技术,如低压CVD(LPCVD)、或PVD等。第一CESL201具有的厚度可以处于约和约之间,如约
第一介电层203可以形成于第一CESL201的上方,并可以用于帮助进一步屏蔽金属化层105,同时在第一CESL201和下面的第二介电层301之间提供过渡层。第一介电层203可以是例如氧化物层,并可以通过诸如CVD技术的工艺使用四乙基原硅酸盐(TEOS)和氧气作为前体来形成。然而,可以可选地利用其他材料和工艺来形成第一介电层203。在实施例中,可以形成厚度处于约和约之间,如约的第一介电层203。
图3示出了第二介电层301在第一介电层203上方以及直接在第一介电层203上而无介入初始层(IL)或者过渡层(TL)的形成。第二介电层301可以是例如低k介电膜,低k介电膜预期用于帮助隔离互连件501(在图3中未示出,但在下面参考下面的图5示出和讨论)与半导体器件100内的其他结构。通过隔离互连件501,可以减少互连件501的电阻-电容(RC)延迟,从而改进总体效率和通过互连件501的电流的速度。
在实施例中,通过首先在第一介电层203上方形成前体层可以形成第二介电层301。前体层可以包含基体材料和在基体材料内散布的成孔剂二者,或者可以可选地包含基体材料而不包含成孔剂。在实施例中,可以例如通过采用诸如PECVD的工艺共同沉积基体和成孔剂形成前体层,在该实施例中,在与成孔剂的同时沉积基体材料,从而形成具有混合在一起的基体材料和成孔剂的前体层。然而,作为本领域普通技术人员将认识到,采用同步PECVD工艺的共同沉积不是可以用于形成前体层的唯一的工艺。也可以利用任何合适的可选工艺,如将基体材料和成孔剂材料预混合为液体,然后在第一介电层203上旋转涂布该混合物。
可以形成厚度足以提供第二介电层301所期望的隔离和布线特性的前体层。在实施例中,可以形成厚度处于约和约之间,如约 的前体层。然而,这些厚度仅意为示例性的,并不用于限制实施例的范围,因为前体层的确切厚度可以是任何合适的期望厚度。
可以采用诸如PECVD的工艺形成基体材料或者基础介电材料,但是可以可选地利用任何合适的工艺,如CVD、PVD、或者甚至是旋涂。PECVD工艺可以利用前体如甲基二乙氧基硅烷(DEMS),但是可以可选地利用其他前体,如其他硅烷、烷基硅烷(例如,三甲基硅烷和四甲基硅烷)、烷氧基硅烷(例如,甲基三乙氧基硅烷(MTEOS)、甲基三甲氧基硅烷(MTMOS)、甲基二甲氧基硅烷(MDMOS)、三甲基甲氧基硅烷(TMMOS)和二甲基二甲氧基硅烷(DMDMOS))、线性硅氧烷和环硅氧烷(例如,八甲基环四硅氧烷(OMCTS)和四甲基环四硅氧烷(TMCTS)、和这些的组合等。然而,作为本领域普通技术人员将认识到,本文所列出的材料和工艺仅仅是示例性的,并不意为限制实施例,因为可以可选地利用任何其他合适的基体前体。
成孔剂可以是分子,该分子在基体材料已设置之后可以从基体材料中去除,以便在基体内形成孔隙,并从而降低第二介电层301的介电常数的总值。成孔剂可以是足够大以形成孔隙同时又保持足够小使得单个孔隙的尺寸不过度取代基体材料的材料。鉴于此,成孔剂可以包括有机分子,该有机分子在单个成孔剂分子内包含一个或者多个环结构。另外,为了减小单个孔隙的尺寸,单个成孔剂分子应具有小环或者低质量,如在该分子内包含的碳原子小于15个。通过使用环结构并具有低质量,可以对一旦去除成孔剂即形成的单个孔隙的尺寸进行调整以降低第二介电层301的介电常数。
成孔剂还可以是很容易结合至现有工艺中并具有容许其很容易与其他分子键合和交联的高机械性能的材料,如下面的第一介电层203。这两种性能可以通过在环结构内在各个原子之间具有大比例的单键,如是单键的键大于约80%至约100%的材料满足。通过在原子之间具有大比例的是单键的键,并且不具有大量的双键或者叁键,可以很容易地断裂并重新形成各原子间的键,以便容易结合至CVD工艺中,以及容许键很容易被断裂以使单个分子可以比具有双键或者叁键的分子更容易在彼此之间(和各层之间)进行交联。
通过使用具有大比例的容易交联的单键的材料,第二介电层301可以更容易粘合至下面的层,如在图3中所示出的第一介电层203。通过增加第二介电层301的粘合性,可以将先前已利用的初始层(IL)和过渡层(TL)去除,并可以实现约5%的电容增量。
另外,成孔剂也可以是具有合适的流动特性以便有助于获得更一致和均匀的通过制造设备(如下面参考图4所述的气体分布***400)的流量的材料。通过获得更均匀的流量,成孔剂在形成工艺期间可以更均匀地分散在前体层内。例如,成孔剂可以是其粘度大于约1.3厘泊且其雷诺数(Reynoldsnumber)小于约0.5的材料。通过具有这些特性,成孔剂的动量可以在流动的成孔剂之间更快速地扩散,以及成孔剂可以具有更均匀的通过管道(代替该管道处的典型流速,管道中心处的成孔剂比管道壁处的成孔剂更快得通过管道)和通过莲蓬式喷头(在下面参考图4进一步所述的)的流动图案。通过利用这种更均匀的流动,成孔剂可以更均匀地分散在整个基体材料中,形成具有更平均的介电常数的第二介电层301。
在实施例中,成孔剂可以是环状的、非芳香族的、低质量、高粘度、小雷诺数、单键的分子如环辛烷,环辛烷具有带有八个碳原子的非芳香环结构,2.1cPoise的高粘度,0.397的小雷诺数,并在整个环结构中具有单键。然而,可以可选地利用具有一个或多个环结构、在各原子之间具有大比例的单键、低质量、高粘度和小雷诺数的任何合适的分子,如环庚烷、环己烷、环戊二烯。另外,一个或者多个官能团,如甲基基团(-CH3)、乙基基团(-C2H5)、或异丙基基团(-C3H7)等可以连接在环结构的侧面。本文所述的这些成孔剂和所有其他合适的成孔剂预期全部包括在实施例的范围内。
当已用在基体材料内分散的成孔剂形成前体层之后,可以从基体材料去除成孔剂以在基体材料内形成孔隙。可以通过退火工艺实施成孔剂的去除,退火工艺可以分解并蒸发成孔剂材料,从而容许成孔剂材料扩散并保留基体材料,从而留下结构上完整的多孔介电材料作为第二介电层301。例如,可以在约200℃和约500℃之间,如约400℃下实施退火,退火时间处于约10秒和约600秒之间,如约200秒。
然而,作为本领域普通技术人员将认识到,上面所述的热处理不是可以用于从基体材料中去除成孔剂以形成第二介电层301的唯一方法。可以可选地利用其他合适的工艺,如用UV辐射辐射成孔剂以分解成孔剂或者利用微波分解成孔剂。用于去除全部或者部分的成孔剂的这些工艺和任何其他合适的工艺全部预期完全包括在实施例的范围内。
图4示出了气体分布***400,气体分布***400可以用于形成第二介电层301。气体分布***400可以包括腔室401、气体输入区403、和控制器405。腔室401可以能够保持真空,在压板407上容纳衬底101(及其上面的层如第一CESL201和第一介电层203),并通过排气孔409排出气体。而且,在腔室401内设置莲蓬式喷头411。莲蓬式喷头411可以连接于气体输入区403,气体输入区403将气体投入莲蓬式喷头411内。莲蓬式喷头411可以通过气体管道415从气体输入区403同时接收多种气体。机构417可以在适当的位置在结构上支持、加热和旋转衬底101。在另一个实施例中,腔室401可以被配置用于容纳多种工作件。
气体输入区403可以位于气体分布***400的内部,比如,例如气源瓶、交替气源、或连接于外部气体分布区的阀门***等。可选地,气体输入区403可以位于气体分布***400的外部。在任何情况下,可以将多种气体同时输入到莲蓬式喷头411,并且通过莲蓬式喷头411,可以同时将气体输送到腔室401。
控制器405可以是任何适当的微处理器单元,包括在气体分布***400内部或者外部的计算机。控制器405可以控制通过连接件419进入莲蓬式喷头411的气体流量。而且,控制器405可以通过连接件421控制衬底101的温度、衬底101的旋转、和腔室401的真空和/或抽气等。
在实施例中,控制器405控制气体输入区403以同时向腔室401引入基体前体和成孔剂。例如,为了形成前体层,采用处于约100W和约2000W之间,如约800W的RF功率,可以在约100mg/min和约4000mg/min之间,如约2000mg/min的速率下引入基体前体,同时可以在约500mg/min和约5000mg/min之间,如约2000mg/min的速率下引入成孔剂。另外,可以在约50sccm和约1000sccm之间,如约200sccm的流速下引入氧气。另外,通过利用如上面所述的成孔剂,在形成前体层的整个过程中,可以以稳定的流速引入基体前体和成孔剂(而不是首先在较低的流速下开始仅引入基体材料,然后在低流速下引入成孔剂,以及然后持续增速以获得大量的材料)。基体前体和成孔剂共同沉积到第一介电层203上,以便形成前体层。在利用具有大比例单键的环状、非芳香族、低质量、高粘性、小雷诺数的分子如上面所述的那些分子的实施例中,成孔剂可以更均匀地分散在基体材料内,产生更平均的介电常数,并且成孔剂可以更容易交联以及更容易结合至制造工艺内。
图5示出了穿过第二介电层301、第一介电层203和第一CESL201的互连件501的形成。互连件501可以用于提供与下面的金属化层105的电连接,并且如图5中所示,可以在双镶嵌结构中形成,双镶嵌结构包含在相同工艺中形成的通孔503和沟槽505二者。然而,作为本领域普通技术人员将认识到,双镶嵌结构不是可以用于形成互连件501的唯一结构,可以可选地利用其他结构,如单镶嵌结构或者任何其他合适的形成方法。
在实施例中,可以通过首先采用两步蚀刻工艺形成通孔503和沟槽505。可以涂覆初始第一掩模(未示出)来限定通孔503的图案,并且可以实施蚀刻工艺以在第二介电层301内蚀刻通孔503的图案达到处于约 和约之间,如约的深度。掩模可以是例如已被涂覆、图案化、暴露、和显影的光刻胶材料。可以使用其他类型的掩模。
已在第二介电层301中形成通孔503的图案之后,可以以与第一掩模相同的方式涂覆第二掩模(也未示出)来限定沟槽505的图案。然后第二蚀刻工艺可以穿过第二介电层301的剩余距离、穿过第一介电层203以及穿过第一CESL201蚀刻通孔503的图案,以暴露下面的金属化层105,从而形成通孔503的开口。第二蚀刻工艺可以同时形成沟槽505的进入第二介电层301的开口。之后,可以去除任何剩余的光刻胶材料。
在已形成通孔503和沟槽505的开口之后,可以用阻挡/粘合层507和导电材料509填充开口。阻挡/粘合层507可以由一层或者多层导电材料如钛、氮化钛、钽、或氮化钽等形成。在实施例中,阻挡/粘合层507可以由采用PVD技术沉积的氮化钽薄层和钽薄层形成。在实施例中,氮化钽层和钽层的合并厚度是约至约
用于填充通孔503和沟槽505的开口的导电材料509可以是例如铜。可以例如通过首先沉积种子层(未示出),然后在种子层上电镀导电材料509来填充通孔503和沟槽505的开口,直到导电材料509填充和过度填充通孔503和沟槽505的开口。导电材料509可以可选地包含金属、元素金属、或过渡金属等。
一旦导电材料509已填充了通孔503和沟槽505的开口,阻挡/粘合层507和导电材料509可以与第二介电层301一起进行平坦化。平坦化工艺可以是例如化学机械抛光,化学机械抛光通过化学反应和机械研磨去除导电材料509和阻挡/粘合层507,直到导电材料509和阻挡/粘合层507与第二介电层301是平坦的。在实施例中,当已完成了平坦化工艺时,沟槽505可以在第二介电层内延伸处于约和约之间,如约的距离,同时通孔503可以在沟槽505下面延伸处于约和约之间,如约的距离。
图6示出了其中在形成第二介电层301之前可以在第一介电层203上形成可选的缓冲层601的另一实施例。可以采用与第二介电层301相同的工艺和前体(例如,利用DEMS和环辛烷的PECVD)制成缓冲层601,但是为了改进缓冲层601和下面的第一介电层203之间的粘合性可以更改沉积参数。例如,用于缓冲层601的成孔剂的流速可以小于用于第二介电层301的成孔剂的流速(在上面参考图3和图4所述的)。
在实施例中,用于缓冲层601的成孔剂的流速可以处于约100mg/min和约4000mg/min之间,如约2000mg/min,同时用于基体材料的前体可以小于约5000mg/min,如约1000mg/min。另外,为了形成缓冲层601,可以在约50sccm和约1000sccm之间,如约200sccm的流速下引入氧气,或者可以将RF功率调节至处于约100W和约2000W之间,如约800W。
通过调节沉积参数,为了有助于第二介电层301粘合至第一介电层203,用于缓冲层601的介电材料的粘合性可以增大。另外,通过使用与第二介电层相同的材料,缓冲层601可以仅遇到在缓冲层601的介电常数和第二介电层301的介电常数之间的小差值,从而有助于改进对半导体器件100的总介电常数具有最小效应的粘合性。缓冲层601的厚度可以处于约和约之间,如约
通过利用具有大比例单键的环状、非芳香族、低质量、高粘度、小雷诺数的分子作为成孔剂,第二介电层301可以具有低介电常数,如2.6或者低于2.6,同时保持硬度为2GPa或者大于2GPa,以及杨氏模量大于约14GPa。这些性能实现了低介电常数以及更容易的工艺联合和孔隙在第二介电层301内更均匀的分散。这容许第二介电层301更好地隔离互连件501和其他结构,而且不使制造工艺复杂化,有助于将半导体器件微型化至低于28纳米技术节点如20纳米技术节点,或者更低。
根据实施例,提供了用于制造半导体器件的方法,该方法包括在衬底上方形成第一材料;在第一材料内形成第二材料,其中第二材料是成孔剂,成孔剂包含单键比例大于约80%的有机环结构。
根据另一实施例,提供了用于制造半导体器件的方法,该方法包括通过在衬底上共同沉积基体材料和成孔剂形成前体层,成孔剂包括有机分子,该有机分子具有碳环结构和小于15的碳原子,其中每个碳原子之间的键仅是单键;通过从前体层去除成孔剂由前体层形成第一介电层。
根据又一个实施例,提供了半导体器件,该半导体器件包括衬底;位于衬底上方的介电层,该介电层具有至少为2Gpa的硬度和小于约2.6的k值。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明的精神和范围的情况下,进行各种不同的改变、替换和更改。例如,用于成孔剂的确切化学品可以不同于本文所显示的示例性实施例。另外,可以采用其他工艺形成第二介电层,同时仍保持在实施例的范围内。
而且,本申请的范围预期并不限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的公开内容应很容易理解,根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同功能或获得基本上相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。
Claims (15)
1.一种用于制造半导体器件的方法,所述方法包括:
在衬底上方形成第一材料;
在所述第一材料内形成第二材料,其中所述第二材料是成孔剂,所述成孔剂包括单键比例大于80%的有机环结构;
并且,该方法进一步包括在形成所述第一材料之前,在所述衬底上方形成缓冲层,在衬底上方形成第一材料的步骤是直接在所述缓冲层上形成所述第一材料,其中所述缓冲层和所述第一材料包含相同的化合物;
在形成所述缓冲层之前,在所述衬底上方形成介电层,形成缓冲层的步骤是直接在所述介电层上形成所述缓冲层;以及
在形成所述介电层之前,在所述衬底和金属化层的上方形成第一接触蚀刻停止层,其中,所述介电层形成于所述第一接触蚀刻停止层的上方。
2.根据权利要求1所述的方法,其中所述成孔剂包含碳原子小于15个的分子。
3.根据权利要求2所述的方法,其中所述成孔剂的粘度大于1.3厘泊,以及雷诺数小于0.5。
4.根据权利要求3所述的方法,其中所述成孔剂包含环辛烷。
5.根据权利要求1所述的方法,进一步包括去除至少一部分的成孔剂以形成低k介电层。
6.根据权利要求5所述的方法,其中所述去除至少一部分的成孔剂进一步包括采用退火工艺加热所述成孔剂。
7.根据权利要求5所述的方法,进一步包括:
在所述低k介电层内形成开口;以及
用导电材料填充所述开口。
8.根据权利要求1所述的方法,其中形成所述第二材料进一步包括在形成所述第二材料的整个过程中在恒定流速下引入所述成孔剂。
9.根据权利要求8所述的方法,其中形成所述第一材料进一步包括在形成所述第一材料的整个过程中在恒定流速下引入所述第一材料。
10.一种用于制造半导体器件的方法,所述方法包括:
通过在衬底上共同沉积基体材料和成孔剂来形成前体层,所述成孔剂包含有机分子,所述有机分子具有碳环结构和小于15个的碳原子,其中每个所述碳原子之间的键仅仅是单键;
通过从所述前体层去除所述成孔剂由所述前体层形成第一介电层;
在形成所述第一介电层之前,在第二介电层上形成缓冲层;以及
在形成所述第二介电层之前,在所述衬底上方形成接触蚀刻停止层,其中,所述第二介电层形成于所述接触蚀刻停止层的上方。
11.根据权利要求10所述的方法,其中所述成孔剂的粘度大于1.3厘泊。
12.根据权利要求10所述的方法,其中所述成孔剂的雷诺数小于0.5。
13.根据权利要求10所述的方法,其中所述成孔剂是环辛烷。
14.根据权利要求10所述的方法,其中,形成第二介电层的步骤是形成与所述接触蚀刻停止层物理接触的所述第二介电层。
15.根据权利要求10所述的方法,其中形成所述前体层进一步包括在形成所述前体层的整个过程中在恒定流速下引入所述成孔剂和所述基体材料。
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2011
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- 2012-02-01 TW TW101103223A patent/TWI604531B/zh active
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CN100340004C (zh) * | 2003-08-14 | 2007-09-26 | 台湾积体电路制造股份有限公司 | 半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN102915954A (zh) | 2013-02-06 |
US10134632B2 (en) | 2018-11-20 |
TW201308429A (zh) | 2013-02-16 |
US9054110B2 (en) | 2015-06-09 |
KR20130016007A (ko) | 2013-02-14 |
US20130032955A1 (en) | 2013-02-07 |
KR101464029B1 (ko) | 2014-11-20 |
US20150270189A1 (en) | 2015-09-24 |
US9564383B2 (en) | 2017-02-07 |
US20170148676A1 (en) | 2017-05-25 |
TWI604531B (zh) | 2017-11-01 |
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