CN102915703A - Pixel driving circuit and driving method thereof - Google Patents
Pixel driving circuit and driving method thereof Download PDFInfo
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Abstract
The invention discloses a pixel driving circuit and a driving method thereof. The pixel driving circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, storage capacitors, an organic light emitting diode (OLED), a bypass circuit, a data line, an N-1st scanning line and an Nth scanning line. A second end of the storage capacitor is connected with a source electrode of the first transistor, and the OLED is connected with the bypass circuit in parallel, so that current flowing through the OLED is completely determined by data voltage and is irrelevant to threshold voltage of the first transistor; the current flowing through the OLED completely relays on the data voltage of the data line, without increasing the number of the transistors, the capacitors and control lines too much, the threshold voltage can be accurately compensated in order to maintain uniformity and constancy of the display brightness, the aperture ratio and the display resolution can be improved easily, and the capability of inhibiting nonuniform distribution of the threshold voltage is improved; therefore, the pixel driving circuit and the driving method thereof have a relatively high practical value and can be expected to be widely used in a microelectronic industry and a flat panel display industry.
Description
Technical field
The invention belongs to the flat pannel display field, be specifically related to a kind of pixel-driving circuit and driving method thereof.
Background technology
It is little that active matrix organic light-emitting diode (Active Matrix Organic Light-Emitting Diode) AMOLED has a volume, simple in structure, from advantages such as main light emission, brightness are high, image quality is good, visible angle is large, low in energy consumption and response time is short, thereby cause extensive concern, become most probably the display technique of future generation that replaces liquid crystal.
Current, the thin film transistor (TFT) TFT that is used for driving AMOLED mainly contains amorphous silicon film transistor and polycrystalline SiTFT.Because the characteristic of organic light emitting diode OLED current drives, OLED needs large electric current to drive, because amorphous silicon film transistor can't provide enough drive currents because carrier mobility is low, and the carrier mobility of polycrystalline SiTFT and metal oxide semiconductor transistor much larger than amorphous silicon film transistor because carrier mobility, can satisfy the requirement of driving OLED, thereby polycrystalline SiTFT and metal oxide semiconductor transistor become the first-selection of driving OLED.In the prior art, usually adopt the pixel-driving circuit of an electric capacity 2T1C of two transistors to be used for driving OLED.But as driving tube, because the grain boundary stochastic distribution of polycrystalline silicon material, the threshold voltage of multi-crystal TFT is skewness between each pixel of viewing area, causes the viewing area brightness irregularities with multi-crystal TFT; Most of metal-oxide semiconductor (MOS) also is polycrystalline structure, also has threshold voltage problem pockety between each pixel.Therefore, the pixel-driving circuit structure of a traditional electric capacity 2T1C of two transistors is not suitable for high-quality AMOLED demonstration.In order to realize the compensation to the threshold voltage of driving tube, need to better drive image element circuit by circuit compensation.
Yet in the prior art, the design of most of AMOLED pixel-driving circuit can only compensate the threshold voltage of driving tube to a certain extent, can not accurately eliminate the inhomogeneous problem of demonstration of being brought by the threshold value skewness.
Summary of the invention
For defective and the deficiency that overcomes above-mentioned prior art, the invention provides a kind of pixel-driving circuit and driving method thereof of AMOLED of threshold voltage of fine compensation driving tube.
One object of the present invention is to provide a kind of pixel-driving circuit.
Pixel-driving circuit of the present invention comprises: the first transistor to the four transistors, memory capacitance, organic light emitting diode OLED, bypass circuit, data line, N-1 sweep trace and N sweep trace; Wherein, N is natural number,
The drain electrode of the first transistor connects supply voltage, and grid connects the first end of memory capacitance, and source electrode connects the second end of memory capacitance and the anode of OLED;
The drain and gate of transistor seconds connects the grid of first end, the 3rd transistorized source electrode and the first transistor of memory capacitance, and source electrode connects the 4th transistorized drain electrode;
The 3rd transistorized grid connects the N-1 sweep trace, and drain electrode connects supply voltage, and source electrode connects the grid of memory capacitance, the first transistor and the drain and gate of transistor seconds;
The 4th transistorized grid connects the N sweep trace, and drain electrode connects the source electrode of transistor seconds, and source electrode connects data line;
Grid and the drain electrode of the grid of the first termination the first transistor of memory capacitance, the 3rd transistor source and transistor seconds, the anode of the second termination OLED and the source electrode of the first transistor;
The anode of OLED connects the second end of memory capacitance and the source electrode of the first transistor, plus earth;
Bypass circuit is in parallel with OLED, and two control ends connect respectively N-1 sweep trace and N sweep trace.
The first transistor is as driving tube, for OLED provides drive current.
Transistor seconds, the 3rd transistor and bypass circuit are high level and sweep trace N sweep trace when being low level at the N-1 sweep trace, and memory capacitance is carried out precharge.
Transistor seconds, the 4th transistor and bypass circuit are low level and N sweep trace when being high level at the N-1 sweep trace, and data voltage is written to the grid of the first transistor and is stored in memory capacitance.
Sweep trace when the N sweep trace is the N time programming; Sweep trace when the N-1 sweep trace is the N-1 time programming.
The first transistor to the four transistors adopt polycrystalline SiTFT or metal oxide semiconductor transistor.
In the viewing area, each pixel is positioned at zones of different, therefore the drift of transistorized threshold voltage of pixel that is positioned at zones of different different (increase or reduce), and the drift of the transistorized threshold voltage in same pixel is consistent (increases simultaneously or reduce).Therefore, in same pixel, the first transistor and transistor seconds arrange middle close-packed arrays at domain, and measure-alike, so that both threshold voltages remain in the same size in same pixel, i.e. and V
TH1=V
TH2
Bypass circuit is in parallel with OLED, and two control ends connect respectively N-1 sweep trace and N sweep trace.When programming state, namely the N-1 sweep trace is that high level and N sweep trace are low level, or the N-1 sweep trace is that low level and N sweep trace are when being high level, the bypass circuit conducting, electric current passes through from bypass circuit, and OLED is bypassed, thereby OLED is not luminous, avoid when the N-1 sweep trace is high level, having large electric current to flow through the situation of OLED, be conducive to improve aperture opening ratio and display resolution.
The second termination of OLED is as the source electrode of the first transistor of driving tube, avoided in the impact on OLED of the drive current of working stage.
Another object of the present invention is to provide a kind of driving method of above-mentioned pixel-driving circuit.
A kind of driving method of pixel-driving circuit may further comprise the steps:
1) the default stage: the N-1 sweep trace is that high level and N sweep trace are low level, and in this stage, transistor seconds and the 3rd transistor are opened, the bypass circuit conducting, and supply voltage is precharged to supply voltage to memory capacitance;
2) adjusting stage: the N-1 sweep trace is that low level and N sweep trace are the high level stage, in this stage, transistor seconds and the 4th transistor are opened, the bypass circuit conducting, memory capacitance is by transistor seconds and the discharge of the 4th transistor, stop discharge until transistor seconds enters cut-off state, the voltage on the memory capacitance is the threshold voltage that data voltage adds transistor seconds at this moment;
3) working stage: N-1 sweep trace and N sweep trace are low level, in this stage, and transistor seconds, the 4th transistor and bypass circuit cut-off, the voltage at memory capacitance two ends remains unchanged, and wherein, N is natural number.
At working stage, because transistor seconds, the 4th transistor and bypass circuit cut-off, there is not the path of releasing in memory capacitance, so the voltage at the two ends of memory capacitance remains unchanged, so the time voltage on the memory capacitance be the anode voltage sum of threshold voltage and the OLED of data voltage, transistor seconds.Be the electric current that flows through OLED and flow through the electric current of the first transistor this moment, square being directly proportional of the gate source voltage of its size of current direct ratio and the first transistor and the difference of threshold voltage, and the threshold voltage of the first transistor equals the threshold voltage of transistor seconds, therefore flow through OLED electric current with square being directly proportional of data voltage.Therefore flow through the electric current of OLED fully by the data voltage decision, and irrelevant with the threshold voltage of the first transistor.
In the prior art, the second end ground connection of OLED, the electric current that flows through OLED is directly proportional with the difference of supply voltage with the cut-in voltage of OLED.In the present invention, because the second end of memory capacitance connects the source electrode of the first transistor, square being directly proportional of the electric current that flows through like this OLED and data voltage.Therefore, in the identical situation of the electric current that guarantees to flow through OLED, data voltage of the present invention can be much smaller.Because data voltage is larger, just poorer for suppressing threshold voltage ability pockety, therefore, the present invention can be in the identical situation of the electric current that guarantees to flow through OLED, effectively reduce data voltage, greatly improved inhibition threshold voltage ability pockety.
Beneficial effect of the present invention:
Pixel-driving circuit of the present invention, the source electrode of the second termination the first transistor of employing memory capacitance, and OLED is in parallel with bypass circuit, is determined by data voltage fully so that flow through the electric current of OLED, and irrelevant with the threshold voltage of the first transistor.The present invention is when exceeding the quantity that increases transistor, electric capacity and control line, the electric current of the OLED data voltage of data line that places one's entire reliance upon so that flow through, can realize accurately that threshold voltage compensation is to keep the evenly constant of display brightness, be conducive to improve aperture opening ratio and display resolution, and can be in the identical situation of the electric current that guarantees to flow through OLED, effectively reduce data voltage, greatly improved inhibition voltage ability pockety.Therefore, the present invention has higher practical value, is expected to be widely used in microelectronics and dull and stereotyped display industries.
Description of drawings
Fig. 1 is the circuit diagram of the embodiment one of pixel-driving circuit of the present invention;
Fig. 2 is the circuit diagram of the embodiment two of pixel-driving circuit of the present invention;
Fig. 3 is the signal timing diagram of embodiments of the invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described by embodiment.
Embodiment one
Pixel-driving circuit of the present invention comprises: the first transistor T1 to the four transistor Ts 4, memory capacitance C
S, organic light emitting diode OLED, bypass circuit, data line, N-1 sweep trace V
N-1With N sweep trace V
NWherein,
The drain electrode of the first transistor T1 connects supply voltage, and grid meets memory capacitance C
SFirst end, source electrode meets memory capacitance C
SThe second end and the anode of OLED;
The drain and gate of transistor seconds T2 meets memory capacitance C
SFirst end, the source electrode of the 3rd transistor T 3 and the grid of the first transistor T1, source electrode connects the drain electrode of the 4th transistor T 4;
The grid of the 3rd transistor T 3 connects the N-1 sweep trace, and drain electrode connects supply voltage, and source electrode meets memory capacitance C
S, the grid of the first transistor T1 and the drain and gate of transistor seconds T2;
The grid of the 4th transistor T 4 connects the N sweep trace, and drain electrode connects the source electrode of transistor seconds T2, and source electrode connects data line;
Memory capacitance C
SGrid and the drain electrode of grid, the 3rd transistor T 3 source electrodes and transistor seconds T2 of the first termination the first transistor T1, the source electrode of the anode of the second termination OLED and the first transistor T1;
The anode of OLED connects the second end of memory capacitance and the source electrode of the first transistor T1, plus earth;
In the present embodiment, bypass circuit is asynchronous double grid thin film transistor (TFT) T5, and is in parallel with OLED, and drain electrode connects the anode of OLED, source ground, and the top gate electrode meets N-1 sweep trace V
N-1, bottom gate thin film meets N sweep trace V
N
Transistor seconds T2, the 3rd transistor T 3 and the 5th transistor T 5 are at sweep trace V
N-1Be high level and sweep trace V
NDuring for low level to memory capacitance C
SCarry out preliminary filling.
Transistor seconds T2, the 4th transistor T 4 and the 5th transistor T 5 are at sweep trace V
N-1Be low level and sweep trace V
NDuring for high level data voltage is written to the grid of the first transistor and is stored in memory capacitance C
S
The first transistor and transistor seconds close-packed arrays in layout design is designed to same size so that in same pixel the threshold voltage V of the first transistor and transistor seconds
TH1And V
TH2In the same size, i.e. V
TH1=V
TH2
In the present embodiment, the parameter of each element is respectively: VDD gets 12V; V
N-1Get 10V during high level, 50uS holds time; V
NGet 10V during high level, 50uS holds time; C
SElectric capacity is got 0.5pS; The breadth length ratio of T1 is set to 18um/6um; The breadth length ratio of T2 is set to 18um/6um; The breadth length ratio of T3 is set to 6um/6um; The breadth length ratio of T4 is set to 6um/6um; The breadth length ratio of T5 is set to 6um/6um.
The sequential of each signal wire as shown in Figure 3, the driving method of above-mentioned pixel-driving circuit may further comprise the steps:
1) the default stage (stage 1): N-1 sweep trace V
N-1Be high level and N sweep trace V
NBe low level, in this stage, transistor seconds T2, the 3rd transistor T 3 and the 5th transistor T 5 are opened supply voltage V
DDTo memory capacitance C
SBe precharged to supply voltage V
DD
2) adjusting stage (stage 2): N-1 sweep trace V
N-1Be low level and N sweep trace V
NBe the high level stage, in this stage, transistor seconds T2, the 4th transistor T 4 and the 5th transistor T 5 are opened memory capacitance C
SBy transistor seconds T2 and 4 discharges of the 4th transistor T, until entering cut-off state, transistor seconds T2 stops discharge, at this moment memory capacitance C
SOn voltage be data voltage V
DATAAdd the threshold voltage V of transistor seconds
TH2, i.e. V
DATA+ V
TH2
3) working stage (stage 3): N-1 sweep trace V
N-1With N sweep trace V
NBe low level, in this stage, transistor seconds T2, the 4th transistor T 4 and 5 cut-offs of the 5th transistor T, memory capacitance C
SThe voltage at two ends remains unchanged, and wherein, N is natural number.
At working stage, since transistor seconds T2, the 4th transistor T 4 and 5 cut-offs of the 5th transistor T, memory capacitance C
SThere is not the path of releasing, so memory capacitance C
SThe voltage at two ends remain unchanged, so the time voltage on the memory capacitance be the anode voltage sum of threshold voltage and the OLED of data voltage, transistor seconds, i.e. V
DATA+ V
TH2+ V
OLED, V wherein
OLEDCut-in voltage for OLED.Be the electric current that flows through OLED, the gate source voltage V of size of current direct ratio and the first transistor T1 and flow through the electric current of the first transistor T1 this moment
GS1With threshold voltage V
TH1Square being directly proportional of difference, i.e. (V
GS1-V
TH1)
2, (V namely
DATA+ V
TH2+ V
OLED-V
OLED-V
TH1)
2, and the threshold voltage V of the first transistor and transistor seconds
TH1And V
TH2Equate, i.e. V
TH1=V
TH2, namely, flow through OLED electric current with square being directly proportional of data voltage, i.e. V
DATA 2Therefore flow through the electric current of OLED fully by data voltage V
DATADetermine, and with the threshold voltage V of the first transistor
TH1Irrelevant.
Embodiment two
In the present embodiment, bypass circuit is the 6th transistor and the 7th transistor T 6 and T7 in parallel, and in parallel with OLED, the drain electrode of T6 and T7 connects respectively the anode of OLED, the source ground of T6 and T7, and the grid of T6 meets N-1 sweep trace V
N-1, the grid of T7 meets N sweep trace V
N, other circuit connects identical with embodiment one, as shown in Figure 2.
The drive scheme of above-mentioned pixel-driving circuit may further comprise the steps:
1) the default stage: N-1 sweep trace V
N-1Be high level and N sweep trace V
NBe low level, in this stage, transistor seconds T2, the 3rd transistor T 3 and the 6th and the 7th transistor T 6 and T7 open, supply voltage V
DDTo memory capacitance C
SBe precharged to supply voltage V
DD
2) adjusting stage: N-1 sweep trace V
N-1Be low level and N sweep trace V
NBe the high level stage, in this stage, transistor seconds T2, the 4th transistor T 4 and the 6th and the 7th transistor T 6 and T7 open, memory capacitance C
SBy transistor seconds T2 and 4 discharges of the 4th transistor T, until entering cut-off state, transistor seconds T2 stops discharge, at this moment memory capacitance C
SOn voltage be data voltage V
DATAAdd the threshold voltage V of transistor seconds
TH2, i.e. V
DATA+ V
TH2
3) working stage: N-1 sweep trace V
N-1With N sweep trace V
NBe low level, in this stage, transistor seconds T2, the 4th transistor T 4 and the 6th and the 7th transistor T 6 and T7 cut-off, memory capacitance C
SThe voltage at two ends remains unchanged.
With embodiment one in like manner, memory capacitance C
SThe voltage at two ends remains unchanged, and the electric current that flows through the first transistor T1 is the electric current that flows through OLED, is proportional to V
DATA 2So flow through the electric current of OLED fully by V
DATADetermine, and with the threshold voltage V of the first transistor
TH1Irrelevant.
It should be noted that at last, the purpose of publicizing and implementing mode is to help further to understand the present invention, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various substitutions and modifications all are possible.Therefore, the present invention should not be limited to the disclosed content of embodiment, and the scope of protection of present invention is as the criterion with the scope that claims define.
Claims (6)
1. a pixel-driving circuit is characterized in that, described pixel-driving circuit comprises: the first transistor T1 to the four transistor Ts 4, memory capacitance C
S, organic light emitting diode OLED, bypass circuit, data line, N-1 sweep trace V
N-1With N sweep trace V
NWherein, N is natural number,
The drain electrode of described the first transistor T1 connects supply voltage, and grid connects the first end of memory capacitance, and source electrode connects the second end of memory capacitance and the anode of OLED;
The drain and gate of described transistor seconds T2 connects the first end of memory capacitance, the source electrode of the 3rd transistor T 3 and the grid of the first transistor T1, and source electrode connects the drain electrode of the 4th transistor T 4;
The grid of described the 3rd transistor T 3 connects the N-1 sweep trace, and drain electrode connects supply voltage, and source electrode connects the grid of memory capacitance, the first transistor T1 and the drain and gate of transistor seconds T2;
The grid of described the 4th transistor T 4 connects the N sweep trace, and drain electrode connects the source electrode of transistor seconds T2, and source electrode connects data line;
Described memory capacitance C
SGrid and the drain electrode of grid, the 3rd transistor T 3 source electrodes and transistor seconds T2 of the first termination the first transistor T1, the source electrode of the anode of the second termination OLED and the first transistor T1;
The anode of described OLED connects the second end of memory capacitance and the source electrode of the first transistor T1, plus earth;
Described bypass circuit is in parallel with OLED, and two control ends connect respectively N-1 sweep trace and N sweep trace.
2. pixel-driving circuit as claimed in claim 1 is characterized in that, described the first transistor to the four transistor Ts 1 to T4 adopt polycrystalline SiTFT or metal oxide semiconductor transistor.
3. pixel-driving circuit as claimed in claim 1 is characterized in that, described the first transistor and transistor seconds close-packed arrays in layout design is designed to same size so that in same pixel the threshold voltage V of the first transistor and transistor seconds
TH1And V
TH2In the same size, i.e. V
TH1=V
TH2
4. pixel-driving circuit as claimed in claim 1 is characterized in that, described bypass circuit is asynchronous double grid thin film transistor (TFT) T5, and is in parallel with OLED, and drain electrode connects the anode of OLED, source ground, and the top gate electrode meets N-1 sweep trace V
N-1, bottom gate thin film meets N sweep trace V
N
5. pixel-driving circuit as claimed in claim 1, it is characterized in that, described bypass circuit is the 6th transistor and the 7th transistor T 6 and T7 in parallel, in parallel with OLED, the drain electrode of described the 6th transistor and the 7th transistor T 6 and T7 connects respectively the anode of OLED, source ground, the grid of the 6th transistor T 6 meets N-1 sweep trace V
N-1, the grid of the 7th transistor T 7 meets N sweep trace V
N
6. the driving method of the described pixel-driving circuit of claim 1 is characterized in that, described driving method may further comprise the steps:
1) the default stage: the N-1 sweep trace is that high level and N sweep trace are low level, and in this stage, transistor seconds and the 3rd transistor are opened, the bypass circuit conducting, and supply voltage is precharged to supply voltage to memory capacitance;
2) adjusting stage: the N-1 sweep trace is that low level and N sweep trace are the high level stage, in this stage, transistor seconds and the 4th transistor are opened, the bypass circuit conducting, memory capacitance is by transistor seconds and the discharge of the 4th transistor, stop discharge until transistor seconds enters cut-off state, the voltage on the memory capacitance is the threshold voltage that data voltage adds transistor seconds at this moment;
3) working stage: N-1 sweep trace and N sweep trace are low level, in this stage, and transistor seconds, the 4th transistor and bypass circuit cut-off, the voltage at memory capacitance two ends remains unchanged, and wherein, N is natural number.
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