CN102915281B - Cache system and cache method of high-reliable spacecraft frame format data queue - Google Patents
Cache system and cache method of high-reliable spacecraft frame format data queue Download PDFInfo
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Abstract
The invention discloses a cache system and a cache method of a high-reliable spacecraft frame format data queue. In the system, a second-level address management mechanism is designed on the basis of a dual port memory; the second-level address management mechanism is divided into frame grade address management and data grade address management; the second-level address management mechanism is mapped to a physical address of the dual port memory through a second-level scaling circuit; and a frame write-in address scaling unit, a frame read-out address scaling unit, a frame address management unit, a writing frame detection unit, a reading frame detection unit and the like are designed. A spacecraft frame format data queue memory which is complete in function and has queue storage and reading operation in a mode that a data frame structure is used as the unit is realized. The cache system is simple in principle, strong in function, small in resource expense, high in robustness and strong in application; and a diversity of hidden fault dangers which influence the data frame format displacement and breakage expansion caused by abnormal data of an on-track satellite are eliminated.
Description
Technical field
The invention belongs to aerospace electron technical field, relate to a kind of highly reliable spacecraft frame format data queue's caching system and caching method.
Background technology
Spacecraft telecommand telemetry frame has specific protocol and corresponding data call format, when frame format is upset or destroyed, can cause makeing mistakes when interpretation data according to the software/hardware of this Protocol Design, produce serious fault.And the inner each subsystem of spacecraft, equipment, chip chamber need to carry out the miscellaneous data communication of quantity, and all transmit with the form of interface protocol specified data format frame.At present, traditional spacecraft telecommand telemetry frame buffer adopts the method for FIFO or ping-pong buffer usually.First, the method adopting FIFO to carry out buffer memory has larger data frame structure and destroys hidden danger, and its phenomenon of the failure shows:
1) read and write and wrongly cause frame structure lock-out: when write signal or read signal cause read/write signal increase than the frame format that agreement specifies or reduce some data due to events such as chip temperature is overheated, the interference of spatial electromagnetic irradiation, frame format lock-out will be there is, frame format in the every frame data read from FIFO according to agreement frame format protocol after showing as all can have offset error, and irrecoverable before the FIFO that again resets.
2) moment difference is powered up between distinct device, when receiving equipment power on the moment be transmitting terminal launch one in the middle of frame data time, the incomplete Frame write in local FIFO can be caused, when carrying out FIFO reading according to Frame Protocol, the frame format placement error of subsequent frame will be caused; Although the method that this fault can adopt receiving end to detect first whole frame is avoided, too increase design complexities.
3) sending ending equipment breaks down, and power-off-when heavily powering up, power-off causes ending frame data imperfect, can cause the frame format placement error of subsequent frame too; And whether receiving end detection transmitting terminal interrupted Comparision difficulty.
Based on above reason, in the Spacecraft Electronic system pursuing high reliability, should avoid using traditional F IFO to carry out the buffering of frame structure data as far as possible.
Adopt the method for ping-pong buffer to carry out Frame alternately, the fault effects diffusion that above-mentioned FIFO can be avoided to introduce, but the method for ping-pong buffer generally supports the buffer depth of two Frames, and designer use not as good as FIFO conveniently.
In addition, carry out in a particular application Frame choose the operation such as frame, frame-skipping, frame losing time, classic method based on above two kinds of structures needs to be equipped with complicated control circuit, add the complexity of design, reduce design readability and fiduciary level in a way, the design maintenance cost in later stage is also higher.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of highly reliable spacecraft frame format data queue's caching system and caching method, utilize the thought design frame structure queue memory of two-level address mapping and frame structure queue, solve and control at spacecraft frame structure data buffer storage the difficult problem that complexity is high, reliability is low.
Technical solution of the present invention is: a kind of highly reliable spacecraft frame format data queue caching system, comprises double port memory, frame writing address scaling unit, frame reading address scaling unit, frame address administrative unit, writes frame detecting unit, reads frame detecting unit;
Write frame detecting unit definition write Frame detection criteria, according to address W_Addr_M output detections signal in this criterion and write Frame and high level or low level frame write-enable signal to frame address administrative unit;
Read frame detecting unit definition sense data frame detection criteria, read enable signal to frame address administrative unit according to address R_Addr_M output detections signal in this criterion and sense data frame and high level or low level frame;
Frame address administrative unit receives the detection signal read frame detecting unit and write frame detecting unit, and the detection signal according to receiving determines the frame address W_Addr_L of current write data and the frame address R_Addr_L of current sense data;
Frame writing address scaling unit produces the write physical address W_ddr_RAM of double port memory according to the frame level address W_Addr_L of address W_Addr_M and current write data in write Frame;
Frame reads address scaling unit produces double port memory reading physical address R_Addr_RAM according to the frame level address R_Addr_L of address R_Addr_M and current sense data in sense data frame;
Double port memory, have a read port and a write port, memory depth is M × L, and bit wide is n bit; Write physical address W_Addr_RAM according to double port memory writes frame data with reading physical address R_Addr_RAM, reads frame data to complete spacecraft frame format data queue buffer memory in double port memory; Wherein M is every frame data length, and L is frame queue capacity, and data bit width is nbit;
Above-mentioned frame level address realm 0 ~ L-1; Address realm 0 ~ M-1 in frame.
Described frame address administrative unit determines that the rule of the frame address W_Addr_L of current write data and the frame address R_Addr_L of current sense data is:
When frame write-enable signal effectively and discontented time, frame writing address W_Addr_L increases by 1, and increasing spilling after counting down to L-1 is again 0, cycle count;
When frame read enable signal effectively and not empty time, frame read address R_Addr_L increase by 1, increasing spilling after counting down to L-1 is again 0, cycle count.
Described W_Addr_RAM=W_Addr_L × M+W_Addr_M.
Described R_Addr_RAM=R_Addr_L × M+R_Addr_M.
Described write Frame detection criteria is: under the effective prerequisite of write enable signal of outside input, when address W_Addr_M is M-1 in write Frame, be judged to the write of a frame, otherwise frame level write address adds 1.
Sense data frame detection criteria is: outside input read the effective prerequisite of enable signal under, when address R_Addr_M is M-1 in sense data frame, be judged to the reading of a frame, otherwise frame level is read address and is added 1.
The technical scheme of the inventive method is: a kind of highly reliable spacecraft frame format data queue caching method, is characterized in that step is as follows:
(1) choose double port memory as physical data storage, this RAM possesses two ports, one for reading interface, another is for writing interface;
(2) determine the parameter of double port memory, suppose that M is every frame data length, L is frame queue capacity, and data width is n bit, and so the degree of depth of this dual port RAM should be M × L, and width is n bit;
(3) carry out classification to data address, be altogether two-stage, the first order is frame level address Addr_L, and address realm is 0 to L-1, for the frame structure in inside addressing double port memory; The second level is intraframe data address Addr_M, and address realm is 0 to M-1; Corresponding double port memory physical address Addr_RAM, address realm is 0 to M × L-1, for the data in the corresponding frame structure of addressing Addr_L;
(4) design read/write data frame detection criteria, determine that whether read/write enable signal is effective according to current read/write data intraframe data address; And then determine the frame address W_Addr_L of current write data and the frame address R_Addr_L of current sense data;
(5) two-level address mapping is carried out in intraframe data address, be converted to read/write physical address R_Addr_RAM and W_Addr_RAM of double port memory;
(6) quantity of the Frame still stored in statistics frame formatted data queue buffer memory, produces the sky/full Status Flag of frame format data queue buffer memory;
(7) judge whether to produce empty/full Status Flag, when frame format data queue buffer memory is in full state, external users no longer to frame format data queue buffering write data, otherwise can cause loss of data; When frame format data queue buffer memory is in dummy status, external users is no longer from frame format data queue buffer memory sense data; Otherwise the write physical address W_Addr_RAM according to the double port memory in step (5) writes frame data with reading physical address R_Addr_RAM, reads frame data to complete spacecraft frame format data queue buffer memory in double port memory.
Described two-level address mapping ruler is:
R_Addr_RAM＝R_Addr_L×M+R_Addr_M；
W_Addr_RAM＝W_Addr_L×M+W_Addr_M。
The present invention's advantage is compared with prior art:
(1) the present invention devises frame structure queue memory according to the thought of two-level address mapping and frame structure queue, based on RAM, the first in first out caching system that to utilize frame level address administration, frame queue thought and two-level address mapping mode to achieve with frame structure data be entirety.The principle of the invention is simple, logical resource expense is little, ease for use is strong, under factors causes when using traditional F IFO leakage data, Duo Shuoju, incomplete frame fault can be eliminated, and the fault pervasion that frame format displacement destroys.And the dirigibility of the buffer memory degree of depth, ease for use etc. are all far above the mode of traditional ping-pong buffer.Can realize kinds of frame data across the transmission of chip/striding equipment, for Spacecraft Electronic system provides a kind of caching system be simple and easy to by, highly reliable, flexible function, for satellite electron modularized design plays an important role.
(2) the intrinsic design characteristics of frame address administrative unit of the present invention can also provide following treatment mechanism:
Frame skips mechanism, if last time uses module to need to skip when last frame data during read data frame, directly read M-1 address once, making frame read address R_Addr_L increases by 1, reads end and points to next frame data, realize skipping of frame data.
Frame manifolding mechanism, do not complete (also not writing M-1 data) when writing frame data, due to the reasons such as error detection to abandon this frame time, this frame data remainder (comprising M-1 data) can not be write, now owing to not detecting that frame write mark is (when address W_Addr_M is M-1 in write Frame, and write enable signal is effective), W_Addr_L does not increase by 1, write frame address also rests on the storage space of present frame, now directly start the write of next frame data, automatically can cover the misdata of this frame.
Write frame interrupts, disappearance, super several automatism isolation mechanism: when fault causes data volume to exceed frame structure length, fault frame completes postamble write, because the present invention strictly uses the frame level addressing of complete frame structure, the data exceeded can not cause the data of next frame to offset.When fault frame does not complete postamble write, _ Addr_L does not increase by 1, and write frame level address also rests on the storage space of present frame, now writes the data that next frame data can cover fault frame, and fault is isolation for reading end.
Accompanying drawing explanation
Fig. 1 is design frame chart of the present invention.
Embodiment
A kind of highly reliable spacecraft frame format data queue caching system.Choose dual port RAM as physical data storage, this RAM possesses two ports, one for reading interface, another is for writing interface; Determine the parameter of RAM, suppose that M is every frame data length, L is frame queue capacity, and data width is n bit, and so the degree of depth of this dual port RAM should be M × L, and width is n bit; Carry out classification to data address, be two-stage altogether, the first order is frame level address Addr_L, and address realm is 0 to L-1, for the frame structure inside addressing frame queue storer; The second level is intraframe data address Addr_M, and address realm is 0 to M-1; Corresponding RAM physical address Addr_RAM, address realm is 0 to M × L-1; Design frame reads, writing address scaling unit, and realize two-level address and map, its rule is:
R_Addr_RAM＝R_Addr_L×M+R_Addr_M；
W_Addr_RAM＝W_Addr_L×M+W_Addr_M；
Design read/write frame detector, detects completing in a frame data write/read operation logic meaning; , still there is the quantity of Frame in statistics queue, produce the sky mark of frame queue, full scale will, Ji Hukong, almost full scale will in the frame level read/write address in design frame address administrative unit, management frames queue memory.
The present invention relates to a kind of spacecraft remote measuring and controlling data frame structure queue caching system, as shown in Figure 1, mainly comprise double port memory, frame writing address scaling unit, frame reading address scaling unit, frame address administrative unit, write frame detecting unit, read frame detecting unit totally 6 modules, implementation method is as follows:
1) double port memory (dual port RAM)
Double port memory is frame data actual storage body, has two FPDP, and one is read port, another is write port.Read port comprise input read clock, input read address R_Addr_RAM, input read enable, export read data.Write port comprises that clock is write in input, input write address W_Addr_RAM, input are write enable, input and write data.The capacity parameter of this double port memory is calculated according to the queue depth L, the frame sign M that need and data bit width n:
The double port memory degree of depth: L × M
Double port memory bit wide: n bit
2) frame detecting unit is write
Definition write Frame detection criteria is: when address W_Addr_M is M-1 in write Frame, and when write enable signal is effective, be judged to the write of a frame, if discontented, frame level write address adds 1.
Write frame detecting unit utilize comparer according to above detection criteria and build testing circuit with door, its logic is: when write data address W_Addr_M in frame and equal M-1 and write enable effective time, frame write operation detected, export a high level frame write-enable signal, otherwise the low level frame write-enable signal that output one is invalid.
3) frame detecting unit is read
Definition sense data frame detection criteria is: when in sense data frame, address R_Addr_M is M-1, and read enable signal effective time, be judged to the reading of a frame, if not empty, frame level is read address and is added 1.
Read frame detecting unit utilize comparer according to above detection criteria and build testing circuit with door, its logic is: when read data address R_Addr_M in frame equal M-1 and read enable effective time, frame read operation detected, export a high level frame and read enable signal, otherwise the low level frame reading enable signal that output one is invalid.
4) frame address administrative unit
Frame address administrative unit maintains 3 count values, and be respectively frame writing address, frame reads address, number of frames is held in queue, these three counters are all reset to full 0 when resetting.
Frame address administrative unit receives the detection signal read frame detecting unit and write frame detecting unit, and when frame write-enable signal is effective, and time discontented, number of frames increase by 1 is held in queue.
When frame reads enable signal effectively, and time not empty, number of frames minimizing 1 is held in queue.Time when frame write-enable signal and frame read enable signal while effectively, queue is held number of frames and is remained unchanged.
Queue holds number of frames for generation of the full signal of sky, when queue hold number of frames equal 0 time, spacing wave effectively (high level), when queue hold number of frames equal L time, full signal is effectively (high level).
Queue holds number of frames simultaneously for generation of almost empty, almost completely signal, when queue hold number of frames be less than the almost empty threshold value of setting time, almost spacing wave effectively (high level), when queue hold number of frames be greater than the full threshold value of a few setting time, almost completely signal is effectively (high level).The almost empty threshold value wherein set with almost completely threshold value can need to arrange according to user.
Frame writing address W_Addr_L records current write data should write for which frame address, and its generation rule is: when frame write-enable signal effectively and discontented time, frame writing address W_Addr_L increases by 1, and increasing spilling after counting down to L-1 is again 0, cycle count.
Frame reads address R_Addr_L and records current sense data and should read which frame address, and its generation rule is: when frame read enable signal effectively and not empty time, frame reads address R_Addr_L increases by 1, and increasing spilling after counting down to L-1 is again 0, cycle count.
Above mechanism can ensure that frame is read address R_Addr_L and surmounted frame write address W_Addr_L never.
In order to better adapt to the numerous situations occurred in data buffer storage process, frame address administrative unit relies on its intrinsic design characteristics can realize following several treatment mechanism:
Frame skips mechanism, if last time uses module to need to skip when last frame data during read data frame, directly read M-1 address once, making frame read address R_Addr_L increases by 1, reads end and points to next frame data, realize skipping of frame data.
Frame manifolding mechanism, do not complete (also not writing M-1 data) when writing frame data, due to the reasons such as error detection to abandon this frame time, this frame data remainder (comprising M-1 data) can not be write, now owing to not detecting that frame write mark is (when address W_Addr_M is M-1 in write Frame, and write enable signal is effective), W_Addr_L does not increase by 1, write frame address also rests on the storage space of present frame, now directly start the write of next frame data, automatically can cover the misdata of this frame.
Write frame interrupts, disappearance, super several automatism isolation mechanism: when fault causes data volume to exceed frame structure length, fault frame completes postamble write, because the present invention strictly uses the frame level addressing of complete frame structure, the data exceeded can not cause the data of next frame to offset.When fault frame does not complete postamble write, W_Addr_L does not increase by 1, and write frame level address also rests on the storage space of present frame, now writes the data that next frame data can cover fault frame, and fault is isolation for reading end.
5) frame writing address scaling unit
Data address of the present invention is divided into two-stage, and the first order is frame level address Addr_L, and address realm is 0 to L-1, for the frame structure inside addressing frame queue storer; The second level is intraframe data address Addr_M, and address realm is 0 to M-1; Corresponding RAM physical address Addr_RAM, address realm is 0 to M × L-1; Design frame write two-level address maps, and its rule is:
W_Addr_RAM＝W_Addr_L×M+W_Addr_M；
Frame writing address scaling unit produces the write physical address W_Addr_RAM of double port memory according to above formula, utilizes multiplier and totalizer to build this scaling unit.
6) frame reads address scaling unit
Data address of the present invention is divided into two-stage, and the first order is frame level address Addr_L, and address realm is 0 to L-1, for the frame structure inside addressing frame queue storer; The second level is intraframe data address Addr_M, and address realm is 0 to M-1; Corresponding RAM physical address Addr_RAM, address realm is 0 to M × L-1; Design frame reads two-level address and maps, and its rule is:
R_Addr_RAM＝R_Addr_L×M+R_Addr_M；
Frame reads address scaling unit produces double port memory reading physical address R_Addr_RAM according to above formula, utilizes multiplier and totalizer to build this scaling unit.
7) each module integration working mechanism
Above-mentioned six unit are integrated the spacecraft frame format data queue storer of the present invention's design according to Fig. 1 mode, this frame queue storer external interface is divided into write port, read port;
Write port comprises:
A) frame full scale will---in marker frames queue, Frame has been full;
B) frame almost full scale will---in marker frames queue, Frame has exceeded setting and has almost expired threshold value;
C) write address in frame---for write present frame frame in address;
D) write enable---enable for writing writing of present frame;
E) frame data are write---for inputting the data of write present frame.
The agreement writing frame data is: similar common synchronization RAM is the same, and utilize write address, write enable, write address 0 to M-1, enable write useful signal, writes corresponding frame data.When address is M-1, writing enable can only be that a clock period is long.
Read port comprises:
A) frame sky mark---in marker frames queue, Frame has been empty;
B) almost empty mark---in marker frames queue, Frame has been less than the almost empty threshold value of setting to frame;
C) read address in frame---for read present frame frame in address;
D) read enable---for read present frame read enable;
E) frame data are read---for exporting the data reading present frame.
The agreement reading frame data is: similar common synchronization RAM is the same, utilize and read address, read enable, read address 0 to M-1, enable read useful signal, read corresponding complete frame data.When address is M-1, reading enable can only be that a clock period is long.
8) fault tolerance
The present invention is except having traditional F IFO reservoir designs flexibly, except the feature that is simple and easy to, also have the advantage that ping-pong buffer reliability is high.In addition, there is more robustness, support more design requirements flexibly.Be specially:
A) support content modification write, cover write---when writing, the postamble (in frame, address W_Addr_M is M-1) that side controller is not also writing present frame is front, needing if any error correction, correction etc. can directly by ad-hoc location in address location to frame, enable write is enable, data after write amendment, write postamble again after completing the amendment of needs, indicate that present frame has write.
B) cover and write frame---when write side controller is before the postamble also not writing present frame, as due to check errors or choose the demands such as frame and need to abandon present frame, directly start to write next frame data when can not write the postamble of present frame.Because previous frame does not complete write, write frame level address also rests on the storage space of present frame, and the write of next frame data directly covers present frame, realizes the covering of present frame.
C) support that reading end frame skips---when reading side controller is before the postamble also not reading present frame, as due to check errors or choose the demands such as frame and need to abandon present frame, directly address can be jumped to postamble position (R_Addr_M=M-1) in frame, read once namely to can skip present frame, directly start to read next frame.
D) frame interrupt, imperfect---due to complex electromagnetic environment impact cause reading, the few read-write of write end, many read-writes or be engraved in the middle of frame sends when receiving chip powers on, when being engraved in during reset in the middle of frame, current frame data can be caused to make mistakes or super several, minority, under these failure conditions, the present invention can isolate the impact of these faults on subsequent frame by the inherent characteristic of whole frame reading and writing data.Be divided into two kinds of situations, when fault frame completes postamble write, so read end and only have current frame data to be subject to fault effects.When fault frame does not complete postamble write, so write the data that next frame data can cover fault frame, fault is invisible for reading end.
9) purposes
The present invention relates to a kind of highly reliable spacecraft frame format data queue caching system, this design is on double port memory basis, devise two-level address administrative mechanism, be respectively the management of frame level address and intraframe data level address administration, be mapped to the physical address of double port memory by secondary scale unit, devise data frame queue sky/full Mark Detection, frame address management circuit etc. simultaneously.Achieve the spacecraft frame format data queue caching system carrying out queue write, read operation in units of partial data frame structure of complete function.The principle of the invention is simple, powerful, resource overhead is little, robustness is high, application is strong, can eliminate many potential faults that data frame format does not line up, breakage is spread affecting satellite in orbit data exception and cause.The frame structure data interaction buffering higher to reliability requirement can be widely used in, the occasion such as mutual in CPU and FPGA, ASIC interface, multi-circuit combiner, demultiplexer, multiplexer, chip chamber Frame.
A kind of highly reliable spacecraft frame format data queue caching method of the present invention, step summary is as follows, and the implementation in concrete steps is unaccounted can with reference to the corresponding description in said system:
(1) choose double port memory as physical data storage, this RAM possesses two ports, one for reading interface, another is for writing interface;
(2) determine the parameter of double port memory, suppose that M is every frame data length, L is frame queue capacity, and data width is n bit, and so the degree of depth of this dual port RAM should be M × L, and width is n bit;
(3) carry out classification to data address, be altogether two-stage, the first order is frame level address Addr_L, and address realm is 0 to L-1, for the frame structure in inside addressing double port memory; The second level is intraframe data address Addr_M, and address realm is 0 to M-1; Corresponding double port memory physical address Addr_RAM, address realm is 0 to M × L-1, for the data in the corresponding frame structure of addressing Addr_L;
(4) design read/write data frame detection criteria, determine that whether read/write enable signal is effective according to current read/write data intraframe data address; And then determine the frame address W_Addr_L of current write data and the frame address R_Addr_L of current sense data;
(5) two-level address mapping is carried out in intraframe data address, be converted to read/write physical address R_Addr_RAM and W_Addr_RAM of double port memory;
(6) quantity of the Frame still stored in statistics frame formatted data queue buffer memory, produces the sky/full Status Flag of frame format data queue buffer memory;
(7) whether sky/full the Status Flag of frame format data queue buffer memory can carry out read-write operation to frame format data queue buffer memory for pointing out user of the present invention.
Judge whether to produce empty/full Status Flag, when frame format data queue buffer memory is in full state, external users no longer to frame format data queue buffering write data, otherwise can cause loss of data; When frame format data queue buffer memory is in dummy status, external users is no longer from frame format data queue buffer memory sense data; Otherwise the write physical address W_Addr_RAM according to the double port memory in step (5) writes frame data with reading physical address R_Addr_RAM, reads frame data to complete spacecraft frame format data queue buffer memory in double port memory.
The content be not described in detail in instructions of the present invention belongs to the known technology of those skilled in the art.
Claims (8)
1. a highly reliable spacecraft frame format data queue caching system, is characterized in that: comprise double port memory, frame writing address scaling unit, frame reading address scaling unit, frame address administrative unit, write frame detecting unit, read frame detecting unit;
Write frame detecting unit definition write Frame detection criteria, according to address W_Addr_M output detections signal in this criterion and write Frame and high level or low level frame write-enable signal to frame address administrative unit;
Read frame detecting unit definition sense data frame detection criteria, read enable signal to frame address administrative unit according to address R_Addr_M output detections signal in this criterion and sense data frame and high level or low level frame;
Frame address administrative unit receives the detection signal read frame detecting unit and write frame detecting unit, and the detection signal according to receiving determines the frame address W_Addr_L of current write data and the frame address R_Addr_L of current sense data;
Frame writing address scaling unit produces the write physical address W_Addr_RAM of double port memory according to the frame level address W_Addr_L of address W_Addr_M and current write data in write Frame;
Frame reads address scaling unit produces double port memory reading physical address R_Addr_RAM according to the frame level address R_Addr_L of address R_Addr_M and current sense data in sense data frame;
Double port memory, have a read port and a write port, memory depth is M × L, and bit wide is n bit; Write physical address W_Addr_RAM according to double port memory writes frame data with reading physical address R_Addr_RAM, reads frame data to complete spacecraft frame format data queue buffer memory in double port memory; Wherein M is every frame data length, and L is frame queue capacity, and data bit width is nbit;
Above-mentioned frame level address realm 0 ~ L-1; Address realm 0 ~ M-1 in frame.
2. a kind of highly reliable spacecraft frame format data queue caching system according to claim 1, is characterized in that: described frame address administrative unit determines that the rule of the frame address W_Addr_L of current write data and the frame address R_Addr_L of current sense data is:
When frame write-enable signal effectively and discontented time, frame writing address W_Addr_L increases by 1, and increasing spilling after counting down to L-1 is again 0, cycle count;
When frame read enable signal effectively and not empty time, frame read address R_Addr_L increase by 1, increasing spilling after counting down to L-1 is again 0, cycle count.
3. a kind of highly reliable spacecraft frame format data queue caching system according to claim 1, is characterized in that: described W_Addr_RAM=W_Addr_L × M+W_Addr_M.
4. a kind of highly reliable spacecraft frame format data queue caching system according to claim 1, is characterized in that: described R_Addr_RAM=R_Addr_L × M+R_Addr_M.
5. a kind of highly reliable spacecraft frame format data queue caching system according to claim 1, it is characterized in that: described write Frame detection criteria is: under the effective prerequisite of write enable signal of outside input, when in write Frame, address W_Addr_M is M-1, be judged to the write of a frame, otherwise frame level write address adds 1.
6. a kind of highly reliable spacecraft frame format data queue caching system according to claim 1, it is characterized in that: sense data frame detection criteria is: outside input read the effective prerequisite of enable signal under, when in sense data frame, address R_Addr_M is M-1, be judged to the reading of a frame, otherwise frame level is read address and is added 1.
7. a highly reliable spacecraft frame format data queue caching method, is characterized in that step is as follows:
(1) choose double port memory as physical data storage, this double port memory possesses two ports, one for reading interface, another is for writing interface;
(2) determine the parameter of double port memory, suppose that M is every frame data length, L is frame queue capacity, and data width is n bit, and so the degree of depth of this double port memory is M × L, and width is n bit;
(3) carry out classification to data address, be altogether two-stage, the first order is frame level address Addr_L, and address realm is 0 to L-1, for the frame structure in inside addressing double port memory; The second level is intraframe data address Addr_M, and address realm is 0 to M-1; Corresponding double port memory physical address Addr_RAM, address realm is 0 to M × L-1, for the data in the corresponding frame structure of addressing Addr_L;
(4) design read/write data frame detection criteria, determine that whether read/write enable signal is effective according to current read/write data intraframe data address; And then determine the frame address W_Addr_L of current write data and the frame address R_Addr_L of current sense data;
(5) two-level address mapping is carried out in intraframe data address, be converted to read/write physical address R_Addr_RAM and W_Addr_RAM of double port memory;
(6) quantity of the Frame still stored in statistics frame formatted data queue buffer memory, produces the sky/full Status Flag of frame format data queue buffer memory;
(7) judge whether to produce empty/full Status Flag, when frame format data queue buffer memory is in full state, external users no longer to frame format data queue buffering write data, otherwise can cause loss of data; When frame format data queue buffer memory is in dummy status, external users is no longer from frame format data queue buffer memory sense data; Otherwise the write physical address W_Addr_RAM according to the double port memory in step (5) writes frame data with reading physical address R_Addr_RAM, reads frame data to complete spacecraft frame format data queue buffer memory in double port memory.
8. a kind of highly reliable spacecraft frame format data queue caching method according to claim 7, is characterized in that: described two-level address mapping ruler is:
R_Addr_RAM＝R_Addr_L×M+R_Addr_M；
W_Addr_RAM＝W_Addr_L×M+W_Addr_M。
Priority Applications (1)
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| CN106776374B (en) * | 2017-01-23 | 2021-04-13 | 中核控制***工程有限公司 | Efficient data buffering method based on FPGA |
| CN108319557B (en) * | 2017-12-15 | 2022-02-08 | 天津津航计算技术研究所 | Data buffer with data retransmission function and read-write method thereof |
| CN109697767B (en) * | 2018-12-29 | 2021-11-19 | 华为技术有限公司 | Data processing method, related device and computer storage medium |
| CN114153758B (en) * | 2021-11-19 | 2022-12-20 | 中国电子科技集团公司第三十四研究所 | Cross-clock domain data processing method with frame counting function |
| CN115203075B (en) * | 2022-06-27 | 2024-01-19 | 威胜能源技术股份有限公司 | Distributed dynamic mapping cache design method |
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| CN101667451A (en) * | 2009-09-11 | 2010-03-10 | 西安电子科技大学 | Data buffer of high-speed data exchange interface and data buffer control method thereof |
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| CN101667451A (en) * | 2009-09-11 | 2010-03-10 | 西安电子科技大学 | Data buffer of high-speed data exchange interface and data buffer control method thereof |
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