CN102904686B - For building method and the code modulating method of code modulated QC-LDPC code - Google Patents

For building method and the code modulating method of code modulated QC-LDPC code Download PDF

Info

Publication number
CN102904686B
CN102904686B CN201210380776.1A CN201210380776A CN102904686B CN 102904686 B CN102904686 B CN 102904686B CN 201210380776 A CN201210380776 A CN 201210380776A CN 102904686 B CN102904686 B CN 102904686B
Authority
CN
China
Prior art keywords
code
prime
matrix
ldpc code
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210380776.1A
Other languages
Chinese (zh)
Other versions
CN102904686A (en
Inventor
彭克武
范力文
潘长勇
宋健
杨知行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Engineering Lab. For DTV (Beijing)
Tsinghua University
Original Assignee
NATIONAL ENGINEERING LAB FOR DTV (BEIJING)
Tsinghua University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NATIONAL ENGINEERING LAB FOR DTV (BEIJING), Tsinghua University filed Critical NATIONAL ENGINEERING LAB FOR DTV (BEIJING)
Priority to CN201210380776.1A priority Critical patent/CN102904686B/en
Publication of CN102904686A publication Critical patent/CN102904686A/en
Application granted granted Critical
Publication of CN102904686B publication Critical patent/CN102904686B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Error Detection And Correction (AREA)

Abstract

The invention discloses a kind of building method for code modulated QC-LDPC code, and a kind of code modulating method.Described building method comprises: the female code offset address matrix E building QC-LDPC code, and to set submatrix exponent number be b; Utilize the line splitting amalgamation property of single-place shift matrix, the basis of matrix E builds the offset address matrix of the QC-LDPC code of different code check; According to offset address matrix and the submatrix exponent number b of the QC-LDPC code of different code check, generate the QC-LDPC code of different code check.Described code modulating method adopts described building method to generate QC-LDPC code, thus encodes to information bit and modulate.The technical scheme that the present invention proposes, take full advantage of the good characteristic of row combine code and partial row combine code, under the prerequisite obtaining premium properties, effectively can improve the flexibility of code modulation system, extensibility and multi-service applicability, ensure that relatively low hardware implementing complexity simultaneously.

Description

For building method and the code modulating method of code modulated QC-LDPC code
Technical field
The present invention relates to digital channel coding techniques field, particularly a kind of building method for code modulated QC-LDPC code and a kind of code modulating method.
Background technology
Low-density checksum (Low Density Parity Check, LDPC) code is that the class that proposed in 1962 by RobertG.Gallager is based on the Special Linear block code of sparse check matrix.It is described by check matrix H usually, the change kernel of H and the code word space of LDPC code, and it is openness that its main feature is that H has.LDPC code not only has the superperformance of approaching shannon limit, and decoding complexity is lower, handling capacity is high, flexible structure, be the study hotspot of field of channel coding in recent years, be widely used in the fields such as deep space communication, optical fiber communication, ground and digital multimedia broadcast (dmb) via satellite at present.LDPC code becomes the strong competitor of forth generation mobile radio system and new-generation digital television broadcast transmissions system channel coding scheme, and based on LDPC code channel coding schemes adopt by multiple Communication and Broadcast standard, as IEEE802.16e, IEEE802.3an, DVB-T2 and DVB-S2, and digital TV ground multimedia broadcast transmission standard (DTMB) etc.
LDPC(N, K) code has the check matrix H=[h of N-K capable N row mn] (N-K) × N, wherein, N is code word size (abbreviation code length), and K is information bit length, M=(N-K) be generally called check digit length, corresponding code check R=K/N.H matrix is made up of element 0 or 1, and its every a line represents a check equations, in Tanner figure, be called check-node, N-K altogether; Each row represents an information bit, in Tanner figure, be called variable node, N number of altogether; Nonzero element in H matrix represents the annexation between its check-node of being expert at and the variable node of column, in Tanner figure, be called limit. represent the set being connected to whole variable nodes of check-node m, namely represent the set being connected to the complete verification node of variable node n, namely
Accurate circulation (Quasi-Cyclic, QC) LDPC code is an important subclass of LDPC code, its check matrix and generator matrix all have accurate circulation form, see the definition of people in document " Quasi-cyclic low-density parity-check codes from circulant permutation matrices " such as Marc P.C.Fossorier.The check matrix of QC-LDPC code is by M c× N cindividual sub-matrix composition, wherein, M c=(N-K)/b, N c=N/b, b are the exponent numbers of submatrix.QC-LDPC code check matrix structure is as follows:
Wherein, A i, jbe the square formation of b × b, 1≤i≤M, 1≤j≤N, b is called submatrix exponent number, these square formations or single-place shift matrix, or full null matrix.Wherein, the feature of shift matrix is, its each provisional capital is the ring shift right position of its lastrow, and the first row is the ring shift right position of last column.Single-place shift matrix is a kind of shift matrix, and being shifted by unit matrix obtains, and only has a nonzero element in its a row or column.For single-place shift matrix A i, j, define its shift index e i, jif, e i, j=a, 1≤a≤b, then represent A i,jthe a of the 1st row is classified as 1, and all the other are classified as 0, and all the other each row are all ring shift rights one of lastrow; If e i, j=0, then represent A i, jit is full null matrix.
Such as, e i, j=a=4, b=5, then represent A i, jthe 4th of 1st row is classified as 1, and all the other are classified as 0, and all the other each row are all ring shift rights one of lastrow, and its structure is as follows:
A i , j = 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0
The offset address matrix E of definition QC-LDPC code is M crow N ccolumn matrix, it is expressed as follows:
E = [ e i , j ] M C × N C
From above-mentioned explanation, after b determines, namely E matrix can be used as the reduced representation form of H matrix; Now, E matrix is uniquely corresponding with H matrix, and H matrix is undertaken obtaining after accurate circulation submatrix is expanded by E matrix.
The channel coding schemes of compatible various code rate (abbreviation multi code Rate of Chinese character) has very strong using value in the real system such as digital broadcasting and mobile communication.The channel coding schemes of compatible multiple code length (being called for short many code lengths) is mainly derived from the demand that transmission system supports multiple business pattern.Long code is generally applied to broadcast and satellite communication; And the business General Requirements such as mobile communication, power line communication (Power Line Communication, PLC) adopts short code.Consultative committee for space data system (The Consultative Committee for Space Data Systems, CCSDS) for the Turbo code of the LDPC code of deep space communication, the LDPC code of DVB-T2 and LTE V8.1 motion, be all the channel coding schemes adopting many code lengths multi code Rate of Chinese character.
The structure of traditional multi code Rate of Chinese character (or many code lengths) LDPC code, is construct different H matrixes respectively according to the requirement of different code check (or code length) mostly, then carries out respectively encoding or decode operation.H matrix due to each code check (or code length) is relatively independent or difference is comparatively large, when the coding that hardware implementing multi code Rate of Chinese character (or many code lengths) is unified and decode system, is often difficult to carry out effective global optimization, makes hardware implementing complexity higher.
Row combine code is by the people such as Andres I.Vila Casado definition in document " Multiple-Rate Low-Density Parity-Check Codes with Constant Block-length ".Partial row combine code has expanded traditional row combine code, and it is by the people such as Zhichu Lin definition in document " ANew Design Method of Multi-Rate Quasi-Cyclic LDPC Codes ".For row combine code and partial row combine code, the decoder function module of different code check can be multiplexing after simple combination, the decoder of composition multi code Rate of Chinese character unification.So, based on the multi code Rate of Chinese character LDPC code scheme of row combine code and partial row combine code, relatively low hardware implementing complexity can be ensured under the prerequisite obtaining premium properties simultaneously.For convenience of description, first make an explanation to give a definition:
1, can merge: check-node i, j can merge, refer in Tanner figure and do not have variable node to be connected to check-node i and check-node j simultaneously, be also otherwise, then can not merge.
2, row merges: check-node i, j merge, and refer to i, j meets can merge condition, and verifies node i in Tanner figure, and j merges into a new node k, whole variable nodes that whole variable node that origin node i connects is connected with origin node j, are all connected to this new node k.Also namely,
Similarly, L check-node i 1, i 2..., i lcan merge, row merge definition, can be obtained by above-mentioned definition recursion.
3, line splitting: check-node k is split into two nodes, refers to check-node k in Tanner figure and is split into two new check-node k 1and k 2, whole variable nodes that origin node k connects are divided into two parts, a part and new node k 1connect, another part and new node k 2connect.Also namely, line splitting and row merge inverse process each other.Line splitting has certain flexibility, because the limit of origin node k, can select neatly and new node k after cleaving 1connect, or with new node k 2connect.
4, partial row merges: check-node k partial row is incorporated into check-node i, j, and referring to check-node k line splitting is two new node k 1and k 2, wherein k 1merge with check-node i is capable, k 2merge with check-node j is capable, and they all meet and can merge condition.
Similarly, check-node k partial row is incorporated into i 1, i 2..., i lthe definition of node, can be obtained by above-mentioned definition recursion.
From the above, row merges and defines the method that matrix multiple row merges into a line, and line splitting defines the method that matrix a line is decomposed into multirow, and partial row merges and is then defined as matrix a line and is split into multirow, then carries out with multirow the method that merges.
For stating conveniently, row merging, line splitting and partial row merge, and are referred to as row and merge division or line splitting merging.
If multi code Rate of Chinese character many code lengths QC-LDPC code can be built based on same female code check matrix, just the good characteristic of row combine code and partial row combine code can be made full use of, under the prerequisite obtaining premium properties, effectively can improve the flexibility of code modulation system, extensibility and multi-service applicability, ensure relatively low hardware implementing complexity simultaneously.
Summary of the invention
(1) technical problem to be solved
The object of the present invention is to provide a kind of building method for code modulated QC-LDPC code and a kind of code modulating method, be difficult to carry out effective integrated optimization, problem that hardware implementing complexity is high with the construction process solving multi code Rate of Chinese character many code lengths LDPC code in prior art.
(2) technical scheme
In order to solve the problems of the technologies described above, the present invention proposes a kind of building method for code modulated QC-LDPC code, described building method comprises the following steps:
S101, build female code offset address matrix E of QC-LDPC code, and to set submatrix exponent number be b, wherein,
Described matrix E is the matrix of the capable 12M row of 12M, and M is positive integer, the shift index e of described matrix E i, jmeet 0≤e i, j≤ b;
S102, described matrix E adds water index obtain matrix E ', the shift index e ' of described matrix E ' i, jmeet 0≤e ' i, j≤ b,
Described matrix E ' adds water index and obtains matrix E ", described matrix E " shift index e " i, jmeet 0≤e " i, j≤ b,
Described matrix E " above add water index obtain matrix E " ', described matrix E " ' shift index e " ' i, jmeet 0≤e " ' i, j≤ b;
S103, calculating code check are the offset address matrix E of the QC-LDPC code of 1/2 (1/2), wherein, described matrix E (1/2)shift index computing formula be: e i , j ( 1 / 2 ) = e i , j + e i + 6 M , j , 1≤i≤6M,1≤j≤12M;
S104, calculating code check are the offset address matrix E of the QC-LDPC code of 2/3 (2/3), wherein, described matrix E (2/3)shift index computing formula be:
e i , j ( 2 / 3 ) = e i , j ′ + e i + 4 M , j ′ + e i + 8 M , j , ′ ′ 1≤i≤4M,1≤j≤12M;
S105, calculating code check are the offset address matrix E of the QC-LDPC code of 3/4 (3/4), wherein, described matrix E (3/4)shift index computing formula be:
e i , j ( 3 / 4 ) = e i , j ′ ′ + e i + 3 M , j ′ ′ + e i + 6 M , j ′ ′ + e i + 9 M , j , ′ ′ 1≤i≤3M,1≤j≤12M;
S106, calculating code check are the offset address matrix E of the QC-LDPC code of 5/6 (5/6), wherein, described matrix E (5/6)shift index computing formula be:
e i , j ( 5 / 6 ) = e i , j ′ ′ ′ + e i + 2 M , j ′ ′ ′ + e i + 4 M , j ′ ′ ′ + e i + 6 M , j ′ ′ ′ + e i + 8 M , j ′ ′ ′ + e i + 10 M , j ′ ′ ′ ,
1≤i≤2M,1≤j≤12M;
S107, according to described matrix E (1/2)with described submatrix exponent number b, generate the QC-LDPC code that code check is 1/2, code length is 12M*b,
According to described matrix E (2/3)with described submatrix exponent number b, generate the QC-LDPC code that code check is 2/3, code length is 12M*b,
According to described matrix E (3/4)with described submatrix exponent number b, generate the QC-LDPC code that code check is 3/4, code length is 12M*b,
According to described matrix E (5/6)with described submatrix exponent number b, generate the QC-LDPC code that code check is 5/6, code length is 12M*b.
Optionally, step is comprised further after step S107:
S108, the numerical value of described submatrix exponent number b is revised as b ', wherein, described submatrix exponent number b ' meets
b′≥e i,j,e′ i,j,e″ i,j,e″′ i,j e i , j ( 1 / 2 ) , e i , j ( 2 / 3 ) , e i , j ( 3 / 4 ) , e i , j ( 5 / 6 ) ;
S109, according to described matrix E (1/2)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 1/2, code length is 12M*b ',
According to described matrix E (2/3)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 2/3, code length is 12M*b ',
According to described matrix E (3/4)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 3/4, code length is 12M*b ',
According to described matrix E (5/6)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 5/6, code length is 12M*b '.
Based on the building method of above-mentioned QC-LDPC code, the present invention proposes a kind of code modulating method simultaneously, and described code modulating method comprises the following steps:
S201, the described building method for code modulated QC-LDPC code of employing, obtain QC-LDPC code;
S202, utilize described QC-LDPC code, information bit waiting for transmission is encoded, obtains coded-bit;
S203, bit mapping is carried out to described coded-bit, obtain constellation bit vectors;
S204, constellation mapping is carried out to described constellation bit vectors, obtain constellation symbol;
S205, described constellation symbol is sent to subsequent processing units.
Optionally, the code length of described QC-LDPC code is 61440 or 15360.
Optionally, step S203 specifically comprises:
S203-1, Bit Interleave is carried out to described coded-bit, obtain interleaving bits;
S203-2, bit permutation is carried out to described interleaving bits, obtains the bit vectors after replacing, and the bit vectors after described displacement is split, obtain described constellation bit vectors,
Wherein, described bit permutation refers to and all bits be mapped in one or more constellation symbol is carried out order adjustment.
Optionally, step S204 specifically comprises:
The APSK constellation of described constellation bit vectors being carried out to M point maps or qam constellation mapping, obtains described constellation symbol,
Wherein, the value of described M is 4,16,64 or 256.
Optionally, step S205 comprises further:
Described constellation symbol is carried out coordinate intertexture and symbol interleaving, then sends to described subsequent processing units.
(3) beneficial effect
The technical scheme tool that the present invention proposes has the following advantages: construct multi code Rate of Chinese character many code lengths QC-LDPC code based on same female code offset address matrix (female code check matrix), take full advantage of the good characteristic of row combine code and partial row combine code, under the prerequisite obtaining premium properties, effectively can improve the flexibility of code modulation system, extensibility and multi-service applicability, ensure that relatively low hardware implementing complexity simultaneously.
In addition, the LDPC code that the technical scheme that the present invention proposes forms for common LDPC code or non-unity shift matrix is also suitable for.
Accompanying drawing explanation
Fig. 1 is the implementation procedure schematic diagram of the building method for code modulated QC-LDPC code that the present invention proposes.
Fig. 2 is the implementation procedure schematic diagram of the code modulating method that the present invention proposes.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.
For a kind of single-place shift matrix A of QC-LDPC code i, j, define its shift index e i, jif, e i, j=a, 1≤a≤b, b is parameter submatrix exponent number, then represent A i, jthe a of the 1st row is classified as 1, and all the other are classified as 0, and all the other each row are all ring shift rights one of lastrow; If e i, j=0, then represent A i, jit is full null matrix.
Such as, e i, j=a=4, b=5, then represent A i, jthe 4th of 1st row is classified as 1, and all the other are classified as 0, and all the other each row are all ring shift rights one of lastrow, and its structure is as follows:
A i , j = 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0
Based on the character of single-place shift matrix, for making full use of the characteristic of row combine code and department's row combine code, the present invention proposes a kind of building method for code modulated QC-LDPC code.
As shown in Figure 1, described building method comprises the following steps:
S101, build female code offset address matrix E of QC-LDPC code, and to set submatrix exponent number be b, wherein,
Described matrix E is the matrix of the capable 12M row of 12M, and M is positive integer, the shift index e of described matrix E i, jmeet 0≤e i, j≤ b;
S102, described matrix E adds water index obtain matrix E ', the shift index e ' of described matrix E ' i, jmeet 0≤e ' i, j≤ b,
Described matrix E ' adds water index and obtains matrix E ", described matrix E " shift index e " i, jmeet 0≤e " i, j≤ b,
Described matrix E " above add water index obtain matrix E " ', described matrix E " ' shift index e " ' i, jmeet 0≤e " ' i, j≤ b;
S103, calculating code check are the offset address matrix E of the QC-LDPC code of 1/2 (1/2), wherein, described matrix E (1/2)shift index computing formula be:
e i , j ( 1 / 2 ) = e i , j + e i + 6 M , j , 1≤i≤6M,1≤j≤12M;
S104, calculating code check are the offset address matrix E of the QC-LDPC code of 2/3 (2/3), wherein, described matrix E (2/3)shift index computing formula be:
e i , j ( 2 / 3 ) = e i , j ′ + e i + 4 M , j ′ + e i + 8 M , j ′ , 1≤i≤4M,1≤j≤12M;
S105, calculating code check are the offset address matrix E of the QC-LDPC code of 3/4 (3/4), wherein, described matrix E (3/4)shift index computing formula be:
e i , j ( 3 / 4 ) = e i , j ′ ′ + e i + 3 M , j ′ ′ + e i + 6 M , j ′ ′ + e i + 9 M , j , ′ ′ 1≤i≤3M,1≤j≤12M;
S106, calculating code check are the offset address matrix E of the QC-LDPC code of 5/6 (5/6), wherein, described matrix E (5/6)shift index computing formula be:
e i , j ( 5 / 6 ) = e i , j ′ ′ ′ + e i + 2 M , j ′ ′ ′ + e i + 4 M , j ′ ′ ′ + e i + 6 M , j ′ ′ ′ + e i + 8 M , j ′ ′ ′ + e i + 10 M , j ′ ′ ′ ,
1≤i≤2M,1≤j≤12M;
S107, according to described matrix E (1/2)with described submatrix exponent number b, generate the QC-LDPC code that code check is 1/2, code length is 12M*b,
According to described matrix E (2/3)with described submatrix exponent number b, generate the QC-LDPC code that code check is 2/3, code length is 12M*b,
According to described matrix E (3/4)with described submatrix exponent number b, generate the QC-LDPC code that code check is 3/4, code length is 12M*b,
According to described matrix E (5/6)with described submatrix exponent number b, generate the QC-LDPC code that code check is 5/6, code length is 12M*b.
Optionally, step is comprised further after step S107:
S108, the numerical value of described submatrix exponent number b is revised as b ', wherein, described submatrix exponent number b ' meets
b′≥e i,j,e′ i,j,e″ i,j,e″′ i,j e i , j ( 1 / 2 ) , e i , j ( 2 / 3 ) , e i , j ( 3 / 4 ) , e i , j ( 5 / 6 ) ;
S109, according to described matrix E (1/2)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 1/2, code length is 12M*b ',
According to described matrix E (2/3)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 2/3, code length is 12M*b ',
According to described matrix E (3/4)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 3/4, code length is 12M*b ',
According to described matrix E (5/6)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 5/6, code length is 12M*b '.
Utilize above-mentioned building method, a kind of multi code Rate of Chinese character QC-LDPC code can be obtained, comprise the FEC forward error correction coding of 4 kinds of code checks:
1, code check is (12M*b, 6M*b) code of 1/2, and offset address matrix is designated as:
E ( 1 / 2 ) = [ e i , j ( 1 / 2 ) ] 6 M × 12 M ;
2, code check is (12M*b, 8M*b) code of 2/3, and offset address matrix is designated as:
E ( 2 / 3 ) = [ e i , j ( 2 / 3 ) ] 4 M × 12 M ;
3, code check is (12M*b, 9M*b) code of 3/4, and offset address matrix is designated as:
E ( 3 / 4 ) = [ e i , j ( 3 / 4 ) ] 3 M × 12 M ;
4, code check is (12M*b, 10M*b) code of 5/6, and offset address matrix is designated as:
E ( 5 / 6 ) = [ e i , j ( 5 / 6 ) ] 2 M × 12 M ;
Wherein, M is positive integer, and b is submatrix exponent number, and different code check shift index is all more than or equal to 0 and is less than or equal to b.
The offset address matrix construction step of above-mentioned different code check QC-LDPC code is as follows:
S101, the capable 12M column matrix of note 12M:
E=[e i,j] 12M×12M
S102, the capable 12M column matrix of note 12M:
E′=[e′ i,j] 12M×12M
E″=[e″ i,j] 12M×12M
E″′=[e" i,j] 12M×12M
Wherein, E ' obtains by E basis being added water index, E " obtain by E ' basis being added water index, on E " ' by E " basis, interpolation water index obtains,
And e i, j, e ' i, j, e " i, j, e " ' i, jall be more than or equal to 0, be less than or equal to b;
S103, code check are (12M*b, 6M*b) code of 1/2, and its 6M capable 12M line skew address matrix is designated as:
E ( 1 / 2 ) = [ e i , j ( 1 / 2 ) ] 6 M × 12 M ,
E (1/2)calculated by E=[ei, j] 12M × 12M, wherein,
e i , j ( 1 / 2 ) = e i , j + e i + 6 M , j , 1≤i≤6M,1≤j≤12M;
S 104, code check are (12M*b, 8M*b) code of 2/3, and its 4M capable 12M line skew address matrix is designated as:
E ( 2 / 3 ) = [ e i , j ( 2 / 3 ) ] 4 M × 12 M ,
E (2/3)by E '=[e ' i, j] 12M × 12Mcalculate, wherein,
e i , j ( 2 / 3 ) = e i , j ′ + e i + 4 M , j ′ + e i + 8 M , j ′ , 1≤i≤4M,1≤j≤12M,
That is, (12M*b, 6M*b) code with the pass of (12M*b, 8M*b) code is, the new water index added of removing, the i-th, i+2M, i+4M of E (1/2) passes through after space split degree, obtains E (2/3)the i-th, i+2M capable, 1≤i≤2M;
S105, code check are (12M*b, 9M*b) code of 3/4, and its 3M capable 12M line skew address matrix is designated as:
E ( 3 / 4 ) = [ e i , j ( 3 / 4 ) ] 3 M × 12 M ,
E (3/4) by E "=[e " i, j] 12M × 12Mcalculate, wherein,
e i , j ( 3 / 4 ) = e i , j ′ ′ + e i + 3 M , j ′ ′ + e i + 6 M , j ′ ′ + e i + 9 M , j ′ ′ , 1≤i≤3M,1≤j≤12M,
That is, the pass of (12M*b, 6M*b) code of 1/2 code check and (12M*b, 9M*b) code of 3/4 code check is, the new water index added of removing, E (1/2)the i-th, i+3M pass through space merge after, obtain E (3/4)the i-th row, 1≤i≤3M;
S106, code check are (12M*b, 10M*b) code of 5/6, and its 2M capable 12M line skew address matrix is designated as:
E ( 5 / 6 ) = [ e i , j ( 5 / 6 ) ] 2 M × 12 m ,
E (5/6)by E " '=[e " ' i, j] 12M × 12Mcalculate, wherein,
e i , j ( 5 / 6 ) = e i , j ′ ′ ′ + e i + 2 M , j ′ ′ ′ + e i + 4 M , j ′ ′ ′ + e i + 6 M , j ′ ′ ′ + e i + 8 M , j ′ ′ ′ + e i + 10 M , j ′ ′ ′ , 1≤i≤2M,1≤j≤12M,
That is, the pass of (12M*b, 8M*b) code of 2/3 code check and (12M*b, 10M*b) code of 5/6 code check is, the new water index added of removing, E (2/3)the i-th, i+2M pass through space merge after, obtain E (5/6)the i-th row, 1≤i≤2M;
S107, offset address matrix E by 4 kinds of code checks (1/2), E (2/3), E (3/4), E (5/6)with submatrix exponent number b, obtain the QC-LDPC code that these 4 kinds of code check code lengths are 12M*b.
In order to expand the range of application of above-mentioned QC-LDPC code, making full use of the quasi-cyclic of check matrix, under identical offset address conditioned matrix, by changing submatrix exponent number b to realize many code lengths scheme, other multiple business can be applicable to.For this reason, the building method of the present invention's proposition is further comprising the steps:
S108, submatrix exponent number is revised as b ', wherein, b ' must be more than or equal to different code check shift index;
S 109, offset address matrix E by above-mentioned 4 kinds of code checks (1/2), E (2/3), E (3/4), E (5/6)with new submatrix exponent number b ', obtain the QC-LDPC code that these new 4 kinds of code check code lengths are 12M*b '.
Repeat step S108 and S109, can obtain the QC-LDPC code character of 4 kinds of multiple code lengths of code-rate-compatible, wherein, the offset address matrix of above-mentioned multiple code length QC-LDPC code is E (1/2), E (2/3), E (3/4), E (5/6), the offset address matrix of above-mentioned 4 kinds of code checks can compatible multiple code length.
More about the decoding algorithm of LDPC at present, Application comparison is the belief propagation algorithm (Belief Propagation Algorithm, BP) based on log-likelihood ratio (Logarithm Likelihood Ratio, LLR) Soft Inform ation widely.BP algorithm forms primarily of two decoding calculation step alternating iteration, i.e. operation of horizontal (Horizontal Process, HP) and vertical computing (Vertical Process, VP).Operation of horizontal by HPU(Horizontal Process Unit, horizontal arithmetic unit) perform, vertical computing by VPU(Vertical Process Unit, vertical arithmetic element) perform.For the multi code Rate of Chinese character QC-LDPC code that the present invention constructs, the HPU of different code check decoder can be multiplexing after simple combination, forms multi code Rate of Chinese character unification HPU; The VPU of different code check decoder can be completely multiplexing, forms multi code Rate of Chinese character unification VPU.Unify HPU/VPU by multi code Rate of Chinese character and can form the decoder obtaining multi code Rate of Chinese character and unify.So, based on the multi code Rate of Chinese character QC-LDPC code structural scheme that the present invention proposes, relatively low hardware implementing complexity can be ensured under the prerequisite obtaining premium properties simultaneously.
Below by specific embodiment, detailed explanation is carried out to the building method of the QC-LDPC code that the present invention proposes.
Embodiment 1:
Multi code Rate of Chinese character many code lengths QC-LDPC code that the present embodiment constructs, comprises the FEC forward error correction coding of 4 kinds of code checks, 2 kinds of code lengths:
1, code check is 1/2-b128 code (15360,7680) and the 1/2-b512 code (61440,30720) of 1/2, and these two codes have identical offset address matrix, are designated as:
E ( 1 / 2 ) = [ e i , j ( 1 / 2 ) ] 60 × 120 ,
Difference is the former parameter b=128, the latter parameter b=512;
2, code check is 2/3-b128 code (15360,10240) and the 2/3-b512 code (61440,40960) of 2/3, and these two codes have identical offset address matrix, are designated as:
E ( 2 / 3 ) = [ e i , j ( 2 / 3 ) ] 40 × 120 ,
Difference is the former parameter b=128, the latter parameter b=512;
3, code check is 3/4-b128 code (15360,11520) and the 3/4-b512 code (61440,46080) of 3/4, and these two codes have identical offset address matrix, are designated as:
E ( 3 / 4 ) = [ e i , j ( 3 / 4 ) ] 30 × 120 ,
Difference is the former parameter b=128, the latter parameter b=512;
4, code check is 5/6-b128 code (15360,12800) and the 5/6-b512 code (61440,51200) of 5/6, and these two codes have identical offset address matrix, are designated as:
E ( 5 / 6 ) = [ e i , j ( 5 / 6 ) ] 20 × 120 ,
Difference is the former parameter b=128, the latter parameter b=512.
The parameter of above-mentioned multi code Rate of Chinese character many code lengths QC-LDPC code is as shown in table 1:
The multiple code length QC-LDPC code parameters of table 1 various code rate
The construction step of the offset address matrix of 4 kinds of code checks, 2 kinds of code length QC-LDPC codes in the present embodiment is described below:
S101, note matrix E=[e i, j] 120 × 120be 120 row 120 column matrix, the shift index of matrix E is provided by annex;
S102, note matrix E '=[e ' i, j] 120 × 120be 120 row 120 column matrix, wherein:
e i , j ′ = 17 , ( i , j ) = ( 104,71 ) 38 , ( i , j ) = ( 113,72 ) 95 , ( i , j ) = ( 80,73 ) 11 , ( i , j ) = ( 117,74 ) 102 , ( i , j ) = ( 111,75 ) 85 , ( i , j ) = ( 5,76 ) 120 , ( i , j ) = ( 99,77 ) 84 , ( i , j ) = ( 61,78 ) , 119 , ( i , j ) = ( 118,79 ) 127 , ( i , j ) = ( 68,80 ) 73 , ( i , j ) = ( 76,81 ) 69 , ( i , j ) = ( 17,82 ) 72 , ( i , j ) = ( 7,83 ) 32 , ( i , j ) = ( 75,84 ) e i , j , else 1 ≤ i ≤ 120,1 ≤ j ≤ 120 ,
Note matrix E "=[e " i, j] 120 × 120be 120 row 120 column matrix, wherein:
e i , j ′ ′ = 122 , ( i , j ) = ( 23,85 ) 64 , ( i , j ) = ( 33,86 ) 55 , ( i , j ) = ( 37,87 ) 26 , ( i , j ) = ( 33,88 ) 114 , ( i , j ) = ( 11,89 ) , 92 , ( i , j ) = ( 15,90 ) 117 , ( i , j ) = ( 19,91 ) 14 , ( i , j ) = ( 42,92 ) e i , j ′ , else 1 ≤ i ≤ 120,1 ≤ j ≤ 120 ,
Note matrix E " '=[e " ' i, j] 120 × 120be 120 row 120 column matrix, wherein:
e i , j ′ ′ ′ = 59 , ( i , j ) = ( 54,93 ) 107 , ( i , j ) = ( 32,94 ) 45 , ( i , j ) = ( 39,95 ) 110 , ( i , j ) = ( 9,96 ) 19 , ( i , j ) = ( 6,97 ) 41 , ( i , j ) = ( 50,98 ) 45 , ( i , j ) = ( 47,99 ) 52 , ( i , j ) = ( 52,100 ) 96 , ( i , j ) = ( 43,101 ) 55 , ( i , j ) = ( 50,102 ) 109 , ( i , j ) = ( 16,103 ) e i , j ′ ′ ,else , 1 ≤ i ≤ 120,1 ≤ j ≤ 120 ;
S103, code check are 1/2-b128 code (15360,7680) and the 1/2-b512 code (61440,30720) of 1/2, and their offset address matrix is designated as:
E ( 1 / 2 ) = [ e I , j ( 1 / 2 ) ] 60 × 120 ,
E ( 1/2)be 60 row 120 column matrix, wherein,
e i , j ( 1 / 2 ) = e i , j + e i + 60 , j , 1≤i≤60,1≤j≤120;
S104, code check are 2/3-b128 code (15360,10240) and the 2/3-b512 code (61440,40960) of 2/3, and their offset address matrix is designated as:
E ( 2 / 3 ) = [ e i , j ( 2 / 3 ) ] 40 × 120 ,
E (2/3)be 40 row 120 column matrix, wherein,
e i , j ( 2 / 3 ) = e i , j ′ + e i + 40 , j ′ + e i + 80 , j ′ , 1≤i≤40,1≤j≤120;
S105, code check are 3/4-b128 code (15360,11520) and the 3/4-b512 code (61440,46080) of 3/4, and their offset address matrix is designated as:
E ( 3 / 4 ) = [ e i , j ( 3 / 4 ) ] 30 × 120 ,
E (3/4)be 30 row 120 column matrix, wherein,
e i , j ( 3 / 4 ) = e i , j ′ ′ + e i + 30 , j ′ ′ + e i + 60 . j ′ ′ + e i + 90 , j ′ ′ , 1≤i≤30,1≤j≤120;
S106, code check are 5/6-b128 code (15360,12800) and the 5/6-b512 code (61440,51200) of 5/6, and their offset address matrix is designated as:
E ( 5 / 6 ) = [ e i , j ( 5 / 6 ) ] 20 × 120 ,
E (5/6)be 20 row 120 column matrix, wherein,
e i , j ( 5 / 6 ) = e i , j ′ ′ ′ + e i + 20 , j ′ ′ ′ + e i + 40 , j ′ ′ ′ + e i + 60 , j ′ ′ ′ + e i + 80 , j ′ ′ ′ + e i + 100 , j ′ ′ ′ , 1≤i≤20,1≤j≤120。
Embodiment 2:
The present embodiment slightly makes improvements the shift index of b=128 short code in embodiment 1:
S1, in embodiment 1, obtain 4 kinds of code checks offset address matrix be:
Code check is 1/2 E ( 1 / 2 ) = [ e i , j ( 1 / 2 ) ] 60 × 120 ,
Code check is the E of 2/3 = ( 2 / 3 ) [ e i , j ( 2 / 3 ) ] 40 × 120 ,
Code check is 3/4 E ( 3 / 4 ) = [ e i , j ( 3 / 4 ) ] 30 × 120 ,
Code check is 5/6 E ( 5 / 6 ) = [ e i , j ( 5 / 6 ) ] 20 × 120 ;
S2, note improve after code check be 1/2 1/2-b128 code (15360,7680) offset address matrix be:
E · ( 1 / 2 ) = [ e · i , j ( 1 / 2 ) ] 60 × 120 , Wherein,
e · i , j ( 1 / 2 ) = 0 , ( i , j ) = ( 2,47 ) e i , j ( 1 / 2 ) , else , 1 ≤ i ≤ 60,1 ≤ j ≤ 120 ;
S3, note improve after code check be 2/3 2/3-b128 code (15360,10240) offset address matrix be:
E · ( 2 / 3 ) = [ e · i , j ( 2 / 3 ) ] 40 × 120 , Wherein,
e · i , j ( 2 / 3 ) = 0 , ( i , j ) = ( 24,13 ) e i , j ( 2 / 3 ) , else , 1 ≤ i ≤ 40,1 ≤ j ≤ 120 ;
S4, note improve after code check be 3/4 3/4-b128 code (15360,11520) offset address matrix be:
E · ( 3 / 4 ) = [ e · i , j ( 3 / 4 ) ] 30 × 120 , Wherein,
e · i , j ( 3 / 4 ) = 0 , ( i , j ) = ( 23,57 ) e i , j ( 3 / 4 ) , else , 1 ≤ i ≤ 30,1 ≤ j ≤ 120 ;
S5, note improve after code check be 5/6 5/6-b128 code (15360,12800) offset address matrix be:
E · ( 5 / 6 ) = [ e · i , j ( 5 / 6 ) ] 20 × 120 , Wherein,
e · i , j ( 5 / 6 ) = 0 , ( i , j ) = ( 13 , 2 ) e i , j ( 5 / 6 ) , else , 1 ≤ i ≤ 20,1 ≤ j ≤ 120 .
The feature of a kind of many code lengths QC-LDPC code that the present embodiment constructs is, on the basis of long code QC-LDPC code offset address matrix, is obtained the QC-LDPC code offset address matrix of short code by amendment parton matrix.Wherein the amendment of parton matrix is specially: one or more cyclic determinant submatrix is revised as complete zero submatrix, or one or more complete zero submatrix is revised as cyclic determinant submatrix.
Based on the described building method for code modulated QC-LDPC code, the present invention proposes a kind of code modulating method simultaneously, and as shown in Figure 2, described code modulating method comprises the following steps:
S201, the described building method for code modulated QC-LDPC code of employing, obtain QC-LDPC code;
S202, utilize described QC-LDPC code, information bit waiting for transmission is encoded, obtains coded-bit;
S203, bit mapping is carried out to described coded-bit, obtain constellation bit vectors;
S204, constellation mapping is carried out to described constellation bit vectors, obtain constellation symbol;
S205, described constellation symbol is sent to subsequent processing units.
Preferably, the code length of described QC-LDPC code is 61440 or 15360.
Preferably, step S203 specifically comprises:
S203-1, Bit Interleave is carried out to described coded-bit, obtain interleaving bits;
S203-2, bit permutation is carried out to described interleaving bits, obtains the bit vectors after replacing, and the bit vectors after described displacement is split, obtain described constellation bit vectors,
Wherein, described bit permutation refers to and all bits be mapped in one or more constellation symbol is carried out order adjustment.
Preferably, step S204 specifically comprises:
The APSK constellation of described constellation bit vectors being carried out to M point maps or qam constellation mapping, obtains described constellation symbol,
Wherein, the value of described M is 4,16,64 or 256.
Preferably, step S205 comprises further:
Described constellation symbol is carried out coordinate intertexture and symbol interleaving, then sends to described subsequent processing units.
In step S202, LDPC coding is carried out to information bit waiting for transmission, obtains coded-bit wherein NLDPC represents that LDPC code is long.
Preferably, the code length of described LDPC code is 61440 or 15360, and code check is 1/2,2/3,3/4 or 5/6.
In step S203, bit mapping is carried out to described coded-bit, obtain constellation bit vectors, as the result of bit mapping.Wherein, first bit mapping carries out interleaving treatment to coded-bit, then intertexture result is combined as bit vectors.
Preferably, described bit mapping specifically comprises the steps:
S203-1, Bit Interleave is carried out to gained coded-bit, obtain interleaving bits.
Wherein, the feature of described Bit Interleave is, coded-bit c is write by row line by line the buffering area of the capable b row of L, obtains Matrix C, namely
C = c 0 c 1 . . . c L - 1 ,
Interior intertexture gone to Matrix C, obtains matrix namely
C ~ = c ~ 0 c ~ 1 . . . c ~ L - 1 ,
Wherein c lwith respectively representing matrix C and l capable, 1≤l<L.Will read by column by row, obtain interleaving bits
Wherein, a kind of optimal way interweaved in row is, and the corresponding relation between the row of C and row is as follows: make lm=mod (l, m) represent the remainder of l mould m, wherein represent and round downwards, m=log 2m, M represent the exponent number of follow-up constellation mapping; Then c ~ l = c L / m &times; l m + l d .
Preferably, the value of parameter L is the value of L=120, parameter b is b=N lDPC/ L, that is, work as N lDPCwhen=61440, b=512, works as N lDPCwhen=15360, b=128.
S203-2, the bit permutation of to carry out successively described interleaving bits in one or more constellation symbol, be called for short bit permutation, obtains the bit vectors after replacing, split, obtain constellation bit vectors, as the result of bit mapping to the bit vectors after displacement.
Wherein, described bit permutation refers to and all bits be mapped in one or more constellation symbol is carried out order adjustment.
The concrete steps of bit permutation are, will every q successive bits be classified as one group, obtain bit vectors wherein the value of q is the positive integer times of m, and the bit vectors arranged after changing is then with corresponding relation be 0≤i < q, wherein p=(p 0, p 1..., p q-1) be called bit permutation pattern.
Wherein, the bit vectors after displacement is split, it is characterized in that, will every m successive bits be classified as one group, obtain one or more constellation bit vectors b=(b 0, b 1..., b m-1).
In step S204, the APSK constellation of described constellation bit vectors being carried out to M point maps or qam constellation mapping, obtains constellation symbol.Wherein, M's can selected value be 4,16,64 and 256.
Wherein, the feature of described M point APSK constellation figure is, all constellation point are distributed in N ron individual donut, the radius of each annulus is ascending to be followed successively by each ring has identical number of constellation points, is set to M c, therefore M=N r× M c, the constellation point on each ring is uniformly distributed in phase place [0,2 π), initial phase is deflected to θ 0.Therefore, planisphere can represent with following formula:
&chi; = { x n , k | x n , k = r n edp { j ( 2 &pi; M C k + &theta; 0 ) } } ,
Wherein, j is imaginary unit n=0,1 ..., N r-1, k=0,1 ..., M c-1.
Preferably, if M=4, then θ 0=0; If M=16,64,256, then θ 0=π/M c.
Preferably, when different M, annulus number N r, number of constellation points M on each ring c, each ring radius r value as shown in table 2, and each ring radius can zoom in or out in proportion.
Table 2 constellation mapping parameter list
In step S205, give subsequent processing units by the constellation symbol obtained, or, coordinate intertexture and symbol interleaving are carried out to described constellation symbol, then is sent to subsequent processing units.
The above is only the preferred embodiment of the present invention; it should be pointed out that for the person of ordinary skill of the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and replacement, these improve and replace and also should be considered as protection scope of the present invention.
Annex
e[1,3]=111 e[2,21]=95 e[3,34]=33 e[4,62]=116
e[1,11]=98 e[2,39]=72 e[3,66]=1 e[5,2]=8
e[1,39]=43 e[2,65]=1 e[4,5]=13 e[5,17]=40
e[1,56]=98 e[3,7]=35 e[4,8]=74 e[5,68]=1
e[2,1]=29 25 e[3,11]=54 30 e[4,45]=63 35 e[6,2]=115
e[6,10]=49 e[13,11]=81 55 e[20,6]=30 e[66,59]=95
e[6,56]=100 e[13,27]=48 e[20,16]=106 e[67,16]=12
e[6,69]=1 30 e[13,74]=17 e[20,83]=1 e[67,21]=70
e[7,6]=39 e[14,3]=17 e[61,4]=62 85 e[67,59]=84
e[7,12]=115 e[14,8]=31 e[61,16]=32 e[67,70]=1
e[7,43]=33 e[14,12]=126 60 e[61,47]=126 e[68,10]=29
e[8,1]=41 e[14,63]=71 e[61,64]=1 e[68,27]=35
e[8,7]=6 35 e[15,9]=43 e[62,6]=59 e[68,43]=70
e[8,16]=91 e[15,12]=60 e[62,13]=101 90 e[68,48]=34
e[8,71]=1 e[15,15]=25 e[62,15]=111 e[69,14]=57
e[9,3]=83 e[15,51]=101 65 e[62,47]=39 e[69,30]=102
e[9,6]=98 e[16,10]=91 e[63,1]=9 e[69,42]=4
e[9,15]=120 40 e[16,11]=52 e[63,15]=111 e[69,72]=1
e[9,35]=85 e[16,15]=25 e[63,59]=98 95 e[70,1]=63
e[10,8]=20 e[16,77]=78 e[63,63]=91 e[70,11]=122
e[10,17]=33 e[16,79]=1 70 e[64,9]=44 e[70,45]=68
e[10,21]=112 e[17,16]=57 e[64,16]=73 e[70,73]=1
e[10,42]=37 45 e[17,78]=48 e[64,27]=41 e[71,4]=83
e[11,5]=63 e[17,80]=1 e[64,67]=1 100 e[71,16]=124
e[11,13]=44 e[18,1]=57 e[65,9]=25 e[71,34]=80
e[11,49]=101 e[18,10]=47 75 e[65,15]=24 e[71,74]=1
e[11,73]=127 e[18,11]=26 e[65,43]=41 e[72,6]=115
e[12,34]=3 50 e[18,16]=34 e[65,49]=126 e[72,9]=20
e[12,42]=88 e[19,14]=7 e[65,56]=76 105 e[72,18]=51
e[12,64]=24 e[19,17]=35 e[66,12]=44 e[73,6]=110
e[12,75]=1 e[19,81]=71 80 e[66,14]=122 e[73,18]=25
e[13,2]=127 e[20,2]=72 e[66,45]=50 e[73,35]=95
e[73,76]=1 e[81,1]=59 55 e[84,58]=43 e[87,90]=1
e[74,16]=75 e[81,5]=117 e[84,60]=35 e[88,4]=5
e[74,49]=68 30 e[81,13]=18 e[84,76]=74 e[88,5]=112
e[74,75]=92 e[81,17]=127 e[84,87]=1 85 e[88,11]=114
e[74,77]=1 e[81,29]=87 e[85,1]=69 e[88,17]=81
e[75,69]=104 e[81,30]=92 60 e[85,5]=34 e[88,25]=9
e[75,71]=67 e[81,51]=123 e[85,12]=90 e[88,46]=59
e[75,78]=1 35 e[81,84]=1 e[85,18]=17 e[88,90]=29
e[76,4]=60 e[82,3]=13 e[85,25]=5 90 e[88,91]=1
e[76,29]=13 e[82,7]=67 e[85,58]=23 e[89,1]=74
e[76,32]=2 e[82,9]=47 65 e[85,79]=2 e[89,9]=44
e[77,7]=113 e[82,18]=13 e[85,88]=1 e[89,10]=113
e[77,14]=58 40 e[82,31]=64 e[86,3]=76 e[89,16]=78
e[77,29]=6 e[82,67]=19 e[86,8]=35 95 e[89,46]=114
e[77,58]=45 e[82,84]=93 e[86,11]=66 e[89,52]=7
e[78,35]=121 e[82,85]=1 70 e[86,15]=77 e[89,89]=4
e[78,51]=8 e[83,8]=84 e[86,24]=114 e[89,92]=1
e[78,80]=102 45 e[83,13]=79 e[86,55]=85 e[90,2]=15
e[78,81]=1 e[83,18]=74 e[86,82]=10 100 e[90,6]=54
e[79,6]=46 e[83,32]=115 e[86,89]=1 e[90,13]=34
e[79,25]=51 e[83,60]=123 75 e[87,1]=17 e[90,16]=62
e[79,32]=4 e[83,83]=126 e[87,7]=112 e[90,24]=78
e[79,82]=1 50 e[83,86]=1 e[87,14]=30 e[90,61]=92
e[80,11]=77 e[84,3]=38 e[87,15]=53 105 e[90,87]=92
e[80,30]=79 e[84,6]=59 e[87,31]=44 e[90,93]=1
e[80,31]=57 e[84,10]=10 80 e[87,60]=1 e[91,7]=1
e[80,41]=19 e[84,17]=102 e[87,88]=2 e[91,12]=6
e[91,17]=116 e[94,97]=1 55 e[98,12]=47 e[101,38]=16
e[91,24]=100 e[95,1]=58 e[98,18]=60 e[101,102]=101
e[91,65]=101 30 e[95,8]=7 e[98,62]=34 e[101,104]=1
e[91,72]=59 e[95,14]=91 e[98,68]=20 85 e[102,4]=65
e[91,94]=1 e[95,18]=119 e[98,95]=113 e[102,8]=120
e[92,2]=44 e[95,46]=14 60 e[98,101]=1 e[102,10]=65
e[92,7]=23 e[95,61]=22 e[99,1]=117 e[102,17]=108
e[92,11]=116 35 e[95,94]=21 e[99,9]=15 e[102,37]=41
e[92,17]=25 e[95,98]=1 e[99,11]=21 90 e[102,66]=82
e[92,36]=90 e[96,1]=36 e[99,18]=59 e[102,103]=43
e[92,52]=38 e[96,6]=32 65 e[99,40]=11 e[102,105]=1
e[92,85]=60 e[96,13]=24 e[99,66]=26 e[103,3]=1
e[92,95]=1 40 e[96,17]=26 e[99,97]=122 e[103,9]=68
e[93,8]=46 e[96,55]=53 e[99,102]=1 95 e[103,12]=51
e[93,12]=67 e[96,70]=68 e[100,3]=110 e[103,17]=105
e[93,16]=20 e[96,98]=118 70 e[100,5]=99 e[103,57]=52
e[93,36]=57 e[96,99]=1 e[100,12]=64 e[103,61]=49
e[93,41]=73 45 e[97,2]=103 e[100,18]=83 e[103,100]=101
e[93,91]=69 e[97,5]=83 e[100,40]=123 100 e[103,106]=1
e[93,96]=1 e[97,15]=26 e[100,53]=105 e[104,4]=116
e[94,4]=73 e[97,18]=7 75 e[100,93]=103 e[104,7]=31
e[94,6]=80 e[97,22]=39 e[100,103]=1 e[104,13]=83
e[94,14]=117 50 e[97,36]=123 e[101,2]=50 e[104,18]=39
e[94,17]=79 e[97,99]=17 e[101,8]=119 105 e[104,55]=110
e[94,26]=88 e[97,100]=1 e[101,10]=17 e[104,69]=33
e[94,52]=65 e[98,4]=110 80 e[101,18]=54 e[104,106]=112
e[94,96]=79 e[98,6]=44 e[101,26]=75 e[104,107]=1
e[105,3]=128 e[108,22]=124 55 e[111,108]=106 e[115,10]=101
e[105,7]=5 e[108,23]=29 e[111,114]=1 e[115,13]=83
e[105,13]=95 30 e[108,37]=2 e[112,4]=13 e[115,19]=29
e[105,26]=20 e[108,101]=93 e[112,10]=109 85 e[115,33]=14
e[105,41]=91 e[108,111]=1 e[112,15]=110 e[115,64]=66
e[105,44]=34 e[109,4]=11 60 e[112,38]=49 e[115,116]=42
e[105,105]=63 e[109,7]=88 e[112,44]=10 e[115,118]=1
e[105,108]=1 35 e[109,12]=81 e[112,54]=43 e[116,5]=76
e[106,5]=41 e[109,22]=125 e[112,111]=13 90 e[116,7]=75
e[106,9]=34 e[109,50]=29 e[112,115]=1 e[116,12]=127
e[106,13]=113 e[109,54]=102 65 e[113,5]=50 e[116,23]=81
e[106,40]=74 e[109,86]=66 e[113,10]=40 e[116,28]=76
e[106,50]=62 40 e[109,112]=1 e[113,14]=11 e[116,38]=31
e[106,63]=82 e[110,3]=12 e[113,50]=98 95 e[116,114]=96
e[106,92]=113 e[110,5]=68 e[113,57]=1 e[116,119]=1
e[106,109]=1 e[110,14]=42 70 e[113,65]=62 e[117,3]=7
e[107,4]=40 e[110,19]=114 e[113,115]=46 e[117,10]=62
e[107,8]=23 45 e[110,54]=122 e[113,116]=1 e[117,13]=114
e[107,11]=9 e[110,68]=83 e[114,2]=113 100 e[117,20]=127
e[107,23]=17 e[110,107]=42 e[114,7]=91 e[117,28]=43
e[107,57]=52 e[110,113]=1 75 e[114,15]=12 e[117,53]=75
e[107,67]=60 e[111,2]=65 e[114,20]=87 e[117,110]=121
e[107,109]=59 50 e[111,8]=68 e[114,33]=9 e[117,120]=1
e[107,110]=1 e[111,14]=19 e[114,62]=68 105 e[118,2]=112
e[108,3]=21 e[111,20]=14 e[114,113]=14 e[118,9]=41
e[108,9]=73 e[111,37]=37 80 e[114,117]=1 e[118,14]=56
e[108,13]=79 e[111,70]=26 e[115,2]=110 e[118,33]=34
e[118,39]=77
e[118,53]=3
e[118,104]=31
e[118,119]=49
e[119,5]=84
e[119,8]=19
e[119,15]=46
e[119,19]=75
e[119,47]=7
e[119,48]=75
e[119,112]=48
e[119,120]=26
e[120,4]=59
e[120,9]=98
e[120,14]=10
e[120,28]=107
e[120,44]=2
e[120,48]=69
e[120,117]=108
e[120,118]=116 。

Claims (7)

1. for a building method for code modulated QC-LDPC code, it is characterized in that, described building method comprises the following steps:
S101, build female code offset address matrix E of quasi-circulating low-density parity check QC-LDPC code, and to set submatrix exponent number be b, wherein,
Described matrix E is the matrix of the capable 12M row of 12M, and M is positive integer, the shift index e of described matrix E i, jmeet 0≤e i,j≤ b;
S102, described matrix E adds water index obtain matrix E ', the shift index e ' of described matrix E ' i,jmeet 0≤e ' i,j≤ b,
Described matrix E ' adds water index and obtains matrix E ", described matrix E " shift index e " i, jmeet 0≤e " i,j≤ b,
Described matrix E " above add water index obtain matrix E " ', described matrix E " ' shift index e " ' i, jmeet 0≤e " ' i, j≤ b;
S103, calculating code check are the offset address matrix E of the QC-LDPC code of 1/2 (1/2), wherein, described matrix E (1/2)shift index computing formula be:
e i , j ( 1 / 2 ) = e i , j + e i + 6 M , j , 1 &le; i &le; 6 M , 1 &le; j &le; 12 M ;
S104, calculating code check are the offset address matrix E of the QC-LDPC code of 2/3 (2/3), wherein, described matrix E (2/3)shift index computing formula be:
e i , j ( 2 / 3 ) = e i , j &prime; + e i + 4 M , j &prime; + e i + 8 M , j &prime; , 1 &le; i &le; 4 M , 1 &le; j &le; 12 M ;
S105, calculating code check are the offset address matrix E of the QC-LDPC code of 3/4 (3/4), wherein, described matrix E (3/4)shift index computing formula be:
e i , j ( 3 / 4 ) = e i , j &prime; &prime; + e i + 3 M , j &prime; &prime; + e i + 6 M , j &prime; &prime; + e i + 9 M , j &prime; &prime; , 1 &le; i &le; 3 M , 1 &le; j &le; 12 M ;
S106, calculating code check are the offset address matrix E of the QC-LDPC code of 5/6 (5/6), wherein, described matrix E (5/6)shift index computing formula be:
e i , j ( 5 / 6 ) = e i , j &prime; &prime; &prime; + e i + 2 M , j &prime; &prime; &prime; + e i + 4 M , j &prime; &prime; &prime; + e i + 6 M , j &prime; &prime; &prime; + e i + 8 M , j &prime; &prime; &prime; + e i + 10 M , j &prime; &prime; &prime; , 1 &le; i &le; 2 M , 1 &le; j &le; 12 M ;
S107, according to described matrix E (1/2)with described submatrix exponent number b, generate the QC-LDPC code that code check is 1/2, code length is 12M*b,
According to described matrix E (2/3)with described submatrix exponent number b, generate the QC-LDPC code that code check is 2/3, code length is 12M*b,
According to described matrix E (3/4)with described submatrix exponent number b, generate the QC-LDPC code that code check is 3/4, code length is 12M*b,
According to described matrix E (5/6)with described submatrix exponent number b, generate the QC-LDPC code that code check is 5/6, code length is 12M*b.
2. building method according to claim 1, is characterized in that, comprises step further after step S107:
S108, the numerical value of described submatrix exponent number b is revised as b ', wherein, described submatrix exponent number b ' meets
b &prime; &GreaterEqual; e i , j , e i , j &prime; , e i , j &prime; &prime; , e i , j &prime; &prime; &prime; , e i , j ( 1 / 2 ) , e i , j ( 2 / 3 ) , e i , j ( 3 / 4 ) , e i , j ( 5 / 6 ) ;
S109, according to described matrix E (1/2)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 1/2, code length is 12M*b ',
According to described matrix E (2/3)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 2/3, code length is 12M*b ',
According to described matrix E (3/4)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 3/4, code length is 12M*b ',
According to described matrix E (5/6)with described submatrix exponent number b ', generate the QC-LDPC code that code check is 5/6, code length is 12M*b '.
3. a code modulating method, is characterized in that, described code modulating method comprises the following steps:
S201, the building method for code modulated QC-LDPC code of employing described in claim 1 or 2, obtain QC-LDPC code;
S202, utilize described QC-LDPC code, information bit waiting for transmission is encoded, obtains coded-bit;
S203, bit mapping is carried out to described coded-bit, obtain constellation bit vectors;
S204, constellation mapping is carried out to described constellation bit vectors, obtain constellation symbol;
S205, described constellation symbol is sent to subsequent processing units.
4. code modulating method according to claim 3, is characterized in that, the code length of described QC-LDPC code is 61440 or 15360.
5. code modulating method according to claim 3, is characterized in that, step S203 specifically comprises:
S203-1, Bit Interleave is carried out to described coded-bit, obtain interleaving bits;
S203-2, bit permutation is carried out to described interleaving bits, obtains the bit vectors after replacing, and the bit vectors after described displacement is split, obtain described constellation bit vectors,
Wherein, described bit permutation refers to and all bits be mapped in one or more constellation symbol is carried out order adjustment.
6. code modulating method according to claim 3, is characterized in that, step S204 specifically comprises:
The APSK constellation of described constellation bit vectors being carried out to M point maps or qam constellation mapping, obtains described constellation symbol,
Wherein, the value of described M is 4,16,64 or 256.
7. code modulating method according to claim 3, is characterized in that, step S205 comprises further:
Described constellation symbol is carried out coordinate intertexture and symbol interleaving, then sends to described subsequent processing units.
CN201210380776.1A 2012-10-10 2012-10-10 For building method and the code modulating method of code modulated QC-LDPC code Active CN102904686B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210380776.1A CN102904686B (en) 2012-10-10 2012-10-10 For building method and the code modulating method of code modulated QC-LDPC code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210380776.1A CN102904686B (en) 2012-10-10 2012-10-10 For building method and the code modulating method of code modulated QC-LDPC code

Publications (2)

Publication Number Publication Date
CN102904686A CN102904686A (en) 2013-01-30
CN102904686B true CN102904686B (en) 2015-08-12

Family

ID=47576744

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210380776.1A Active CN102904686B (en) 2012-10-10 2012-10-10 For building method and the code modulating method of code modulated QC-LDPC code

Country Status (1)

Country Link
CN (1) CN102904686B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103763298A (en) * 2014-01-02 2014-04-30 清华大学 Code modulation method and system based on APSK constellation mapping
CN104579576B (en) * 2015-01-27 2018-02-09 清华大学 Code modulating method and system
KR101776273B1 (en) 2015-02-25 2017-09-07 삼성전자주식회사 Transmitter and method for generating additional parity thereof
CN112165335B (en) 2015-02-25 2023-09-01 三星电子株式会社 Transmitting apparatus and receiving apparatus
CN108400836B (en) * 2017-02-08 2020-03-27 清华大学 Construction and coding method of multi-code-rate multi-code-length QC-LDPC code
CN108667556B (en) * 2017-03-29 2021-07-30 上海交通大学 Bit interleaving coding modulation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047387A (en) * 2007-03-23 2007-10-03 北京大学 Construction method of multi-code rate compatible LDPC code and its decoder
CN101170530A (en) * 2006-10-27 2008-04-30 中兴通讯股份有限公司 OFDM multi-carrier digital TV data framing transmission device and method
CN102075196A (en) * 2010-12-10 2011-05-25 清华大学 Multi-code rate multi-code length QC-LDPC code construction method and coding modulation system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7222284B2 (en) * 2003-06-26 2007-05-22 Nokia Corporation Low-density parity-check codes for multiple code rates

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101170530A (en) * 2006-10-27 2008-04-30 中兴通讯股份有限公司 OFDM multi-carrier digital TV data framing transmission device and method
CN101047387A (en) * 2007-03-23 2007-10-03 北京大学 Construction method of multi-code rate compatible LDPC code and its decoder
CN102075196A (en) * 2010-12-10 2011-05-25 清华大学 Multi-code rate multi-code length QC-LDPC code construction method and coding modulation system

Also Published As

Publication number Publication date
CN102904686A (en) 2013-01-30

Similar Documents

Publication Publication Date Title
CN102904686B (en) For building method and the code modulating method of code modulated QC-LDPC code
CN109891753B (en) Method and apparatus for encoding and decoding LDPC code
CN110086474B (en) Transmitter apparatus and signal processing method thereof
CN1866751B (en) Construction method and device for low density parity codes
CN110114978B (en) Efficient decodable QC-LDPC codes
CN102075196B (en) Multi-code rate multi-code length QC-LDPC coding method and coding modulation system
WO2014200304A1 (en) Method and apparatus for encoding and decoding low density parity check
CN103339862A (en) Data processing device and data processing method
US20150200747A1 (en) Transmission method, reception method, transmitter, and receiver
CN103944586A (en) Method for constructing code-rate compatibility QC-LDPC code
US10374632B2 (en) Low density parity check coded modulation for optical communications
CN106165301B (en) Communication method and communication device
WO2008016117A1 (en) Inspection matrix generation method, encoding method, communication device, communication system, and encoder
CN100592639C (en) Low density parity check coding method, device and parity check matrix generating method
EP2510623A2 (en) Method and apparatus for channel encoding and decoding in a communication system using a low-density parity check code
CN103731235A (en) Code modulation method based on bit mapping and corresponding demodulation and decoding method thereof
KR102606202B1 (en) Transmitting apparatus and signal processing method thereof
KR102598272B1 (en) Transmitting apparatus and signal processing method thereof
KR102606204B1 (en) Transmitting apparatus and signal processing method thereof
KR102531733B1 (en) Transmitting apparatus and signal processing method thereof
CN107786210B (en) Middle and high code rate LDPC code word structure and coding method for multi-point cooperative communication system
KR102482110B1 (en) Apparatus and method for channel encoding/decoding in communication or broadcasting system
CN102811064B (en) Method for constructing multi-rate low density parity check (LDPC) code
CN104426553A (en) Encoding method for low-density parity check matrix
KR102146803B1 (en) Method and apparatus for encoding and decoding of parity-check codes

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: NATIONAL ENGINEERING LABORATORY FOR DIGITAL TV (BE

Effective date: 20140623

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20140623

Address after: 100084 mailbox, 100084-82 Tsinghua Yuan, Haidian District, Beijing, Beijing

Applicant after: Tsinghua University

Applicant after: National Engineering Lab. For DTV (Beijing)

Address before: 100084 mailbox, 100084-82 Tsinghua Yuan, Haidian District, Beijing, Beijing

Applicant before: Tsinghua University

C14 Grant of patent or utility model
GR01 Patent grant