CN102903703A - Chip packaging stacking structure - Google Patents
Chip packaging stacking structure Download PDFInfo
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- CN102903703A CN102903703A CN2011102142107A CN201110214210A CN102903703A CN 102903703 A CN102903703 A CN 102903703A CN 2011102142107 A CN2011102142107 A CN 2011102142107A CN 201110214210 A CN201110214210 A CN 201110214210A CN 102903703 A CN102903703 A CN 102903703A
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- stacked structure
- chip
- front surface
- chip package
- heat dissipating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a chip packaging stacking structure which is formed by stacking two or more than two packaging structures in the vertical direction, and a heat dissipation layer is arranged between every two adjacent packaging structures. The heat dissipation layer is arranged between every two adjacent packaging structures, thereby enhancing the heat dissipation capacity of the chip packaging stacking structure and improving the properties of the chip packaging stacking structure.
Description
Technical field
The present invention relates to the semiconductor packaging field, relate in particular to a kind of chip package stacked structure.
Background technology
Along with the development of integrated circuit technique, the encapsulation technology of integrated circuit is also in continuous improve, and its developing direction is mainly to light, thin, short, little development in pluralism, and also more and more higher to the requirement of integrated level; Requirement is integrated more chip apparatus on given space.This demand has driven the development of three-dimension packaging, and laminated chips encapsulation and encapsulation stacking (POP, Package on Package) all belong to three-dimensional packaging technology.
With respect to laminated chips, the advantage of encapsulation stacking (POP) is: each assembly can be tested first before assembling, guaranteed the functional of each discrete device.This advantage is conducive to the raising of whole package module yield.Therefore, encapsulation stacking (POP) structure is subject to paying close attention to more and more widely in the portable product such as mobile phone.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of existing chip package laminated construction, and as shown in Figure 1, existing chip package laminated construction is formed by two-layer encapsulation stacking, comprising: bottom package 200, and be stacked in top encapsulation 100 on the described bottom package 200.Wherein, described bottom package 200 comprises:
Bottom package soldered ball 240 is positioned at the bottom surface of described base substrate 220, is electrically connected with the bottom surface of described base substrate 220;
Bottom epoxy-plastic packaging material 230 is sealed in described logic chip 210, adhesive layer and lead-in wire on the front surface of described base substrate 220.
Described top encapsulation 100 comprises:
The storage chip stacked structure is fixed in the front surface of described top substrate 120, and described storage chip stacked structure is by one or more storage chip 110 stacking forming; Particularly, described storage chip stacked structure is fixed in the front surface of described top substrate 120 by adhesive layer, and carries out bonded stack by adhesive layer between described a plurality of storage chip 110; And each storage chip 110 in the described storage chip stacked structure all is electrically connected to the front surface of described top substrate 120 by lead-in wire;
Top encapsulation soldered ball 140 is positioned at the bottom surface of described top substrate 120, is electrically connected with the bottom surface of described top substrate 120; And the diameter of described top encapsulation soldered ball 140 is greater than the height of bottom epoxy-plastic packaging material 230, thereby so that between the top of described bottom epoxy-plastic packaging material 230 and the described top substrate 120 interval is arranged;
Top epoxy-plastic packaging material 130 is sealed in described storage chip stacked structure, adhesive layer and lead-in wire on the front surface of described top substrate 120.
Yet there are the following problems for above-mentioned existing chip stack package (POP) structure:
1) power than the storage chip 110 in the top encapsulation 100 is large usually for the power of the logic chip 210 in the bottom package 200, so that the heat that bottom package 200 produces is larger than the heat that top encapsulation 100 produces, thereby, the temperature of bottom package 200 is higher than the temperature of top encapsulation 100, thereby so that the Temperature Distribution of whole chip stack package (POP) structure is very inhomogeneous, easily cause bottom package 200 because thermal expansion produces flexural deformation, further affect the reliability of bottom package soldered ball 240;
2) since the power of logic chip 210 in the bottom package 200 power than the storage chip 110 in the top encapsulation 100 is large usually, thereby the logic chip in the bottom package 200 210 is the highest positions of temperature in the whole chip stack package (POP); In above-mentioned prior art, the heat that logic chip 210 produces by the air transmitted between top encapsulation 100 and the bottom package 200 to external environment condition; And the air between top encapsulation 100 and the bottom package 200 is the non-conductor of heat, and its conductive coefficient only is 0.023W/mk; Thereby, the heat that the logic chip 210 of the bottom package 200 in existing chip stack package (POP) structure produces can not in time be derived, so that the heat problem of whole encapsulating structure is more serious, directly affect the useful life of chip stack package (POP) structure.
Therefore, be necessary existing chip stack package (POP) structure is improved.
Summary of the invention
The object of the present invention is to provide a kind of chip stack package structure, to improve the performance of chip stack package structure.
For addressing the above problem, the present invention proposes a kind of chip package stacked structure, and the encapsulating structure in the vertical direction is stacking forms by two or more for this chip package stacked structure, is provided with heat dissipating layer between each encapsulating structure.
Optionally, the thermal conductivity of described heat dissipating layer is more than 1W/mk.
Optionally, the material of described heat dissipating layer is any in scolder, heat-conducting glue, the macromolecule polymer material.
Optionally, described heat dissipating layer links to each other neighbouring two encapsulating structures.
Optionally, described heat dissipating layer is arranged on lower floor's encapsulating structure of two adjacent encapsulating structures, and and two adjacent encapsulating structures in the upper strata encapsulating structure between have a spacing.
Optionally, the upper surface of described heat dissipating layer forms V-groove, to increase its cooling surface area.
Optionally, the upper surface of described heat dissipating layer also scribbles the coating material that increases convection transfer rate.
Optionally, this chip package stacked structure is by two stacking formation of encapsulating structure in the vertical direction.
Optionally, this chip package stacked structure specifically comprises the bottom package structure and is stacked on the structural top encapsulation structure of described bottom package, is provided with described heat dissipating layer between described bottom package structure and the described top encapsulation structure.
Optionally, described bottom package structure comprises:
Base substrate has a front surface and the bottom surface relative with described front surface;
Logic chip is fixed in the front surface of described base substrate, and is electrically connected to the front surface of described base substrate by lead-in wire;
The bottom package soldered ball is positioned at the bottom surface of described base substrate, is electrically connected with the bottom surface of described base substrate;
The bottom epoxy-plastic packaging material is sealed in described logic chip and lead-in wire on the front surface of described base substrate.
Optionally, described top encapsulation structure comprises:
Top substrate has a front surface and the bottom surface relative with described front surface;
The storage chip stacked structure is fixed in the front surface of described top substrate, and described storage chip stacked structure forms by one or more storage chips are stacking; And each storage chip in the described storage chip stacked structure all is electrically connected to the front surface of described top substrate by lead-in wire;
The top encapsulation soldered ball is positioned at the bottom surface of described top substrate, is electrically connected with the bottom surface of described top substrate; And the diameter of described top encapsulation soldered ball is greater than the height of bottom epoxy-plastic packaging material, so that between the top of described bottom epoxy-plastic packaging material and the described top substrate interval is arranged;
The top epoxy-plastic packaging material is sealed in described storage chip stacked structure and lead-in wire on the front surface of described top substrate.
Compared with prior art, chip package stacked structure provided by the invention is by being provided with heat dissipating layer between each encapsulating structure, thereby increased the heat-sinking capability of chip package stacked structure, the heat dissipating layer that is full of the gap also plays the effect of interface unit simultaneously, increase the stacked package integral rigidity, improved the performance of chip package stacked structure.
Description of drawings
Fig. 1 is the schematic diagram of existing chip package laminated construction;
The schematic diagram of the chip package laminated construction that Fig. 2 provides for first embodiment of the invention;
The schematic diagram of the chip package laminated construction that Fig. 3 provides for second embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the chip package stacked structure that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-accurately ratio, only is used for convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of chip package stacked structure is provided, by between each encapsulating structure, being provided with heat dissipating layer, thereby increased the heat-sinking capability of chip package stacked structure, the heat dissipating layer that is full of the gap also plays the effect of interface unit simultaneously, increase the stacked package integral rigidity, improved the performance of chip package stacked structure.
Embodiment 1
Please refer to Fig. 2, the schematic diagram of the chip package laminated construction that Fig. 2 provides for first embodiment of the invention, as shown in Figure 2, in the vertical direction is stacking forms by two encapsulating structures (bottom package structure 200 and top encapsulation structure 100) for the chip package laminated construction that first embodiment of the invention provides, and is provided with heat dissipating layer 300 between bottom package structure 200 and the top encapsulation structure 100.By between bottom package structure 200 and top encapsulation structure 100, being provided with heat dissipating layer 300, thereby increase the heat-sinking capability of chip package stacked structure, improved the performance of chip package stacked structure.
Further, the thermal conductivity of described heat dissipating layer 300 is more than 1W/mk, thereby the dissipation of heat that can well encapsulating structure be produced is to environment; Concrete, the material of described heat dissipating layer 300 is any in scolder, heat-conducting glue, the macromolecule polymer material.
Further, described heat dissipating layer 300 links to each other bottom package structure 200 and top encapsulation structure 100, thereby the heat of bottom package structure 200 can be transmitted on the top encapsulation structure 100, so that the Temperature Distribution of whole chip package stacked structure is more even, the degree of irregularity of Temperature Distribution in the encapsulating structure is alleviated the thermal reliability problem that produces owing to temperature distributing disproportionation about having reduced.And, the heat that whole chip package stacked structure produces can conduct in the air of external environment by top encapsulation structure 100, thereby improved the heat-sinking capability of whole chip package stacked structure, reduce the bending that bottom package structure 200 produces because of thermal expansion, further reduce the failure probability of soldered ball, alleviate the heat problem that produces owing to heat dispersion is poor, improve the life-span of chip package stacked structure.
Wherein, described bottom package structure 200 comprises:
Bottom package soldered ball 240 is positioned at the bottom surface of described base substrate 220, is electrically connected with the bottom surface of described base substrate 220;
Bottom epoxy-plastic packaging material 230 is sealed in described logic chip 210, adhesive layer and lead-in wire on the front surface of described base substrate 220.
Described top encapsulation structure 100 comprises:
The storage chip stacked structure is fixed in the front surface of described top substrate 120, and described storage chip stacked structure is by one or more storage chip 110 stacking forming (only having illustrated two among the figure); And each storage chip 110 in the described storage chip stacked structure all is electrically connected to the front surface of described top substrate 120 by lead-in wire; Particularly, described storage chip stacked structure is fixed in the front surface of described top substrate 120 by adhesive layer, and carries out bonded stack by adhesive layer between described each storage chip 110;
Top encapsulation soldered ball 140 is positioned at the bottom surface of described top substrate 120, is electrically connected with the bottom surface of described top substrate 120; And the diameter of described top encapsulation soldered ball 140 is greater than the height of bottom epoxy-plastic packaging material 230, thereby so that between the top of described bottom epoxy-plastic packaging material 230 and the described top substrate 120 interval is arranged;
Top epoxy-plastic packaging material 130 is sealed in described storage chip stacked structure, adhesive layer and lead-in wire on the front surface of described top substrate 120.
In a specific embodiment of the present invention, described chip package laminated construction comprises bottom package structure 200 and 100 two encapsulating structures of top encapsulation structure, and described heat dissipating layer 300 is arranged between described bottom package structure 200 and the described top encapsulation structure 100; Yet should be realized that, the present invention is not as limit, and chip package laminated construction provided by the invention can also comprise two above encapsulating structures, and is provided with the described heat dissipating layer 300 of first embodiment of the invention between adjacent two encapsulating structures.
Embodiment 2
Please refer to Fig. 3, the schematic diagram of the chip package laminated construction that Fig. 3 provides for second embodiment of the invention, as shown in Figure 3, the difference of the chip package laminated construction that chip package laminated construction and the first embodiment of the invention that second embodiment of the invention provides provides is that institute's heat dissipating layer 300 is not connected neighbouring two encapsulating structures, has a spacing between the upper strata encapsulating structure during namely institute's heat dissipating layer 300 connects from neighbouring two encapsulating structures.To comprise bottom package structure 200 and 100 two encapsulating structure chip packages of top encapsulation structure laminated construction, described heat dissipating layer 300 is arranged on the described bottom package structure 200, and from there being a spacing between the described top encapsulation structure 100.
Further, the upper surface of described heat dissipating layer 300 forms V-groove, thereby can increase its cooling surface area, improves the heat-sinking capability of bottom package structure 200; And, the upper surface of described heat dissipating layer 300 also scribbles the coating material that increases convection transfer rate, thereby increase the heat-exchange capacity between described bottom package structure 200 and the described top encapsulation structure 100, heat with bottom package structure 200 is transmitted on the top encapsulation structure 100 better, so that the Temperature Distribution of whole chip package stacked structure is more even, the degree of irregularity of Temperature Distribution in the encapsulating structure is alleviated the thermal reliability problem that produces owing to temperature distributing disproportionation about having reduced.
Except above-mentioned difference, the chip package laminated construction that chip package laminated construction and the first embodiment of the invention that second embodiment of the invention provides provides is all identical, therefore repeats no more.
In a specific embodiment of the present invention, described chip package laminated construction comprises bottom package structure 200 and 100 two encapsulating structures of top encapsulation structure, and described heat dissipating layer 300 is arranged between described bottom package structure 200 and the described top encapsulation structure 100; Yet should be realized that, the present invention is not as limit, and chip package laminated construction provided by the invention can also comprise two above encapsulating structures, and is provided with the described heat dissipating layer 300 of second embodiment of the invention between adjacent two encapsulating structures.
In sum, the invention provides a kind of chip package stacked structure, the encapsulating structure in the vertical direction is stacking forms by two or more for this chip package stacked structure, and is provided with heat dissipating layer between each encapsulating structure; By between each encapsulating structure, heat dissipating layer being set, thereby increased the heat-sinking capability of chip package stacked structure, the heat dissipating layer that is full of the gap also plays the effect of interface unit simultaneously, increases the stacked package integral rigidity, has improved the performance of chip package stacked structure.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (11)
1. chip package stacked structure, the encapsulating structure in the vertical direction is stacking forms by two or more, it is characterized in that, is provided with heat dissipating layer between each encapsulating structure.
2. chip package stacked structure as claimed in claim 1 is characterized in that, the thermal conductivity of described heat dissipating layer is more than 1W/mk.
3. chip package stacked structure as claimed in claim 2 is characterized in that, the material of described heat dissipating layer is any in scolder, heat-conducting glue, the macromolecule polymer material.
4. chip package stacked structure as claimed in claim 3 is characterized in that, described heat dissipating layer links to each other neighbouring two encapsulating structures.
5. chip package stacked structure as claimed in claim 3 is characterized in that, described heat dissipating layer is arranged on lower floor's encapsulating structure of two adjacent encapsulating structures, and and two adjacent encapsulating structures in the upper strata encapsulating structure between have a spacing.
6. chip package stacked structure as claimed in claim 5 is characterized in that, the upper surface of described heat dissipating layer forms V-groove.
7. chip package stacked structure as claimed in claim 6 is characterized in that, the upper surface of described heat dissipating layer also scribbles the coating material that increases convection transfer rate.
8. such as each described chip package stacked structure of claim 1 to 7, it is characterized in that, this chip package stacked structure is by two stacking formation of encapsulating structure in the vertical direction.
9. chip package stacked structure as claimed in claim 8, it is characterized in that, this chip package stacked structure specifically comprises the bottom package structure and is stacked on the structural top encapsulation structure of described bottom package, is provided with described heat dissipating layer between described bottom package structure and the described top encapsulation structure.
10. chip package stacked structure as claimed in claim 9 is characterized in that, described bottom package structure comprises:
Base substrate has a front surface and the bottom surface relative with described front surface;
Logic chip is fixed in the front surface of described base substrate, and is electrically connected to the front surface of described base substrate by lead-in wire;
The bottom package soldered ball is positioned at the bottom surface of described base substrate, is electrically connected with the bottom surface of described base substrate;
The bottom epoxy-plastic packaging material is sealed in described logic chip and lead-in wire on the front surface of described base substrate.
11. chip package stacked structure as claimed in claim 10 is characterized in that, described top encapsulation structure comprises:
Top substrate has a front surface and the bottom surface relative with described front surface;
The storage chip stacked structure is fixed in the front surface of described top substrate, and described storage chip stacked structure forms by one or more storage chips are stacking; And each storage chip in the described storage chip stacked structure all is electrically connected to the front surface of described top substrate by lead-in wire;
The top encapsulation soldered ball is positioned at the bottom surface of described top substrate, is electrically connected with the bottom surface of described top substrate; And the diameter of described top encapsulation soldered ball is greater than the height of bottom epoxy-plastic packaging material, so that between the top of described bottom epoxy-plastic packaging material and the described top substrate interval is arranged;
The top epoxy-plastic packaging material is sealed in described storage chip stacked structure and lead-in wire on the front surface of described top substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102142107A CN102903703A (en) | 2011-07-28 | 2011-07-28 | Chip packaging stacking structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102142107A CN102903703A (en) | 2011-07-28 | 2011-07-28 | Chip packaging stacking structure |
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| Publication Number | Publication Date |
|---|---|
| CN102903703A true CN102903703A (en) | 2013-01-30 |
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|---|---|---|---|
| CN2011102142107A Pending CN102903703A (en) | 2011-07-28 | 2011-07-28 | Chip packaging stacking structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231724A (en) * | 2016-12-14 | 2018-06-29 | 南亚科技股份有限公司 | Semiconductor structure and its manufacturing method |
| CN109449148A (en) * | 2018-09-25 | 2019-03-08 | 深圳市奥拓电子股份有限公司 | LED encapsulation structure and LED display system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883426A (en) * | 1996-04-18 | 1999-03-16 | Nec Corporation | Stack module |
| KR20070076084A (en) * | 2006-01-17 | 2007-07-24 | 삼성전자주식회사 | Stack package and manufacturing method thereof |
| CN101197354A (en) * | 2006-12-08 | 2008-06-11 | 日月光半导体制造股份有限公司 | Stack packaging structure |
| US20110176280A1 (en) * | 2010-01-20 | 2011-07-21 | Samsung Electronics Co., Ltd. | Stacked semiconductor package |
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2011
- 2011-07-28 CN CN2011102142107A patent/CN102903703A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883426A (en) * | 1996-04-18 | 1999-03-16 | Nec Corporation | Stack module |
| KR20070076084A (en) * | 2006-01-17 | 2007-07-24 | 삼성전자주식회사 | Stack package and manufacturing method thereof |
| CN101197354A (en) * | 2006-12-08 | 2008-06-11 | 日月光半导体制造股份有限公司 | Stack packaging structure |
| US20110176280A1 (en) * | 2010-01-20 | 2011-07-21 | Samsung Electronics Co., Ltd. | Stacked semiconductor package |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231724A (en) * | 2016-12-14 | 2018-06-29 | 南亚科技股份有限公司 | Semiconductor structure and its manufacturing method |
| CN109449148A (en) * | 2018-09-25 | 2019-03-08 | 深圳市奥拓电子股份有限公司 | LED encapsulation structure and LED display system |
| CN109449148B (en) * | 2018-09-25 | 2020-10-16 | 深圳市奥拓电子股份有限公司 | LED packaging structure and LED display system |
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Application publication date: 20130130 |