CN102903670A - Low-cost TSV (through silicon via) three-dimensional integration process method - Google Patents
Low-cost TSV (through silicon via) three-dimensional integration process method Download PDFInfo
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Abstract
The invention discloses a low-cost TSV (through silicon via) three-dimensional integration process method. The method is characterized in that barrier layer and seeding layer fabrication steps, and a copper plating step are directly carried out after an insulation layer is fabricated on the side wall of a TSV. In comparison with the conventional TSV process, the method obviates six steps of gluing, exposure, development, CD (critical dimension) measurement, silicon dioxide etching, and resist removal; and an over-thinning step is carried out moderately to remove the insulation layer on the bottom of the TSV while thinning the back side of a wafer, so that all processes are substantially in the same plane to obviate photolithography and etching steps which are carried out in the prior art to remove the insulation layer on the bottom of the TSV with a depth of tens of micrometers, thereby obviating the need for expensive special equipment. The low-cost TSV three-dimensional integration process method provided by the invention has the advantages of short process flow, high efficiency, and low process cost.
Description
Technical field
The present invention relates to microelectronics technology.
Background technology
Traditional TSV is three-dimensional integrated to be after the through-hole side wall insulating process is finished, and forms the photoresist protection at through-hole side wall, etches away bottom insulation layer, then makes barrier layer and Seed Layer and electro-coppering.The paper of delivering such as IMEC Corp. and the patent (200910082236.3 " a kind of manufacture method of insulating barrier of TSV through hole ") of having applied for etc.The characteristics of this method are so that keep dielectric film between barrier layer and Seed Layer and the through-hole side wall; and dielectric film is removed in the bottom; but for dark tens of microns large depth-to-width ratio through hole; common photoetching, automatic double surface gluer are difficult to through-hole side wall is formed good protection; and during etching TSV via bottoms insulating barrier; more difficult complete clean removal bottom insulating film, and degumming process afterwards also is larger challenge.At present general targetedly way is, adopts the special-purpose glue spraying equipment of TSV, large depth of field exposure machine, special-purpose etching and degumming equipment, the shortcoming of this flow process be special equipment expensive drop into huge, technique is loaded down with trivial details, efficient is low.
Summary of the invention
In order to overcome the deficiencies in the prior art, the invention provides the three-dimensional integrated technique technology of a kind of low-cost TSV, save the sidewall gluing, removed at the bottom of the hole the larger technique of difficulty such as dielectric film, use existing etching, deposit, the technologies such as plating and cmp can form the good greatly TSV hole of depth-to-width ratio of homogeneity, reduce cost, improved efficient.And in conjunction with three-dimensional integrated technique technology, in the vertical direction multilayer two-dimension Planar integration IC is carried out the solid interconnection, greatly improved capacity and the integrated level of IC.
The technical solution adopted for the present invention to solve the technical problems may further comprise the steps:
(1) at the silicon dioxide of silicon chip surface deposit 1500A thickness, at the silica surface resist coating, and exposure imaging, exposing needs the silicon dioxide of etching window;
(2) at window etching silicon dioxide layer, and the etching silicon wafer substrate, forming a TSV deep hole that the degree of depth is 500000A～600000A, SPM cleans, and removes the photoresist on surface, uses the BOE etching liquid, removes the silicon dioxide layer of silicon chip surface;
(3) form the silicon dioxide insulating layer of 150A thickness at Si sheet surface deposition;
(4) tantalum nitride barrier layer of deposit 150A, the copper seed layer of deposit 150A;
(5) at the silicon chip surface resist coating, exposure and photoetching form the window that needs electro-coppering;
(6) at silicon chip surface electro-coppering 600000A～700000A, use SPM to clean and remove photoresist;
(7) cmp, the silicon dioxide insulating layer that is ground to silicon chip is surperficial;
(8) use the silicon slide glass to be bonded in the silicon chip surface that had ground;
(9) silicon chip back side carries out cmp, exposes to the base copper surface in TSV hole;
(10) at the silicon dioxide insulating layer of silicon chip back side deposit 150A, resist coating, exposure, develop, expose and need the TSV of barrier layer hole bottom, use the BOE etching liquid, etch away the silicon dioxide layer of the 150A in the hole, the tantalum nitride barrier layer of deposit 150A, the then copper seed layer of deposit 150A;
(11) at the silicon chip back side resist coating, exposure is also developed, and exposes the window of electro-coppering;
(12) at the copper of the whole back side plating of silicon chip 15000A, use SPM to clean, remove photoresist;
(13) carry out scribing in the scribing road of silicon chip surface, form tube core;
(14) back side alignment keys of tube core is combined in the surface of another sheet silicon chip;
(15) silicon chip surface that is bonded is carried out scribing, remove unwanted part;
(16) the slide glass bonding of releasing die surfaces removes slide glass.
The invention has the beneficial effects as follows: the three-dimensional integrated technique flow process of low-cost TSV proposed by the invention is directly made barrier layer and Seed Layer and electro-coppering after TSV through-hole side wall insulating barrier completes, with compare with traditional TSV technological process, reduced gluing, exposure, development, CD measurement, silicon dioxide etching, remove photoresist 6 the step operations, this flow process is carried out appropriateness and is crossed attenuate removal TSV via bottoms insulating barrier (this operation is the indispensable operation of TSV technique, does not increase additional technical steps and equipment) when thinning back side of silicon wafer.After processing step is so adjusted, all techniques all are in the same plane substantially, avoided conventional process flow to carry out photoetching, etching to the dark TSV via bottoms insulating barrier of tens of microns, therefore do not needed the dark TSV via bottoms of tens of microns is carried out the special-purpose glue spraying equipment of technique, large depth of field exposure machine, special-purpose etching and degumming equipment etc.It is short that this flow process has technological process, saved expensive special equipment, and efficient is high, process costs is low, be efficiently, the three-dimensional integrated technique technology of TSV cheaply.Adopt this technique to save tens million of special equipments and drop into, can significantly reduce the three-dimensional integrated device cost of TSV, economic benefit is obvious.
Description of drawings
Fig. 1: the flow chart that is the TSV hole etching process of traditional silicon substrate
Fig. 2: the TSV hole etching process that is traditional silicon substrate;
Among the figure, (1) deposit silicon dioxide and photoetching, (2) etching silicon dioxide layer and silicon substrate, and remove silicon dioxide layer, (3) deposition insulating layer, and remove the hole bottom insulation layer, and (4) barrier layer and Seed Layer, (5) make the plating area by lithography, (6) electro-coppering, (7) cmp, the interim bonding of (8) slide glass, (9) silicon chip back side attenuate, (10) deposition insulating layer, barrier layer and Seed Layer, (11) make the plating area by lithography, (12) electro-coppering, (13) scribing, (14) tube core is aimed at bonding with silicon chip, (15) scribing, and (16) separate bonding;
The 1-silicon substrate, 2-photoresist, the silicon dioxide layer of 3-deposit, 4-insulating barrier, 5-barrier layer and Seed Layer, 6-copper, 7-slide glass, 8-insulating barrier, 9-barrier layer and Seed Layer, 10-copper;
Fig. 3: the flow chart that is the TSV hole etching process of the novel silicon substrate of the present invention
Fig. 4: the TSV hole etching process that is the novel silicon substrate of the present invention;
Among the figure, (1) deposit silicon dioxide and photoetching, (2) etching silicon dioxide layer and silicon substrate, and remove silicon dioxide layer, (3) deposition insulating layer, (4) barrier layer and Seed Layer, (5) make the plating area by lithography, (6) electro-coppering, (7) cmp, (8) the interim bonding of slide glass, (9) silicon chip back side attenuate, (10) deposition insulating layer, barrier layer and Seed Layer, (11) make the plating area by lithography, (12) electro-coppering, (13) scribing, (14) tube core is aimed at bonding with silicon chip, (15) scribing, (16) separate bonding;
The 1-silicon substrate, 2-photoresist, the silicon dioxide layer of 3-deposit, 4-insulating barrier, 5-barrier layer and Seed Layer, 6-copper, 7-slide glass, 8-insulating barrier, 9-barrier layer and Seed Layer, 10-copper.
Embodiment
For the TSV hole of large depth-to-width ratio, be difficult to form the Coating glue protect of oppose side wall, the insulating barrier at the bottom of the hole remove fully and the difficulty of the degumming process of sidewall also larger, need to use special equipment, cost is high, efficient is low.The present invention has realized cheaply TSV hole etching.In technical process, after finishing TSV through-hole side wall insulation operation, do not remove specially the via bottoms insulating barrier, but the time carry out the techniques such as barrier/seed layers deposit, cross the attenuate mode in conjunction with the chemical machinery technique through hole of subsequent wafer attenuate and remove TSV via bottoms insulating barrier, solved the special equipment of the large depth-to-width ratio TSV through-hole side wall of conventional process flow and the special use of bottom gluing, photoetching, insulating barrier etching costliness, process costs is low, the problem that efficient is high.
Technical scheme
The novel technical matters method of the present invention is: (1) at the silicon dioxide of silicon chip surface deposit 1500A thickness, at the silica surface resist coating, and exposure imaging, exposing needs the silicon dioxide of etching window; (2) at window etching silicon dioxide layer, and the etching silicon wafer substrate, forming a TSV deep hole that the degree of depth is 500000A～600000A, SPM cleans, and removes the photoresist on surface, uses the BOE etching liquid, removes the silicon dioxide layer of silicon chip surface; (3) form the silicon dioxide insulating layer of 150A thickness at Si sheet surface deposition; (4) copper seed layer of the tantalum nitride barrier layer of deposit 150A, and deposit 150A; (5) at the silicon chip surface resist coating, exposure and photoetching form the window that needs electro-coppering; (6) at silicon chip surface electro-coppering 600000A～700000A, use SPM to clean and remove photoresist; (7) cmp, the silicon dioxide insulating layer that is ground to silicon chip is surperficial; (8) use the silicon slide glass to be bonded in the silicon chip surface that had ground; (9) silicon chip back side carries out cmp, exposes to the base copper surface in TSV hole; (10) at the silicon dioxide insulating layer of silicon chip back side deposit 150A, resist coating, exposure, develop, expose and need the TSV of barrier layer hole bottom, use the BOE etching liquid, etch away the silicon dioxide layer of the 150A in the hole, the tantalum nitride barrier layer of deposit 150A, the then copper seed layer of deposit 150A; (11) at the silicon chip back side resist coating, exposure is also developed, and exposes the window of electro-coppering; (12) at the copper of the whole back side plating of silicon chip 15000A, use SPM to clean, remove photoresist; (13) carry out scribing in the scribing road of silicon chip surface, form little tube core; (14) back side alignment keys of little tube core is combined in the surface of another sheet silicon chip; (15) to the silicon chip surface that is bonded through the row scribing, remove unwanted part; (16) the slide glass bonding of releasing die surfaces removes slide glass.
The present invention is further described below in conjunction with drawings and Examples.
The three-dimensional integrated technique flow process of low-cost TSV proposed by the invention, specifically as shown in Figure 2.This technology is directly made Seed Layer and the electroplates in hole after the through-hole side wall insulation, saved TSV via bottoms insulating barrier removing step in the traditional process.When subsequent wafer attenuate chemical machinery technique, utilize chemical mechanical method to remove the insulating barrier of via bottoms.The method technological process is short, simple, has solved the special equipment of the large depth-to-width ratio TSV through-hole side wall of conventional process flow and the special use of bottom gluing, photoetching, insulating barrier etching costliness, and process costs is low, the problem that efficient is high.
Now in conjunction with the embodiments, the invention will be further described for Fig. 4:
Embodiment 1:
1. adopt the substrate of Cz silicon (100) (0.1 ~ 0.2 Ω cm); Use LPCVD deposit silica 1 500A, at silicon chip surface resist coating 10000A, exposure is developed, and exposes the silica surface that width is 200000A
2. etching silicon dioxide, to surface of silicon, and continuing the etch silicon substrate, to form the degree of depth be the TSV hole of 500000A;
3.SPM clean the photoresist of removing the surface, adopt LPCVD deposit silica insulation film 150A;
4. adopt ion sputtering growth barrier layer tantalum nitride 150A, and Seed Layer copper 150A;
5. again at silicon chip surface resist coating 10000A, exposure is developed, and exposes the window that needs electro-coppering;
6. at silicon chip surface electro-coppering 600000A, and use SPM to clean and remove photoresist;
7. the employing cmp is ground to the soi layer surface;
8. use silicon slide glass ephemeral key to be combined in silicon chip surface;
9. the silicon chip back side cmp exposes to the copper surface of bottom, TSV hole;
10. use the insulating barrier silicon dioxide of LPCVD growth 150A, gluing 10000A, exposure is also developed, and exposing needs bottom, the TSV of barrier layer hole; Use the BOE etching liquid, etch away the silicon dioxide layer of the 150A this hole in, adopt the barrier layer tantalum nitride of ion sputtering generation 150A, then at the Seed Layer copper of deposit 150A;
11. at silicon chip back side resist coating 10000A, the window that needs electro-coppering is exposed in exposure and development;
12. at silicon chip back side electro-coppering 15000A, use SPM to clean and remove photoresist;
13. the scribing road section by silicon face forms little tube core;
14. with little tube core and need TSV hole copper post bonding between the silicon chip surface of bonding;
15. the silicon chip surface scribing is removed the part that does not need bonding and connection;
16. the releasing bonding removes interim slide glass.
Embodiment 2:
1. adopt the substrate of Cz silicon (100) (0.1 ~ 0.2 Ω cm); Use LPCVD deposit silica 1 500A, at silicon chip surface resist coating 10000A, exposure is developed, and exposes the silica surface that width is 250000A
2. etching silicon dioxide, to surface of silicon, and continuing the etch silicon substrate, to form the degree of depth be the TSV hole of 550000A;
3.SPM clean the photoresist of removing the surface, adopt LPCVD deposit silica insulation film 150A;
4. adopt ion sputtering growth barrier layer tantalum nitride 150A, and Seed Layer copper 150A;
5. again at silicon chip surface resist coating 10000A, exposure is developed, and exposes the window that needs electro-coppering;
6. at silicon chip surface electro-coppering 650000A, and use SPM to clean and remove photoresist;
7. the employing cmp is ground to the soi layer surface;
8. use silicon slide glass ephemeral key to be combined in silicon chip surface;
9. the silicon chip back side cmp exposes to the copper surface of bottom, TSV hole;
10. use the insulating barrier silicon dioxide of LPCVD growth 150A, gluing 10000A, exposure is also developed, and exposing needs bottom, the TSV of barrier layer hole; Use the BOE etching liquid, etch away the silicon dioxide layer of the 150A this hole in, adopt the barrier layer tantalum nitride of ion sputtering generation 150A, then at the Seed Layer copper of deposit 150A;
11. at silicon chip back side resist coating 10000A, the window that needs electro-coppering is exposed in exposure and development;
12. at silicon chip back side electro-coppering 15000A, use SPM to clean and remove photoresist;
13. the scribing road section by silicon face forms little tube core;
14. with little tube core and need TSV hole copper post bonding between the silicon chip surface of bonding;
15. the silicon chip surface scribing is removed the part that does not need bonding and connection;
16. the releasing bonding removes interim slide glass.
Embodiment 3:
1. adopt the substrate of Cz silicon (100) (0.1 ~ 0.2 Ω cm); Use LPCVD deposit silica 1 500A, at silicon chip surface resist coating 10000A, exposure is developed, and exposes the silica surface that width is 300000A
2. etching silicon dioxide, to surface of silicon, and continuing the etch silicon substrate, to form the degree of depth be the TSV hole of 600000A;
3.SPM clean the photoresist of removing the surface, adopt LPCVD deposit silica insulation film 150A;
4. adopt ion sputtering growth barrier layer tantalum nitride 150A, and Seed Layer copper 150A;
5. again at silicon chip surface resist coating 10000A, exposure is developed, and exposes the window that needs electro-coppering;
6. at silicon chip surface electro-coppering 700000A, and use SPM to clean and remove photoresist;
7. the employing cmp is ground to the soi layer surface;
8. use silicon slide glass ephemeral key to be combined in silicon chip surface;
9. the silicon chip back side cmp exposes to the copper surface of bottom, TSV hole;
10. use the insulating barrier silicon dioxide of LPCVD growth 150A, gluing 10000A, exposure is also developed, and exposing needs bottom, the TSV of barrier layer hole; Use the BOE etching liquid, etch away the silicon dioxide layer of the 150A this hole in, adopt the barrier layer tantalum nitride of ion sputtering generation 150A, then at the Seed Layer copper of deposit 150A;
11. at silicon chip back side resist coating 10000A, the window that needs electro-coppering is exposed in exposure and development;
12. at silicon chip back side electro-coppering 15000A, use SPM to clean and remove photoresist;
13. the scribing road section by silicon face forms little tube core;
14. with little tube core and need TSV hole copper post bonding between the silicon chip surface of bonding;
15. the silicon chip surface scribing is removed the part that does not need bonding and connection;
16. the releasing bonding removes interim slide glass.
Claims (1)
1. the three-dimensional integrated technology process of low-cost TSV is characterized in that comprising the steps:
(1) at the silicon dioxide of silicon chip surface deposit 1500A thickness, at the silica surface resist coating, and exposure imaging, exposing needs the silicon dioxide of etching window;
(2) at window etching silicon dioxide layer, and the etching silicon wafer substrate, forming a TSV deep hole that the degree of depth is 500000A～600000A, SPM cleans, and removes the photoresist on surface, uses the BOE etching liquid, removes the silicon dioxide layer of silicon chip surface;
(3) form the silicon dioxide insulating layer of 150A thickness at Si sheet surface deposition;
(4) tantalum nitride barrier layer of deposit 150A, the copper seed layer of deposit 150A;
(5) at the silicon chip surface resist coating, exposure and photoetching form the window that needs electro-coppering;
(6) at silicon chip surface electro-coppering 600000A～700000A, use SPM to clean and remove photoresist;
(7) cmp, the silicon dioxide insulating layer that is ground to silicon chip is surperficial;
(8) use the silicon slide glass to be bonded in the silicon chip surface that had ground;
(9) silicon chip back side carries out cmp, exposes to the base copper surface in TSV hole;
(10) at the silicon dioxide insulating layer of silicon chip back side deposit 150A, resist coating, exposure, develop, expose and need the TSV of barrier layer hole bottom, use the BOE etching liquid, etch away the silicon dioxide layer of the 150A in the hole, the tantalum nitride barrier layer of deposit 150A, the then copper seed layer of deposit 150A;
(11) at the silicon chip back side resist coating, exposure is also developed, and exposes the window of electro-coppering;
(12) at the copper of the whole back side plating of silicon chip 15000A, use SPM to clean, remove photoresist;
(13) carry out scribing in the scribing road of silicon chip surface, form tube core;
(14) back side alignment keys of tube core is combined in the surface of another sheet silicon chip;
(15) silicon chip surface that is bonded is carried out scribing, remove unwanted part;
(16) the slide glass bonding of releasing die surfaces removes slide glass.
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| CN103700621A (en) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Method for etching vertical glass through holes with high depth-to-width ratios |
| CN105070683A (en) * | 2015-08-07 | 2015-11-18 | 深圳先进技术研究院 | Bottom windowing manufacturing method for insulating layer of silicon perforated structure and silicon perforated structure |
| CN105097659A (en) * | 2014-05-16 | 2015-11-25 | 中国科学院苏州纳米技术与纳米仿生研究所 | Indium interconnection mechanism and preparation method thereof, focal plane apparatus and packaging method thereof |
| CN105529299A (en) * | 2015-09-14 | 2016-04-27 | 上海交通大学 | Method for electroplating filling of TSV adapter plate |
| CN105679703A (en) * | 2016-03-23 | 2016-06-15 | 中国科学院微电子研究所 | Silicon through hole structure-based metal filling method and silicon through hole structure |
| CN106252276A (en) * | 2016-08-08 | 2016-12-21 | 中国电子科技集团公司第五十四研究所 | Manufacture method based on TSV technology switch matrix radio frequency unit |
| CN107910248A (en) * | 2017-11-14 | 2018-04-13 | 武汉新芯集成电路制造有限公司 | A kind of method for improving the brilliant back of the body defect of bonding wafer |
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| CN102412195A (en) * | 2011-08-08 | 2012-04-11 | 上海华虹Nec电子有限公司 | Through silicon via (TSV) filling method |
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| CN103700621A (en) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Method for etching vertical glass through holes with high depth-to-width ratios |
| CN105097659A (en) * | 2014-05-16 | 2015-11-25 | 中国科学院苏州纳米技术与纳米仿生研究所 | Indium interconnection mechanism and preparation method thereof, focal plane apparatus and packaging method thereof |
| CN105097659B (en) * | 2014-05-16 | 2018-03-20 | 中国科学院苏州纳米技术与纳米仿生研究所 | Indium interconnection mechanism and preparation method thereof, focal plane device and its method for packing |
| CN105070683A (en) * | 2015-08-07 | 2015-11-18 | 深圳先进技术研究院 | Bottom windowing manufacturing method for insulating layer of silicon perforated structure and silicon perforated structure |
| CN105070683B (en) * | 2015-08-07 | 2018-02-27 | 深圳市化讯半导体材料有限公司 | The insulating barrier bottom windowing manufacture method and silicon perforation structure of a kind of silicon perforation structure |
| CN105529299A (en) * | 2015-09-14 | 2016-04-27 | 上海交通大学 | Method for electroplating filling of TSV adapter plate |
| CN105529299B (en) * | 2015-09-14 | 2019-03-22 | 上海交通大学 | A method of plating filling silicon substrate TSV pinboard |
| CN105679703A (en) * | 2016-03-23 | 2016-06-15 | 中国科学院微电子研究所 | Silicon through hole structure-based metal filling method and silicon through hole structure |
| CN106252276A (en) * | 2016-08-08 | 2016-12-21 | 中国电子科技集团公司第五十四研究所 | Manufacture method based on TSV technology switch matrix radio frequency unit |
| CN106252276B (en) * | 2016-08-08 | 2019-01-15 | 中国电子科技集团公司第五十四研究所 | Manufacturing method based on TSV technology switch matrix radio frequency unit |
| CN107910248A (en) * | 2017-11-14 | 2018-04-13 | 武汉新芯集成电路制造有限公司 | A kind of method for improving the brilliant back of the body defect of bonding wafer |
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Application publication date: 20130130 |