CN102903613A - 消除接触孔工艺中桥接的方法 - Google Patents
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Abstract
一种消除了接触孔工艺中桥接的方法,提供了包括多步适应性保护薄膜沉积工艺的清洁菜单,在HDP CVD设备腔室的侧壁上形成叠层适应性保护薄膜,叠层适应性保护薄膜具有良好的粘附性、致密性和均匀性,可以保护HDP CVD设备腔室的侧壁,使其不会受到等离子体的伤害,还避免了缺陷颗粒的产生,提高了HDP CVD工艺的技术良率,消除了接触孔工艺中的桥接现象。
Description
技术领域
本发明涉及半导体集成电路制造领域,特别地,涉及一种消除接触孔工艺中桥接(contact bridge)的方法。
背景技术
半导体集成电路以摩尔定律所预测的时间表向前推进,器件的特征尺寸向小尺寸结构发展,集成度不断提高。随着特征尺寸的不断细微化,单个芯片的集成度已高达108~109,而与此同时,对生产工艺的要求也越来越高,因此,在制造工艺中减少缺陷的尺寸和密度就变得非常关键。在尺寸100微米的晶体管上面有一个1微米的灰尘可能不是问题,但是对于一个1微米的晶体管来说会是一个导致器件失效的致命缺陷,所以特别是对化学气相淀积(CVD)薄膜制程提出了更高的要求。相同的淀积薄膜工艺下同样尺寸的10个缺陷,对90nm产品良率的影响不到2%,可是对65nm产品良率的影响却大于30%以上。
在目前的CVD制程中,由高密度等离子体化学气相淀积(HDPCVD)制程所带来的缺陷问题是最严重的,例如浅沟槽隔离(STI)介质的HDP CVD制程、作为层间介质层(ILD)的磷硅玻璃(PSG)的HDP CVD制程等。其中,作为ILD的PSG的HDP CVD工艺如果控制不好将会产生块状缺陷,引起后续制程的桥接,即:ContactBridge,造成产品失效,具体参见附图1-4。
附图1显示了具有ILD的典型的CMOS结构。衬底10上具有N阱11和P阱12,STI结构13将N阱11和P阱12隔离。NMOS和PMOS的源漏极22,栅极21。由HDP CVD形成的ILD14覆盖在应变SiN包裹的NMOS和PMOS之上,ILD14中存在缺陷15,缺陷15例如工艺过程中难以预期的玷污颗粒。在形成ILD14之后,经过清洗、化学机械抛光(CMP),缺陷15被除去,但是,在ILD14中留下了孔洞16,参见附图2。然后,参见附图3,通过ILD14,形成多个接触孔17,以引出电极。接着,参见附图4,进行导电材料填充,例如是Ti/TiN,在接触孔17中形成接触插塞19,但同时在孔洞16中也留下了部分导电材料,从而形成了桥接部件18。由于桥接部件18的存储,多个接触插塞17被桥接而短路,造成了电路失效。
因此,根据目前半导体制造流程对HDP CVD技术良率提升提出的进一步需求,需要开发一种消除接触孔工艺中桥接(contact bridge)的方法,以减少HDP CVD工艺沉积过程中产生的缺陷而避免电路失效。
发明内容
本发明提供一种消除接触孔工艺中桥接的方法,其中,包括:
对高密度等离子体化学气相淀积设备的反应腔室进行清洁,该清洁工艺包括设定清洁菜单,在上述清洁菜单中,在去除反应腔室的腔壁生长的SiO2薄膜后,设置多步的适应性保护薄膜沉积工艺,用以在所述腔壁上形成叠层适应性保护薄膜,该叠层适应性保护薄膜保护所述腔壁,使所述腔壁在高密度等离子体化学气相淀积工艺中不会受到等离子体的损伤。
在本发明的方法中,所述适应性保护薄膜的材料为SiO2、Si3N4、SiON中的一种或多种。
在本发明的方法中,所述叠层适应性保护薄膜为SiO2、Si3N4、SiON薄膜中的一种或多种形成的叠层;优选地,叠层适应性保护薄膜为多层SiO2形成的叠层;更优选地,叠层适应性保护薄膜为多层富硅SiO2形成的叠层,富硅SiO2的折射率大于1.5,或者,叠层适应性保护薄膜为多层富氧SiO2形成的叠层,富氧SiO2的折射率小于1.5;其中,在多步的适应性保护薄膜形成工艺中,交替改变薄膜沉积的SiH4和O2气体流量的比值,以获得不同折射率组分的薄膜覆盖,提高适应性保护薄膜的致密性。
在本发明的方法中,在多步的适应性保护薄膜形成工艺中,交替改变薄膜沉积的射频功率的参数,以提高适应性保护薄膜的均匀性和致密性;优选地,改变的射频功率参数包括改变等离子体分布浓度和方向。
在本发明的方法中,还包括在沉积一层或任意多层适应性保护薄膜后,在腔体保养维护时对所述腔室的侧壁进行增加粗糙度的擦刮,改善表面性能,提高适应性保护薄膜的粘附性。
本发明包括多步适应性保护薄膜沉积工艺的清洁菜单,在HDPCVD设备腔室的侧壁上形成叠层适应性保护薄膜,叠层适应性保护薄膜具有良好的粘附性、致密性和均匀性,可以保护HDP CVD设备腔室的侧壁,使其不会受到等离子体的伤害,还避免了缺陷颗粒的产生,提高了HDP CVD工艺的技术良率,消除了接触孔工艺中的桥接现象。
附图说明
图1-4桥接现象示意图;
图5-6缺陷产生原因示意图;
图7本发明提供的叠层保护层;
图8本发明提供的经过打磨的叠层保护层;
图9-10本发明提供的无桥接的半导体器件。
具体实施方式
以下,通过附图中示出的具体实施例来描述本发明。但是应该理解,这些描述只是示例性的,而并非要限制本发明的范围。此外,在以下说明中,省略了对公知结构和技术的描述,以避免不必要地混淆本发明的概念。
本发明的实施例涉及使用高密度等离子体化学气相淀积(HDPCVD)方法进行电介质薄膜沉积后的干法清洁工艺,以实现沉积的晶圆表面完美的颗粒需求,从而提高了HDP CVD工艺的技术良率,消除了接触孔工艺中的桥接现象。
根据本发明,参见附图9,首先提供半导体衬底10,半导体衬底10上具有N阱11和P阱12,隔离结构13,例如是STI结构,将N阱11和P阱12隔离。在阱区中形成NMOS和PMOS的源漏极22,在衬底10之上形成栅极21。之后,采用应变SiN保形地覆盖NMOS和PMOS。接着,采用HDP CVD工艺,在应变SiN之上形成层间介质层(ILD)14,覆盖NMOS和PMOS区域。接着,形成多个接触孔17,接触孔17穿过ILD14,以便引出源漏电极以及栅电极。
相对传统的等离子体增强化学气相沉积(PECVD)技术而言,HDP CVD沉积技术可以在较低的压力下,采用电感耦合的方式产生高密度等离子体(ICP),或采用电子回旋共振方式产生高密度等离子体(ECR),也可以采用其他方法产生高密度等离子体,如表面波,哨声波等方式。PECVD沉积方式具有108~1010的密度(n/cm3)的等离子体,而如果采用HDP CVD沉积方式可以达到1011~1012甚至量级更高的高密度(n/cm3)等离子体。由于HDP CVD是一种沉积与溅射(刻蚀)同步进行的工艺,高密度的等离子体对反应腔室也有一定的轰击作用。参见附图5,反应腔室的侧壁1上形成有一层薄膜2’,薄膜2’是进行HDP CVD工艺时形成的,然而,通常情况下,经过长时间等离子体的轰击导致腔体的表面性能下降,另外薄膜2’的致密性和均匀性不佳,等离子3轰击薄膜2’的表面,可能会将例如是颗粒状的缺陷3从薄膜2’中击出(参见附图6),并使其落在ILD14层中,产生如图1所示的情况。为了减少缺陷的产生,提高半导体器件良率,在制备所需薄膜时,例如是本实施例中的IDL14,需要执行一个清洁工艺以消除可能产生缺陷的因素。
本发明消除接触孔工艺中桥接的方法中,包括了新开发的清洁工艺。在采用HDP CVD工艺制备所需薄膜时,例如是淀积ILD层,对高密度等离子体化学气相淀积设备的腔室进行清洁,该清洁工艺包括设定清洁菜单,在上述清洁菜单中,设置多步的适应性保护薄膜沉积工艺,用以在所述腔室的侧壁上形成叠层适应性保护薄膜2,参见附图7,该叠层适应性保护薄膜2保护所述腔室的侧壁,使所述腔室的侧壁在高密度等离子体化学气相淀积工艺中不会受到等离子体的损伤。
通常,在工厂生产或实验室实验的时候,先对一批控片(dummywafer)进行流片,使HDP CVD反应发生的腔体逐渐进入稳定状态,而后进行大规模晶圆流片生产或实验。在本发明中的情节工艺中,通过执行清洁菜单中的适应性保护薄膜沉积(又称为流程中薄膜沉积,即season薄膜沉积)工艺,将适应性保护薄膜沉积在腔壁上,保护腔壁并且为下一片或下一批的晶圆的生长保持一个稳定的反应环境。
在本发明的方法中,所述适应性保护薄膜的材料为SiO2、Si3N4、SiON中的一种或多种。具体采用何种材料,还要根据ILD层而定,适应性保护薄膜的材料是与ILD材料相同的。因此,叠层适应性保护薄膜2为SiO2、Si3N4、SiON薄膜中的一种或多种形成的叠层;优选地,当ILD14为SiO2层时,叠层适应性保护薄膜2为多层SiO2形成的叠层;更优选地,叠层适应性保护薄膜2为多层富硅SiO2形成的叠层,富硅SiO2的折射率大于1.5,或者,叠层适应性保护薄膜2为多层富氧SiO2形成的叠层,富氧SiO2的折射率小于1.5。其中,在多步的适应性保护薄膜2形成工艺中,交替改变薄膜沉积的SiH4和O2气体流量的比值,以获得不同折射率组分的薄膜覆盖,提高适应性保护薄膜的致密性。
在本发明的方法中,在多步的适应性保护薄膜2形成工艺中,交替改变HDP CVD薄膜沉积的射频(RF)功率的参数,以提高适应性保护薄膜2的粘附性、均匀性和致密性;优选地,改变的射频功率参数包括改变等离子体分布浓度和方向。
在本发明的方法中,还包括在沉积一层或任意多层适应性保护薄膜2后,在腔体保养维护时对所述腔室的侧壁进行增加粗糙度的擦刮,改善表面性能,提高适应性保护薄膜的粘附性。参见附图8,擦刮后的薄膜具有粗糙的表面5,可以提供良好的附着能力,提高整个叠层适应性保护薄膜2的粘附性,使其不容易被等离子体轰击而脱落,从而进一步降低了缺陷产生的可能。
由于执行了本发明的清洁工艺,ILD14表面不会产生缺陷,从而,消除了在后续接触孔填充工艺可能产生的桥接现象。接着,参见附图10,进行导电材料填充,例如是Ti/TiN,在接触孔17中形成接触插塞19。此时,半导体器件中不存在如附图4所示的桥接部件18,因而电路功能得到保证,集成电路的良率提高。
在本发明中,提供了包括多步适应性保护薄膜沉积工艺的清洁菜单,在HDP CVD设备腔室的侧壁上形成叠层适应性保护薄膜,叠层适应性保护薄膜具有良好的致密性和均匀性,可以保护HDP CVD设备腔室的侧壁,使其不会受到等离子体的伤害,避免了缺陷颗粒的产生,提高了HDP CVD工艺的技术良率,消除了接触孔工艺中的桥接现象。
以上参照本发明的实施例对本发明予以了说明。但是,这些实施例仅仅是为了说明的目的,而并非为了限制本发明的范围。本发明的范围由所附权利要求及其等价物限定。不脱离本发明的范围,本领域技术人员可以做出多种替换和修改,这些替换和修改都应落在本发明的范围之内。
Claims (10)
1.一种消除接触孔工艺中桥接的方法,其特征在于,包括:
对高密度等离子体化学气相淀积设备的腔室进行清洁,该清洁工艺包括设定清洁菜单,在上述清洁菜单中,设置多步的适应性保护薄膜沉积工艺,用以在所述腔室的侧壁上形成叠层适应性保护薄膜,该叠层适应性保护薄膜保护所述腔室的侧壁,使所述腔室的侧壁在高密度等离子体化学气相淀积工艺中不会受到等离子体的损伤。
2.根据权利要求1所述的方法,其特征在于,所述适应性保护薄膜的材料为SiO2、Si3N4、SiON中的一种或多种。
3.根据权利要求1所述的方法,其特征在于,所述叠层适应性保护薄膜为SiO2、Si3N4、SiON薄膜中的一种或多种形成的叠层。
4.根据权利要求3所述的方法,其特征在于,所述叠层适应性保护薄膜为多层SiO2形成的叠层。
5.根据权利要求4所述的方法,其特征在于,所述叠层适应性保护薄膜为多层富硅SiO2形成的叠层,富硅SiO2的折射率大于1.5。
6.根据权利要求4所述的方法,其特征在于,所述叠层适应性保护薄膜为多层富氧SiO2形成的叠层,富氧SiO2的折射率小于1.5。
7.根据权利要求4至6之一所述的方法,其特征在于,在多步的适应性保护薄膜形成工艺中,交替改变薄膜沉积的SiH4和O2气体流量的比值,以获得不同折射率组分的薄膜覆盖,提高适应性保护薄膜的致密性。
8.根据权利要求1所述的方法,其特征在于,在多步的适应性保护薄膜形成工艺中,交替改变薄膜沉积的射频功率的参数,以提高适应性保护薄膜的均匀性和致密性。
9.根据权利要求8所述的方法,其特征在于,改变的射频功率参数包括改变等离子体分布浓度和方向。
10.根据权利要求1所述的方法,其特征在于,还包括在沉积一层或任意多层适应性保护薄膜后,在腔体保养维护时对所述腔室的侧壁进行增加粗糙度的擦刮,改善表面性能,提高适应性保护薄膜的粘附性。
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