CN102902834B - A kind of verification method of SOC and system - Google Patents
A kind of verification method of SOC and system Download PDFInfo
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- CN102902834B CN102902834B CN201110217229.7A CN201110217229A CN102902834B CN 102902834 B CN102902834 B CN 102902834B CN 201110217229 A CN201110217229 A CN 201110217229A CN 102902834 B CN102902834 B CN 102902834B
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Abstract
The present invention is applicable to chip technology field, embodiments provides a kind of verification method of SOC, and described method comprises the steps: to load test procedure; In system interface function library, corresponding system function is called according to described test procedure, according to described system function, and the maintenance list that described system function is corresponding, generate random affairs; According to described random affairs, treat test chip and verify.The test procedure that the invention enables software engineer to write can directly run on existing verification platform, achieves software-hardware co-designing, low level information is encapsulated simultaneously, makes verification system easy to use, and be easy to multiplexing.
Description
Technical field
The invention belongs to chip technology field, particularly relate to a kind of verification method and system of SOC.
Background technology
After chip design completes, needs are verified, the main task of checking is the correctness of checking design, determines whether chip meets all design specificationss.
Traditional verification method is direct vector test (directvectortest), direct vector test is the checking of a kind of signal level, directly communicated with chip to be verified on signal level by the excitation manufacturing fixed scene, carried out the function of proofing chip by the value and change checking chip pin signal.This verification method requires the operative scenario must designing chip in advance, and checking personnel directly process the signal level information of very low level.Adopt this verification method, checking person works amount is very large, and some unexpected scenes, error handle scene can not be considered one by one and authenticate to, and causes checking not comprehensive.When chip more complicated, scale are larger, the verification method of direct vector test does not verify ability substantially.Owing to being the checking of signal level, verification platform is directly relevant to the interface protocol of chip, and verification platform reusability is very poor, and when chip is regenerated, original verification platform cannot be reused substantially, must again build new verification platform.
In order to overcome the shortcoming of traditional verification method, the development trend of chip checking improves abstraction hierarchy, carries out the checking of transaction-level.
Representational transaction-level (transactionlevel) verification method is verification method handbook (VerificationMethodologyManual, VMM).The framework of VMM verification system as shown in Figure 1, retrains generator by the constraint condition in checking personnel operative configuration device and produces test affairs, and achieve on-line automatic comparison by automatic comparer.
After adopting VMM verification method, constrained random checking (constrainedrandomverification) can be realized, carry out random under the constraint condition of setting, to cover normal operative scenario and unexpected operative scenario; Coverage-Driven checking (coveragedrivenverification), when function coverage, code coverage reach desired value and stop accidental validation later; Automatically compare online, run into wrong automatic alarm and stop emulation, saving scene; Based on the checking of asserting (assertionbasedverification).
VMM verification method achieves verification method from signal level to the transformation of transaction-level, facilitates the checking of data path type chip.But due to data interaction and the control more complicated of VMM verification method, concerning multimedia chip, the method operating chip to be verified is quite complicated, inconvenient control imitation flow process, ease for use is low, and because it cannot add device drives, therefore complicated application scenarios cannot be verified and escalate into whole-system verification.
Summary of the invention
The object of the embodiment of the present invention is the verification method providing a kind of SOC, be intended to solve prior art for existing verification platform, verification operation is complicated, and cannot verify complicated application scenarios, cannot realize the problem of software-hardware co-designing in analogue system.
The embodiment of the present invention is achieved in that a kind of verification method of SOC, and described method comprises the steps:
Load test procedure;
In system interface function library, corresponding system function is called according to described test procedure, according to described system function, and the maintenance list that described system function is corresponding, generate random affairs;
According to described random affairs, treat test chip and verify.
The embodiment of the present invention additionally provides a kind of verification system of SOC, and described system comprises:
Loader, for loading test procedure;
Random affairs generator, calls corresponding system function for the test procedure loaded according to described loader in system interface function library, according to described system function, and the maintenance list that described system function is corresponding, generate random affairs;
Authentication unit, for the random affairs produced according to described random affairs generator, treats test chip and verifies.
The embodiment of the present invention calls corresponding system function by the test procedure loaded in system interface function library, according to system function, and the maintenance list that system function is corresponding, generate random affairs, according to random affairs, treat test chip and verify.The test procedure that software engineer is write can directly run on existing verification platform, verification method is promoted to whole-system verification, achieve software-hardware co-designing, achieve the checking of complex application context, simultaneously by low level information is encapsulated, make verification system easy to use, and be easy to multiplexing.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the VMM verification platform of prior art provided by the invention;
Fig. 2 is the realization flow figure of the verification method of the SOC that the embodiment of the present invention one provides.
Fig. 3 is the process flow diagram of the test program development that the embodiment of the present invention one provides;
Fig. 4 is the realization flow figure of the method for the random affairs of generation that the embodiment of the present invention two provides;
Fig. 5 is the realization flow figure of the realization example of the generation test affairs that the embodiment of the present invention two provides;
Fig. 6 is the realization flow figure of the method for the random affairs of generation that the embodiment of the present invention three provides;
Fig. 7 is the realization flow figure of the realization example of the generation I/O operation affairs that the embodiment of the present invention three provides;
Fig. 8 is the realization flow figure of the method for the random affairs of generation that the embodiment of the present invention four provides;
Fig. 9 is the realization flow figure of the generation random number that provides of the embodiment of the present invention four or random series realization example;
Figure 10 is the checking structural drawing of the SOC that the embodiment of the present invention five provides;
Figure 11 is the checking structural drawing of the SOC that the embodiment of the present invention six provides;
Figure 12 is the checking structural drawing of the SOC that the embodiment of the present invention seven provides;
Figure 13 is the structural drawing of the random device configuration operation unit that the embodiment of the present invention seven provides;
Figure 14 is the structural drawing of the random I/O operation unit that the embodiment of the present invention seven provides;
Figure 15 is the structural drawing of the random series operating unit that the embodiment of the present invention seven provides;
Figure 16 is the process flow diagram of the proof procedure of the SOC that the embodiment of the present invention eight provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The embodiment of the present invention calls corresponding system function by the test procedure of above-mentioned loading in system interface function library, according to said system function, and the maintenance list that said system function is corresponding, generate random affairs, according to above-mentioned random affairs, treat test chip and verify.
Technical scheme of the present invention for convenience of explanation, is described below by specific embodiment:
embodiment one
Fig. 2 shows the realization flow figure of the verification method of the SOC that the embodiment of the present invention one provides, and details are as follows:
In step s 201, test procedure is loaded.
In embodiments of the present invention, test procedure can realize following functions:
(1) flow process of verification system is controlled.
(2) obtain and change the state of verification system.
(3) operate, access chip to be measured.
(4) produce random test affairs and carry out test chip.
(5) the other standards C/C++ operation that can complete.
In embodiments of the present invention, test procedure can be driver or application program, such as, can comprise master routine and interrupt service routine etc., wherein,
1, interrupt service routine can be the function with following form:
Intisr (intpid, intsource, intport); All functions with above form, all to system registry, can become interrupt service routine.
2, the mode of the registration of interrupt service routine in main test procedure, can call with minor function:
intregister_isr(intpid，intport，isr_ptisr)；
Pid is wherein test component numbering, and port is interruptive port numbering, and isr is the function for registration.
The form of 3, interrupting can be divided into weaken rock and firmly interrupt, and the interruption sent by " hardware " i.e. tested device is called " firmly interrupting ", and test procedure also can send interruption to system, is called " weaken rock ".
Call lower array function and namely send weaken rock:
assert_irq(intpid，intsource_id，intport_id)
Wherein, pid is test component numbering, and source_id is interrupt source numbering, and for showing caller identity, port_id is then interruptive port numbering.
In embodiments of the present invention, test procedure can have multiple, test procedure can be the c/c++ program of standard, now, the c/c++ compiler of standard can be used, and test procedure can exist with the form in test procedure storehouse, such as, test procedure library file can be compiled into by gcc etc., the development process in test procedure storehouse can adopt development process as shown in Figure 3, on stream, according to c/c++ library file, development and testing master routine and interrupt service routine respectively, test master routine and interrupt service routine are compiled into file destination through gcc, all file destinations generate test procedure storehouse through packing.
In embodiments of the present invention, Direct Programming interface (DirectProgrammingInterface can be passed through, DPI) test procedure is loaded, by DPI interface, C/C++ program can call the function of EDA (Electronicdesignautomation) language domains, and EDA language domains also can call the function of C/C++ language domains, when test procedure comprises master routine and interrupt service routine, DPI interface also can have two accordingly, respectively corresponding master routine and interrupt service routine.
In step S202, in system interface function library, call corresponding system function according to test procedure, according to system function, and the maintenance list that system function is corresponding, generate random affairs.
In embodiments of the present invention, random affairs can comprise random test affairs, random I/O operation affairs and/or random series operation affairs.
In embodiments of the present invention, corresponding system function is called in system function storehouse, system function specifically can comprise control function, event functions, IO function, semaphore function, the combination in any shared in data function, thread function or randomized function, wherein:
(1) control function
Control function, for controlling the operation of verification system, as suspended emulation, continuing emulation, obtaining simulation time, obtain analogue system current state, change system state etc., specifically can adopt:
Sim_finish (); // terminate emulation
Sim_stop (); // suspend emulation
Doubleget_time (); // obtain current simulation time
(2) event functions
Event functions is synchronous for what test between thread, wherein, and the generation of event or synchronously can operate corresponding list of thing,
Intevent_create (); // create an event column list item, return Case Number
Voidevent_trigger (intevent_id); // trigger event, triggers usually after certain simulated conditions occurs
Voidevent_sync (intevent_id, intsync_type); // be synchronized to event, before event occurs, block thread
(3) semaphore function
Semaphore function, can the list of operation signal amount during operation signal amount for accessing shielded resource.
Intsemaphore_create (intkey_count); // creating a semaphore list item, return signal amount is numbered
Voidsemaphore_get (intsemaphore_id, intkey_count); // application semaphore, if not enough during signal, blocks until there are enough semaphores.Apply for before access resources.
Voidsemaphore_put (intsemaphore_id, intkey_count); // release semaphore, answers release semaphore to make other thread energy access resources after having accessed resource.
(3) IO function
IO function is used for the function of directly being accessed tested device by the port address of device, when supporting multithreading, also need between each I/O operation to carry out synchronously to guarantee that their execution sequence is correct, this order is ensured by I/O bank table, the I/O operation being in list head first completes, subsequent operation continue after, be below some IO function operation functions:
Voidio_write (intpid, intaddress, intop_size, intdata, intmask); // write device
Intio_read (intpid, intaddress, intop_size); // read device
Voidio_burst_write (intpid, intaddress, intop_size, intburst_type, int*data, int*mask); // write device in the mode of bursting out
Voidio_burst_read (intpid, intaddress, intop_size, intburst_type, int*data); // read device in the mode of bursting out
Voidio_random_transfer (intpid, intstart_address, intend_address, intop_size, intop, intburst_type, intntests); // random access is carried out to device
(4) data function is shared
When needs carry out data sharing between each thread of test procedure, shared data can be placed in general data list and use for each thread by shared data function.
Voidscfg_create_reg (char*reg_name, intinit_value); // create a list item
Voidscfg_set_reg (char*reg_name, intvalue); // a shared item is set
Intscfg_get_reg (char*reg_name); // read a shared item
Voidscfg_wait_reg (char*reg_name, intexp_value, intmask); // wait for until the value sharing item is designated value
Voidscfg_wait_reg_created (char*reg_name); // wait for until shared item is created
Voidscfg_wait_reg_write (char*reg_name); // wait for until the value sharing item is set up
Voidscfg_wait_reg_read (char*reg_name); // wait for until the value sharing item is read
Voidscfg_wait_reg_change (char*reg_name); // wait for until the value sharing item changes
Voidscfg_wait_reg_not (char*reg_name, intexp_value, intmask); // wait for until the value sharing item is not designated value
Voidscfg_wait_reg_less (char*reg_name, intexp_value); // wait for until the value sharing item is less than designated value
Voidscfg_wait_reg_larger (char*reg_name, intexp_value); // wait for until the value sharing item is greater than designated value
(5) thread function
Thread function for generation of multithreading, and can be carried out synchronous between thread, the operations such as cancellation, and thread list saves the current thread that performing and their state.
Intio_fork (int (* io_func) (), inttotal_args ...); // perform function in parallel thread mode, return thread number
Voidio_sync (intschedule_id); // synchronous, block until specify the thread execution of numbering complete
Voidio_fiush (intpid); // synchronous, block until the main device of specifying finishes all I/O operation
Voidio_nop (intpid); // wait a upper I/O operation of main device to be specified to complete
Voiddelay_t (doubledelay_time); // current thread blocks one section of simulation time
Voiddelay_clock (intpid, intclock_cycles); // current thread blocks a clock cycle
Voidsim_pause (intpause_id); // current thread is suspended
Voidsim_resume (intpause_id); // continue to perform the thread be suspended
(6) randomized function
Randomized function is used for the configuration of randomization tested device, when performing randomized function, on the one hand random function produces a random series and stored in stochastic ordering list, inquiry tested device configured list on the one hand, find corresponding tested device and the tested device of correspondence configuration loading is come in, random constraints is wherein described for generation of random affairs.
Intrandc (intmax, intmin); // from scope [min, max], obtain unduplicated random integers
Intrandc_array (int*ResultArray, intArraySize, intmax, intmin); // from scope [min, max], obtain ArraySize unduplicated random integers
Intrandcase (weight_0 ...); // from subsequent branches, to get a branch at random perform, the weight of branch is respectively weight_0, weight_1 ... weight_N.
Voidcfg_rand_regs (intpid, char*cfg_name ...); // randomization tested device register is to obtain random arrangement value
Voidcfg_set_rand_mask (intpid, char*cfg_name, char*reg_name, intrand_mask); // for tested device register arranges random mask, guarantee not need randomized register to keep original value
Voidcfg_flush_regs (intpid, char*cfg_name, char*reg_name...); // register value good is at random write tested device (DUT) by system bus
In embodiments of the present invention, safeguard that list can comprise multiple different list, being specially different system functions can carry out corresponding from different lists, such as, the corresponding list of thing of event functions, the corresponding I/O bank table of IO function, the list of semaphore function respective signal amount, share the corresponding general data list of data function, the corresponding thread list of thread function, the corresponding stochastic ordering list of randomized function and tested device configured list.
1. list of thing (eventtable)
List of thing represents that the event when meeting certain condition there occurs, and carries out notice with synchronous in analogue system.When the somewhere of analogue system there occurs certain event, just can state event and event is put into list of thing, other place of analogue system just can with this event for trigger condition performs handling procedure.Each thread is by event functions Action Events.
2.IO list (IOtable)
Test procedure test tested device is realized by the register of accessing tested device possibly, these operations are in chronological sequence sequentially safeguarded by I/O bank table, realize I/O operation synchronous, ensure the legitimacy of operation, also test procedure is carried out synchronous simultaneously.
Test procedure can visit tested device by IO function.
3. semaphore list (semaphoretable)
When multiple thread needs to access same resource, need the alternative ensureing access.Semaphore (semaphore) is exactly a kind of method ensureing alternative.Often kind of resource several semaphores corresponding; Need first to file semaphore during thread accesses resource, if semaphore is not enough, then thread gets clogged, and just unblocks, have access to resource until obtain enough semaphores, and last release semaphore is to make other thread energy access resources.Each thread is by semaphore function operation semaphore.
4. general data list (universaldatatable)
General data list saves the data of general-use, and can share for each thread of analogue system, each thread is by shared data function accessing universal.
5. thread list (scheduledthreadtable)
Test procedure can operate thread by thread function, test procedure can cause many sub-threads simultaneously performed, this a little thread is safeguarded by thread list, to ensure that the execution sequence of thread meets expection, also be controllable simultaneously, such as, can complete at other thread waits threads, kill certain thread, cause sub-thread etc.
6. stochastic ordering list (randomsequencetable)
Stochastic ordering list is for safeguarding random series, and make random series production process be transparent concerning test procedure, programmer need not be concerned about concrete implementation procedure, and test procedure can obtain random series by randomized function.
7. tested device configured list (deviceundertestconfigurationtable),
Tested device configured list saves the inventory of all tested device configuration files (deviceundertestconfiguration, dut_cfg) of current system.The corresponding tested device of each dut_cfg file.When operating device under test, from tested device configured list, searching corresponding tested device and the tested device of correspondence is configured to produce random test affairs.
In step s 103, according to above-mentioned random affairs, treat test chip and verify.
The embodiment of the present invention calls corresponding system function by the test procedure of above-mentioned loading in system interface function library, according to said system function, and the maintenance list that said system function is corresponding, generate random affairs, according to above-mentioned random affairs, treat test chip to verify, the test procedure that software engineer is write can directly run on existing verification platform, achieve software-hardware co-designing, simultaneously by low level information is encapsulated, make verification system easy to use, and be easy to multiplexing.
embodiment two
Fig. 4 show that the invention process two provides when random affairs are random test affairs, according to system function, and the maintenance list that system function is corresponding, generate the process flow diagram of the realization of the method for random affairs, details are as follows:
In step S401, in tested device configured list, search the tested device corresponding with above-mentioned tested device and configure.
In embodiments of the present invention, each tested device has a tested device configuration, tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, above-mentioned register image specifically comprises the title of register, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values, above-mentioned constraint expression formula limits the scope of the stray parameter of tested device, is specially:
1, the register image of device under test, comprises the title of register, address, bit wide, default value, a front Configuration Values, current Configuration Values etc.
2, the constraint expression formula of tested device, constraint expression formula limits the scope of the stray parameter of tested device, and during randomization, these expression formulas will be satisfied.As current configuration and frontly once configure the logical relation that need meet, the logical relation that two registers need meet, the legal range etc. of the value of register.
In step S402, configure according to above-mentioned tested device, generate the class object corresponding with test affairs.
In embodiments of the present invention, register image and the constraint expression formula of tested device is determined by tested device configuration, and set up according to tested device configuration and test class object corresponding to affairs, and using register image and the constraint expression formula member as class object.
In step S403, above-mentioned class object is carried out at random.
In step s 404, enter row stochastic result according to described class object, generate test affairs.
For the ease of understanding, be described with the method for a specific implementation example to the embodiment of the present invention below, but be not limited with this realization example, specifically refer to Fig. 5, when system function calls, tested device is searched by tested device configured list, and load corresponding tested device configuration, register image and constraint expression formula is obtained by tested device configuration, register image specifically comprises the title of tested device register, address, bit wide, default value, currency, the parameters such as last sub-value and configuration constraint expression formula, the attribute of class object is set simultaneously, using the member of the data in above-mentioned parameter and stochastic ordering list as the class object of prior construction, the random device of separating constraint server calls class object is carried out at random to class object, solve the random effect of class object, complete class object random after, by the result combination producing test affairs solved, follow-up transaction processor is sent to after test affairs produce, tested device is driven into again by bus driver.
In the embodiment of the present invention, at least 1 tested device configuration can be set according to the difference of the type of formula device to be measured, specifically can comprise tested device configuration 1, tested device configuration 2 ... tested device configuration N, wherein, N is natural number, the value of concrete tested device configured number N can be determined according to the actual needs, secondary not in order to limit the present invention.
In embodiments of the present invention, make the random affairs of generation become transparent, automatic by tested device configuration, the coverage rate of test vector need not be considered when writing test procedure, also need not consider how test vector produces.By automatically carrying out randomization to random affairs, ensure to verify random, comprehensive and robotization.
embodiment three
Fig. 6 show that the invention process three provides when random affairs are random I/O operation affairs, according to system function, and the maintenance list that system function is corresponding, generate the realization flow figure of the method for random affairs, details are as follows:
In step s 601, determine to need randomized stray parameter in random IO function.
In step S602, by I/O bank table, in chronological sequence order produces the random value of above-mentioned stray parameter.
In step S603, according to the random value of above-mentioned stray parameter, generate random I/O operation affairs.
For the ease of understanding, be described with the method for a specific implementation example to the embodiment of the present invention below, but be not limited with this realization example, specifically refer to Fig. 7, when random affairs are random I/O operation affairs, according to the parameter of random IO function, determine which parameter can be random, which is fixing, wherein, by random can be operation address, operand, burst out mode, mode of operation etc., then, by I/O bank table, in chronological sequence take out address and address random mask in turn, operand and operand random mask, mode of operation and mode of operation random mask and burst out mode and the mode mask that bursts out, when needs are random, calling system random function, address acquisition, operand, the random value of mode of operation and the stray parameters such as mode that burst out, according to the random value of stray parameter, generate random I/O operation affairs.
embodiment four
Fig. 8 show that the invention process four provides when random affairs are random series operation affairs, according to system function, and the maintenance list that system function is corresponding, generate the realization flow figure of the method for random affairs, details are as follows:
In step S801, determine the parameter of the random number that test procedure needs or random series.
In step S802, according to stochastic ordering list and above-mentioned parameter, calculate random number or the random series of test procedure needs.
In step S803, the random number calculated or random series are returned to test procedure, and be kept in stochastic ordering list.
For the ease of understanding, be described with the method for a specific implementation example to the embodiment of the present invention below, but be not limited with this realization example, specifically refer to Fig. 9, in this realization example, test procedure needs to obtain the random number or the random number sequence that meet specified conditions.According to the known value in stochastic ordering list, and above-mentioned parameter, known value, weight and the scope comprised in the system function called uses the method for mathematical operation to calculate qualified number or array returns to test procedure, and result is kept in stochastic ordering list to treat that next time makes, time item the earliest in stochastic ordering list can be deleted, to keep the item number of stochastic ordering list for fixed value simultaneously.
embodiment five
Figure 10 shows the structure of the verification system of the SOC that the embodiment of the present invention five provides, and for the ease of understanding, illustrate only the structure of relevant portion.
The structure of the system of the embodiment of the present invention specifically comprises loader 101, random affairs generator 102 and authentication unit 103, wherein:
Loader 101 loads test procedure.
In embodiments of the present invention, loader 101 loads test procedure, specifically can load the test master routine in trial function storehouse or test interrupt service routine and run, when tested device does not interrupt producing, then load test master routine and run; And when tested device sends interrupt request, then load interrupt service routine and run, now, test master routine is suspended to suspend and performs, then performs interrupt service routine, and after interrupt service routine is complete, test master routine continues to perform.
The test procedure that random affairs generator 102 loads according to above-mentioned loader 101 calls corresponding system function in system interface function library, according to said system function, and the maintenance list that said system function is corresponding, generate random affairs.
According to the random affairs that above-mentioned random affairs generator 102 produces, authentication unit 103 is treated test chip and is verified.
When random affairs are random test affairs, described random affairs generator 102 comprises device and searches unit, class object generation unit, class object random cells and test affairs generation unit, is specially:
Device searches unit in tested device configured list, searches the tested device corresponding with described tested device and configures.
In embodiments of the present invention, described tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, described register image specifically comprises the title of register, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values, and described constraint expression formula limits the scope of the stray parameter of tested device
Search according to described device the tested device configuration that unit searches, class object generation unit generates the class object corresponding with testing affairs.
Class object random cells is carried out the class object that described class object generation unit generates at random.
Enter row stochastic result according to described class object random cells to class object, test affairs generation unit generates test affairs.
When random affairs are random I/O operation affairs, described random affairs generator 102 comprises stray parameter determining unit, random value generation unit and I/O operation generation unit, is specially:
Stray parameter determining unit is determined to need randomized stray parameter in random IO function.
By I/O bank table, random value generation unit in chronological sequence order produces the random value of described stray parameter determining unit determination stray parameter.
According to the random value of the stray parameter that described random value generation unit generates, I/O operation generation unit generates random I/O operation affairs.
When random affairs are random series operation affairs, described random affairs generator 102 comprises random series determining unit, random series determining unit, computing unit and returns unit, is specially:
The parameter of the random number that random series determining unit determination test procedure needs or random series.
According to the parameter that stochastic ordering list and described random series determining unit are determined, computing unit calculates random number or the random series of test procedure needs.
Return random number that described computing unit calculates by unit or random series returns to test procedure, and be kept in stochastic ordering list.
The embodiment of the present invention loads test procedure by loader, and corresponding system function is called in system interface function library, according to said system function, and the maintenance list that said system function is corresponding, generate random affairs, according to above-mentioned random affairs, treat test chip and verify, the test procedure that software engineer is write can directly run on existing verification platform, achieves software-hardware co-designing.
embodiment six
Figure 11 shows the structure of the SOC verification system that the embodiment of the present invention six provides, and for the ease of understanding, illustrate only the structure of relevant portion.
In embodiments of the present invention, Direct Programming interface (DirectProgrammingInterface can be passed through, DPI) start-up loading device, and the test procedure of loading is loaded on analogue system, by DPI interface, C/C++ program can call the function of EDA (Electronicdesignautomation) language domains, and EDA language domains also can call the function of C/C++ language domains.
Wherein, test procedure can comprise master routine and interrupt service routine, and the DPI interface of corresponding system can comprise master routine DPI interface 111 and interrupt routine DPI interface 112.
In embodiments of the present invention, when tested device does not interrupt producing, perform test master routine, when tested device sends interrupt request, perform interrupt service routine, when there being multiple interrupt request to arrive, system can comprise interrupt manager 114 and carry out priority management and interrupt nesting management.
embodiment seven
Figure 12 shows the structure of the SOC verification system that the embodiment of the present invention seven provides, and for the ease of understanding, illustrate only the structure of relevant portion.
The corresponding system function that random affairs generator calls in system interface function library 125, system function specifically comprises: control function, event functions, IO function, semaphore function, shared data function, thread function or randomized function.
System function operation safeguards list 126 accordingly, safeguards that list kind specifically comprises: list of thing, I/O bank table, semaphore list, general data list, thread list, stochastic ordering list and tested device configured list.
In embodiments of the present invention, random affairs generator 128 comprises random device configuration operation unit 1281, random I/O operation unit 1282 and/or random series operating unit 1283.
Wherein, the device that specifically comprises that Figure 13 shows random device configuration operation unit searches module 131, class object generation module 132, class object randomized blocks 133 and test affairs generation module 134, wherein:
Device searches module 131 in tested device configured list 127, searches the tested device corresponding with above-mentioned tested device and configures, and loads the tested device configuration corresponding with tested device.
In embodiments of the present invention, tested device configuration can comprise the register image of tested device and the constraint expression formula of tested device, above-mentioned register image specifically comprises the title of register, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values, and above-mentioned constraint expression formula limits the scope of the stray parameter of tested device.
Search according to above-mentioned device the tested device configuration that module 131 searches, class object generation module 132 generates the class object corresponding with testing affairs.
Class object randomized blocks 133 carries out the class object that above-mentioned class object generation module 132 generates at random.
In embodiments of the present invention, class object randomized blocks 131 calls the random device of corresponding class object, carries out at random class object.
Enter row stochastic result according to above-mentioned class object randomized blocks 133 pairs of class objects, test affairs generation module 134 generates test affairs.
Figure 14 shows the concrete structure of above-mentioned random I/O operation unit:
Stray parameter determination module 141 is determined to need randomized stray parameter in random IO function.
Random value generation module 142 is by safeguarding the I/O bank table in list 126, and in chronological sequence order produces the random value of stray parameter determination module determination stray parameter.
According to the random value of the stray parameter that random value generation module 142 generates, I/O operation generation module 143 generates random I/O operation affairs.
Figure 15 shows the concrete structure of above-mentioned random series operating unit:
Random series determination module 151 determines the parameter of the random number that test procedure needs or random series.
According to the parameter that the stochastic ordering list safeguarded in list 126 and random series determination module 151 are determined, computing module 152 calculates random number or the random series of test procedure needs.
Return random number that computing module calculates by module 153 or random series returns to test procedure, and be kept in stochastic ordering list.
embodiment eight
Figure 16 shows the proof procedure of the SOC that the embodiment of the present invention eight provides:
(1) Hardware Engineer designs tested device (deviceundertest, DUT), provides register-transmitting stage code (RegisterTransferLevelCode, RTL)
(2) Hardware Engineer or checking slip-stick artist extract tested device configuration constraint file (deviceundertestconfiguration, dut_cfg) of outlines device characteristic according to hardware design specifications.
(3) verify that slip-stick artist gets out verification system miscellaneous part as transaction processor, bus driver, monitor, automatically comparer etc. according to the verification methodology (such as VMM) of current popular.
(4) verify that above-mentioned DUT, dut_cfg, parts of the present invention and verification platform miscellaneous part are connected into verification system by slip-stick artist.
(5) verify that slip-stick artist or software engineer are ready to using the test procedure of c/c++ language compilation as test file, such as, test procedure can be driver or application program.
(6) verify that slip-stick artist or software engineer are by test file, are compiled into test procedure library file with standard c/c++ compiler.
(7) Utility Engineers EDA emulator compiling verification system is verified.
(8) verify that slip-stick artist is using the time as random seed (randomseed) runtime verification system.
(9), after emulation starts, test procedure library file is loaded into verification system by loader and runs by master controller.
(10) verification system run duration may find that hardware logic behavior, performance etc. define inconsistent defect (bug) with hardware design specifications, at this moment, automatic comparer suspends verification system, record random seed and derive simulation waveform, transferring to checking slip-stick artist, Hardware Engineer jointly to debug; Use identical random seed to rerun verification system and can reappear defect scene, convenient debugging.After Hardware Engineer changes design, checking slip-stick artist recompilates verification system.
(11) if verification system run duration does not find hardware deficiency, verification system runs until current trial function completes.
(12), after current trial function completes, DUT code coverage is checked.
(13) if do not reach the coverage rate target of setting, then repeat 8 ~ 12 steps and re-start random simulation next time, until terminate emulation when code coverage makes it.
To sum up above-mentioned, the embodiment of the present invention calls corresponding system function, according to said system function by the test procedure of above-mentioned loading in system interface function library, and the maintenance list that said system function is corresponding, generate random affairs, according to above-mentioned random affairs, treat test chip and verify., the test procedure that software engineer is write can directly run on existing verification platform, achieves software-hardware co-designing, simultaneously by low level information is encapsulated, makes verification system easy to use, and is easy to multiplexing.
In addition, make the random affairs of generation become transparent, automatic by tested device configuration, the coverage rate of test vector need not be considered when writing test procedure, also need not consider how test vector produces.By automatically carrying out randomization to random affairs, ensure to verify random, comprehensive and robotization.
It should be noted that the unit included by said system is carry out dividing according to function logic, but be not limited to above-mentioned division, as long as corresponding function can be realized; In addition, the concrete title of each functional unit, also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that all or part of step realized in above-described embodiment method is that the hardware that can carry out instruction relevant by program completes, corresponding program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. a verification method for SOC, is characterized in that, described method comprises the steps:
Load test procedure;
In system interface function library, corresponding system function is called according to described test procedure, according to described system function, and the maintenance list that described system function is corresponding, generate random affairs, describedly safeguard that list comprises multiple different list, being specially different system functions carries out corresponding from different lists, and described random affairs comprise random test affairs, random I/O operation affairs and/or random series operation affairs;
According to described random affairs, treat test chip and verify.
2. the method for claim 1, is characterized in that, when random affairs are random test affairs, described according to described system function, and the maintenance list that described system function is corresponding, and the step generating random affairs is specially:
In tested device configured list, search the tested device corresponding with described tested device and configure;
Configure according to described tested device, generate the class object corresponding with test affairs;
Carry out at random to described class object;
Enter row stochastic result according to described class object, generate test affairs.
3. method as claimed in claim 2, it is characterized in that, described tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, described register image specifically comprises the title of register, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values, and described constraint expression formula limits the scope of the stray parameter of tested device.
4. the method for claim 1, is characterized in that, when random affairs are random I/O operation affairs, described according to described system function, and the maintenance list that described system function is corresponding, and the step generating random affairs is specially:
Determine to need randomized stray parameter in random IO function;
By I/O bank table, in chronological sequence order produces the random value of described stray parameter;
According to the random value of described stray parameter, generate random I/O operation affairs.
5. the method for claim 1, is characterized in that, when random affairs are random series operation affairs, described according to described system function, and the maintenance list that described system function is corresponding, and the step generating random affairs is specially:
Determine the parameter of the random number that test procedure needs or random series;
According to stochastic ordering list and described parameter, calculate random number or the random series of test procedure needs;
The described random number that calculates or random series are returned to test procedure, and is kept in stochastic ordering list.
6. the method for claim 1, is characterized in that, described test procedure comprises test master routine and test interrupt service routine;
When tested device does not interrupt producing, perform test master routine;
When tested device sends interrupt request, perform interrupt service routine.
7. a verification system for SOC, is characterized in that, described system comprises:
Loader, for loading test procedure;
Random affairs generator, test procedure for loading according to described loader calls corresponding system function in system interface function library, according to described system function, and the maintenance list that described system function is corresponding, generate random affairs, describedly safeguard that list comprises multiple different list, be specially different system functions and carry out corresponding from different lists, described random affairs comprise random test affairs, random I/O operation affairs and/or random series operation affairs;
Authentication unit, for the random affairs produced according to described random affairs generator, treats test chip and verifies.
8. system as claimed in claim 7, it is characterized in that, when random affairs are random test affairs, described random affairs generator comprises:
Unit searched by device, in tested device configured list, searches the tested device corresponding with described tested device and configures;
Class object generation unit, searching according to described device the tested device configuration that unit searches, generating the class object corresponding with testing affairs;
Class object random cells, carries out at random for the class object generated described class object generation unit;
Test affairs generation unit, for entering row stochastic result according to described class object random cells to class object, generates test affairs.
9. system as claimed in claim 8, it is characterized in that, described tested device configuration comprises the register image of tested device and the constraint expression formula of tested device, described register image specifically comprises the title of register, address, bit wide, default configuration value, current Configuration Values and a front Configuration Values, and described constraint expression formula limits the scope of the stray parameter of tested device.
10. system as claimed in claim 7, it is characterized in that, when random affairs are random I/O operation affairs, described random affairs generator comprises:
Stray parameter determining unit, needs randomized stray parameter for determining in random IO function;
Random value generation unit, for by I/O bank table, in chronological sequence sequentially produces the random value of described stray parameter determining unit determination stray parameter;
I/O operation generation unit, for the random value of the stray parameter according to described random value generation unit generation, generates random I/O operation affairs.
11. systems as claimed in claim 7, is characterized in that, when random affairs are random series operation affairs, described random affairs generator comprises:
Random series determining unit, for determining the parameter of the random number that test procedure needs or random series;
Computing unit, for the parameter determined according to stochastic ordering list and described random series determining unit, calculates random number or the random series of test procedure needs;
Return unit, return to test procedure for the random number that calculated by described computing unit or random series, and be kept in stochastic ordering list.
12. systems as claimed in claim 7, is characterized in that, described test procedure comprises test master routine and test interrupt service routine.
13. systems as claimed in claim 7, it is characterized in that, described system also comprises interrupt manager, for when there being multiple interrupt request to arrive, carries out priority management and interrupt nesting management.
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| CN201110217229.7A CN102902834B (en) | 2011-07-29 | 2011-07-29 | A kind of verification method of SOC and system |
| PCT/CN2012/076895 WO2013016979A1 (en) | 2011-07-29 | 2012-06-14 | Method and system for verifying soc chip |
| PCT/CN2012/079225 WO2013017037A1 (en) | 2011-07-29 | 2012-07-26 | Method and system for verifying soc chip |
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