CN102891253B - Resistance-variable storing device and preparation method thereof - Google Patents
Resistance-variable storing device and preparation method thereof Download PDFInfo
- Publication number
- CN102891253B CN102891253B CN201210361359.2A CN201210361359A CN102891253B CN 102891253 B CN102891253 B CN 102891253B CN 201210361359 A CN201210361359 A CN 201210361359A CN 102891253 B CN102891253 B CN 102891253B
- Authority
- CN
- China
- Prior art keywords
- electrode
- top electrode
- formation
- storing device
- resistance layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The embodiment of the invention discloses a kind of resistance-variable storing device and preparation method thereof.Described resistance-variable storing device comprises top electrode, resistive material and bottom electrode, and described resistive material is positioned on bottom electrode, and described top electrode is embedded within resistive material, and the width at the top of described top electrode is greater than the width bottom it.The invention also discloses the preparation method of resistance-variable storing device.Resistance-variable storing device provided by the present invention and preparation method thereof, effectively can reduce the active area of electrode, meanwhile, originally can realize the effect of nanoscale-memory with the one-tenth making micron order memory, and simplify the manufacture craft of memory, saved cost of manufacture simultaneously.
Description
Technical field
The present invention relates to field of semiconductor devices, specifically, relate to semiconductor resistance-variable storing device and manufacture method thereof, more specifically, relate to a kind of resistance-variable storing device with microelectrode and preparation method thereof.
Background technology
Along with the development that information technology is at full speed, semiconductor memory has become the indispensable part of various electronic apparatus system.At present, memory on market some be the floating gate flash memory (FloatingGateFlashMemory) doing floating grid (floatinggate) and control gate (controlgate) based on the polysilicon gate of other materials of mixing (as boron, phosphorus).But flash memory is swift and violent in nearest Two decades years development, flash cell size sharply reduces, flash memory faces huge challenge in scaled down, after particularly entering 45nm technology node, distance between flash cell reduces, cause the interference between unit to increase the weight of, the reliability of memory is brought and has a strong impact on.
By contrast, the features such as resistance-variable storing device is with its good stability, and reliability is strong, and structure is simple, and CMOS technology is compatible, are more and more widely used.Resistance-variable storing device is a kind of voltage by additional opposed polarity, size, changes the resistance sizes of resistive material thus the novel memory devices part of storage data.Primarily of top electrode in structure, resistive material and bottom electrode composition.In order to adapt to more and more higher requirement, wish the operating current of resistance-variable storing device, the operating current (reset operation) especially from low-resistance to high resistant is the smaller the better.
Existing resistance variation memory structure is generally MIM(metal electrode-resistive material-metal electrode) structure or criss-cross construction.Mim structure refers to the structure of upper/lower electrode sandwich resistive material, is similar to electric capacity.Criss-cross construction is upper and lower two mutual square crossings of microelectrode, between the overlapping area intersected, fill resistive material.No matter be which kind of structure, all expect to obtain low operating current, one of method is exactly reduce electrode area.Electrode area is less, and the effective area being carried in electric field on resistive material is less, and the conductive filament of formation is more concentrated, and operating current is less.Electrode does less by current hope, and especially reach hundred nanometers and the even less rank of ten nanometers, thus realize this microelectrode (namely above-mentioned metal electrode) often through nano level technique, manufacture craft is comparatively complicated, and cost is high and unstable.
Summary of the invention
Reduce electrode area complex process and the high problem of cost for what exist in above-mentioned technology, in the embodiment of the present invention, provide a kind of resistance-variable storing device and preparation method thereof.
On the one hand, The embodiment provides a kind of resistance-variable storing device, comprise top electrode, resistive material and bottom electrode, described resistive material is positioned on bottom electrode, described top electrode is embedded within resistive material, and the width at the top of described top electrode is greater than the width bottom it.
On the other hand, The embodiment provides a kind of preparation method of resistance-variable storing device, comprising: step one: by deposited metal on Semiconductor substrate, form bottom electrode; Step 2: grow the material for the formation of change resistance layer on the bottom electrode, and in for the formation of the material of change resistance layer, form groove by anisotropic etching, the width of the upper opening of described groove is greater than the width of its lower surface; Step 3: fill described groove by utilizing metal material and form top electrode, makes the width at the top of described top electrode be greater than width bottom it; Step 4: form change resistance layer by the material for the formation of change resistance layer be oxidized on described bottom electrode.
Compared with prior art, resistance-variable storing device provided by the present invention and preparation method thereof, because top electrode is embedded in resistive material with the shape being similar to inverted trapezoidal, top electrode upper end open area is greater than the area bottom it, the effective active area of this memory is the area size that top electrode lower end surface region and bottom electrode are corresponding with it, thus the effective active area of electrode can be reduced, and then can optimized device performance.
In addition, in preparation, owing to can be achieved the making of sub-micron or nano level electrode by micron order Fabrication Technology of Electrode, or the making of nanoscale electrodes is realized by the Fabrication Technology of Electrode of submicron order, the manufacture craft adopting complicated smaller szie is not needed in manufacture process, thus, can manufacture craft be simplified, cost-saving.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the resistance variation memory structure schematic diagram with microelectrode of one embodiment of the invention;
Fig. 2,3,4,5,6,7 shows and makes the flow chart with the resistance-variable storing device of microelectrode according to the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, carry out clear, complete description to the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
See Fig. 1, Fig. 1 shows the resistance variation memory structure schematic diagram with microelectrode of the embodiment of the present invention, wherein, resistance-variable storing device comprises top electrode 1, resistive material 2 and bottom electrode 3, resistive material 2 is positioned on bottom electrode 3, top electrode 1 is embedded within resistive material 2, and, make the width at the top of top electrode be greater than width bottom it.
Embodiment as shown in Figure 1, the top electrode part be embedded within resistive material can be inverted trapezoidal, and the sidewall of inverted trapezoidal is a with the angle in the direction being parallel to bottom electrode.This angle a depends on the type of etching technics and resistive material, such as, when adopt wet etching and be silicon for the formation of the material of resistive material, described angle a can be 54.74 °.The region of the effective active area of top electrode and bottom electrode in Fig. 1 shown in 4, namely in top electrode bottom section and bottom electrode with the region of the part corresponding to it.
Compared with prior art, in the structure of the resistance-variable storing device according to the embodiment of the present invention, because top electrode top width is greater than its bottom width, and the effective electrode area of this memory is the area with bottom electrode corresponding part bottom top electrode, thus effectively can reduce electrode area.
Fig. 2,3,4,5,6,7 shows and makes the flow process with the resistance-variable storing device of microelectrode according to the embodiment of the present invention, comprises the following steps.
Step one: by deposited metal on Semiconductor substrate 31, forms bottom electrode 3.
According to one embodiment of present invention, as shown in Figure 2, by deposit layer of metal on silicon substrate 31, bottom electrode 3 can be formed.
In a specific embodiment, described metal can be platinum, tungsten, nickel, aluminium, palladium, gold, titanium, any one in titanium nitride.
Step 2: grow the material for the formation of change resistance layer on the bottom electrode, and in for the formation of the material of change resistance layer, form groove by anisotropic etching, the width of the upper opening of described groove is greater than the width of its lower surface.
Specifically, above-mentioned steps two can be realized by following process.
First, the material for the formation of change resistance layer can be grown on the bottom electrode.
In one embodiment of the invention, the described material for the formation of change resistance layer can comprise: silicon, germanium and other known or being applicable to of being about to occur form the material of change resistance layer.
As shown in Figure 3, in one particular embodiment of the present invention, monocrystalline silicon layer 22 can be grown as the material for the formation of change resistance layer by crystal orientation 100 on the lower electrode 3.
Then, can described for the formation of the material of change resistance layer in form groove, the width of the upper opening of described groove is greater than the width of its lower surface.
As shown in Figure 4, in one particular embodiment of the present invention, photoresist 21 can smeared for the formation of on the material (such as, the monocrystalline silicon layer 22 in Fig. 4) of change resistance layer, and reserve the window size size needing etching, to carry out follow-up etching technics.Afterwards, as shown in Figure 5, anisotropic etch process (dry anisotropic etching technics or wet anisotropic etching technics) can be passed through in for the formation of the material (monocrystalline silicon layer 22 such as, in Fig. 4) of change resistance layer, form groove.
Consider the anisotropy of silicon materials in wet etching (namely the etch rate of monocrystalline silicon 111 is very large with the ratio of the etch rate of 100), in a preferred embodiment of the invention, wet etching technique can be adopted to form groove.Such as, can etch on 100, because when etching into 111, etching speed greatly reduces, so can form a groove.In addition, can just can the degree of depth of control flume and bottom area by controlling the concentration of etching liquid and etch period.
Fig. 5 shows the inverted trapezoidal groove utilizing wet anisotropic to etch to obtain.As shown in Figure 5, the width of the upper opening of described groove is greater than the width of its lower surface.Although Fig. 5 does not illustrate, when adopt wet etching and be silicon for the formation of the material of resistive material, be 54.74 ° at the hypotenuse of obtained inverted trapezoidal groove (i.e. described groove) and the angle a in the direction that is parallel to bottom electrode.In addition, for different application scenarios, adjust by the concentration and etch period controlling etching liquid the degree of depth etching the inverted trapezoidal groove obtained.
Step 3: fill described groove by utilizing metal material and form top electrode, makes the width at the top of described top electrode be greater than width bottom it.
In one embodiment of the invention, at monocrystalline silicon layer 22 top depositing metal 24, inverted trapezoidal groove can be filled, obtains structure as shown in Figure 6 thus; Then, the metal on stripping photoresist 21 and photoresist 21, the metal only leaving filling inverted trapezoidal slot part, as top electrode, obtains the structure of memory as shown in Figure 7.
Wherein, in a particular embodiment, the metal level of described top electrode can be platinum, tungsten, nickel, aluminium, palladium, gold, titanium, any one in titanium nitride.
Step 4: form change resistance layer.
In one embodiment, by the described material (such as monocrystalline silicon) for the formation of change resistance layer of oxidation, silica change resistance layer can be formed.In this case, described change resistance layer comprises silica.
In addition, above embodiment is only example, the present invention is not limited thereto, and also can form change resistance layer by the material of other any appropriate, such as, germanium can be utilized to form germanium oxide as change resistance layer etc.
Compared with prior art, the resistance-variable storing device preparation method that the embodiment of the present invention provides, the effective active area of electrode is the area of metal material bottom portion of groove, in illustrated embodiment of the present invention, the area on groove top is submicron order, and bottom is nanoscale, the nano level effect that the cost being equivalent to make other resistance-variable storing device of submicron order realizes, simplify manufacture craft, greatly reduce cost of manufacture simultaneously.
Resistance-variable storing device that the embodiment of the present invention provides and preparation method thereof, due to the structure that top electrode is wide at the top and narrow at the bottom, the effective active area of electrode is the less area bottom top electrode, not only effectively reduces the area of electrode, optimizes device, simultaneously, in preparation process, obtain submicron order or nano level electrode by micron order Fabrication Technology of Electrode, or obtain nano level electrode by the manufacture craft of submicron order electrode, simplify manufacture craft, save cost of manufacture.
Claims (7)
1. a resistance-variable storing device, it is characterized in that, comprise top electrode (1), resistive material (2) and bottom electrode (3), described resistive material (2) is positioned on bottom electrode (3), described top electrode (1) is embedded within resistive material (2), the width at the top of described top electrode is greater than the width bottom it, wherein, described top electrode and bottom electrode effective active area in: top electrode bottom section and bottom electrode with the region of the part corresponding to it;
The described top electrode part be embedded within resistive material is inverted trapezoidal, the sidewall of described inverted trapezoidal is a with the angle in the direction being parallel to bottom electrode, wherein, employing wet etching forms inverted trapezoidal and is silicon for the formation of the material of resistive material in resistive material, and a is 54.74 °.
2. resistance-variable storing device as claimed in claim 1, it is characterized in that, described top electrode is by platinum, tungsten, nickel, aluminium, palladium, gold, titanium, and any one material in titanium nitride is made.
3. resistance-variable storing device as claimed in claim 1, it is characterized in that, described bottom electrode is by platinum, tungsten, nickel, aluminium, palladium, gold, titanium, and any one material among titanium nitride is made.
4. a preparation method for resistance-variable storing device, is characterized in that, comprising:
Step one: by deposited metal on Semiconductor substrate (31), forms bottom electrode (3);
Step 2: grow the material (22) for the formation of change resistance layer on the bottom electrode, and by anisotropic etching described for the formation of the material of change resistance layer in form groove, the width of the upper opening of described groove is greater than the width of its lower surface;
Step 3: fill described groove by utilizing metal material and form top electrode, the width at the top of described top electrode is made to be greater than width bottom it, wherein, described top electrode and bottom electrode effective active area in: top electrode bottom section and bottom electrode with the region of the part corresponding to it;
Step 4: form change resistance layer by the material for the formation of change resistance layer be oxidized on described bottom electrode;
Wherein, the described top electrode part be embedded within change resistance layer is inverted trapezoidal, and the sidewall of described inverted trapezoidal is a with the angle in the direction being parallel to bottom electrode, and described anisotropic etching is wet etching, and the material for the formation of change resistance layer is silicon, and a is 54.74 °.
5. resistance-variable storing device preparation method as claimed in claim 4, it is characterized in that, described metal level comprises: platinum, tungsten, nickel, aluminium, palladium, gold, titanium, any one in titanium nitride.
6. resistance-variable storing device preparation method as claimed in claim 4, is characterized in that, the described process forming groove in for the formation of the material of change resistance layer by anisotropic etching comprises:
Smear photoresist in the upper surface of the material for the formation of change resistance layer, and reserve the window size size needing etching;
Utilize photoresist as mask, by the material for the formation of change resistance layer described in anisotropic etching, form groove.
7. resistance-variable storing device preparation method as claimed in claim 6, is characterized in that, fills the process that described groove forms top electrode comprise by utilizing metal material:
At the material top depositing metal for the formation of change resistance layer with filling groove, described metal is platinum, tungsten, nickel, aluminium, palladium, gold, titanium, any one among titanium nitride;
Peel off the metal be deposited on photoresist part, leave the metal be filled in for the formation of the material pocket part of change resistance layer and form top electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210361359.2A CN102891253B (en) | 2012-09-25 | 2012-09-25 | Resistance-variable storing device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210361359.2A CN102891253B (en) | 2012-09-25 | 2012-09-25 | Resistance-variable storing device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102891253A CN102891253A (en) | 2013-01-23 |
| CN102891253B true CN102891253B (en) | 2016-03-02 |
Family
ID=47534701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210361359.2A Active CN102891253B (en) | 2012-09-25 | 2012-09-25 | Resistance-variable storing device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102891253B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576926B (en) * | 2013-10-25 | 2019-05-14 | 华邦电子股份有限公司 | Resistance-type memory and its manufacturing method |
| CN104409627A (en) * | 2014-10-30 | 2015-03-11 | 北京大学 | Small-size ultrathin resistive random access memory and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200636923A (en) * | 2005-02-23 | 2006-10-16 | Taiwan Semiconductor Mfg Co Ltd | Memory device and fabrication method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100481865B1 (en) * | 2002-11-01 | 2005-04-11 | 삼성전자주식회사 | Phase changeable memory device and method of fabricating the same |
| KR101004207B1 (en) * | 2006-03-09 | 2010-12-24 | 파나소닉 주식회사 | Resistance-varying type element, semiconductor device, and method for manufacturing the element |
| WO2008047530A1 (en) * | 2006-10-16 | 2008-04-24 | Panasonic Corporation | Non-volatile storage device and method for manufacturing the same |
| US8283650B2 (en) * | 2009-08-28 | 2012-10-09 | International Business Machines Corporation | Flat lower bottom electrode for phase change memory cell |
| KR101094384B1 (en) * | 2010-01-21 | 2011-12-15 | 주식회사 하이닉스반도체 | Resistive memory device and method for manufacturing the same |
-
2012
- 2012-09-25 CN CN201210361359.2A patent/CN102891253B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200636923A (en) * | 2005-02-23 | 2006-10-16 | Taiwan Semiconductor Mfg Co Ltd | Memory device and fabrication method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102891253A (en) | 2013-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9281476B2 (en) | Resistive memory and method for fabricating the same | |
| CN103247632B (en) | Semiconductor device and method of manufacturing the same | |
| JP5544621B2 (en) | Electrochemical transistor | |
| Ielmini et al. | Nanowire-based resistive switching memories: devices, operation and scaling | |
| CN106847821A (en) | Semiconductor structure and forming method thereof | |
| US9768381B2 (en) | Resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof | |
| CN103682091A (en) | Resistive memory structure, operation method and manufacturing method thereof | |
| TWI460896B (en) | Nonvolatile resistance change element | |
| CN102610746A (en) | Nonvolatile resistance transformation type memorizer | |
| CN102891253B (en) | Resistance-variable storing device and preparation method thereof | |
| CN101764195B (en) | Method for making nano-sized phase change memory | |
| WO2014047974A1 (en) | Resistive random access memory and preparation method thereof | |
| CN103456883A (en) | Field focusing features in a reram cell | |
| US9680094B2 (en) | Memory device and method for manufacturing the same | |
| CN103035575A (en) | Formation method of flash memory storage cell | |
| US9076519B2 (en) | Reram device structure | |
| CN101789492B (en) | Preparation method of plane phase change memory | |
| CN110010610A (en) | Split-gate flash memory and forming method thereof | |
| CN104071745A (en) | Preparation method for silicon nanowire field effect tube with closely attached suspended grid electrode | |
| CN103779182A (en) | Method for manufacturing nanowire | |
| KR101263309B1 (en) | Fabrication method of resistive random access memory device using sidewall and spacer processes and rram fabricated by the same method | |
| CN103035838B (en) | Resistive random access memory component and preparation method thereof | |
| CN103296051A (en) | Resistive random memory unit with Schottky barrier structures and method for forming resistive random memory unit | |
| CN102610275B (en) | Cadmium selenide nanowire-based Schottky junction type multi-byte nonvolatile memory and preparation method thereof | |
| CN204130534U (en) | A kind of non-volatile high density three dimensional semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |