CN102881690B - Dynamic random access memory and manufacture method thereof - Google Patents
Dynamic random access memory and manufacture method thereof Download PDFInfo
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- CN102881690B CN102881690B CN201110196006.7A CN201110196006A CN102881690B CN 102881690 B CN102881690 B CN 102881690B CN 201110196006 A CN201110196006 A CN 201110196006A CN 102881690 B CN102881690 B CN 102881690B
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Abstract
The invention discloses a kind of dynamic random access memory and manufacture method thereof, above-mentioned dynamic random access memory comprises a buried bit lines, is arranged in the bottom of one first groove extending along a first direction in a substrate; The a pair of character line that buries, is arranged at respectively in the pair of sidewalls of one second groove extending along a second direction in aforesaid substrate; One auxiliary character line, is arranged at the top of another buried bit lines that is parallel to above-mentioned buried bit lines, and completely cuts off with above-mentioned another buried bit lines along above-mentioned first direction, wherein the two ends of above-mentioned auxiliary character line connect respectively above-mentioned to burying character line.
Description
Technical field
Present invention is directed to a kind of dynamic random access memory and manufacture method thereof, relate to especially one dynamically withBuried bit lines and the manufacture method thereof of machine access memory structure cell.
Background technology
At present electric capacity is stacked to stacking type (stacked) dynamic random access memory (Dynamic on transistorRandomAccessMemory, hereinafter to be referred as DRAM) can reach the target of high memory density. Because as stacking typeIn DRAM, the buried bit lines contactant (buriedbitlinecontact, CB) of transistor drain contactant produces with transistorInverting channel (inversionchannel) be not positioned at sustained height, the two contiguity is extremely important. But,Now in manufacturing process, in order to determine the bottom surface of burying character line (buriedwordline, BW) of stacking type DRAMTrench etch step is not good and produce to the distance control between the end face of buried bit lines (buriedbitline, BL) of its belowMany problems. For instance, burying hypotelorism between the bottom surface of character line and the end face of buried bit lines can make element produceElectric leakage. On the other hand, the hypertelorism burying between the bottom surface of character line and the end face of buried bit lines can make in DRAM brilliantThe On current (on-current) of body pipe is too small, and needs larger buried bit lines contact regions of out-diffusion to increase buried bit linesThe contiguity of contactant and inverting channel, can produce adjacent buried bit lines contact electric leakage (CBleakage) problem like this.
Therefore, need a kind of dynamic random access memory and manufacture method thereof with novel structure badly, to solve above-mentioned askingTopic.
Summary of the invention
In view of this, one embodiment of the invention system provides a kind of dynamic random access memory, comprises a buried bit lines,Be arranged at respectively in the bottom of one first groove extending along a first direction in a substrate; The a pair of character line that buries, respectivelyBe arranged in the pair of sidewalls of one second groove extending along a second direction in aforesaid substrate; One auxiliary character line, along upperState the top that first direction is arranged at another buried bit lines that is parallel to above-mentioned buried bit lines, and bury position with above-mentioned anotherLine is isolated, and wherein the two ends of above-mentioned auxiliary character line connect respectively above-mentioned to burying character line.
Another embodiment of the present invention system provides a kind of manufacture method of dynamic random access memory, comprises a substrate is provided;In aforesaid substrate, form one first groove parallel to each other and another first groove along a first direction; In above-mentioned the first ditchIn the bottom of groove and above-mentioned another the first groove, form a buried bit lines and another buried bit lines; In above-mentioned another first grooveTop in form a high K dielectric matter; In aforesaid substrate, form one second groove along a second direction; RemoveAbove-mentioned high K dielectric matter, and the pair of sidewalls on the top of above-mentioned another the first groove is come out; In above-mentionedIn the pair of sidewalls of two grooves, form a pair of character line that buries; In out above-mentioned of the upper exposed of above-mentioned another the first grooveOn oppose side wall, form an auxiliary character line, wherein the two ends of above-mentioned auxiliary character line connect respectively above-mentioned to burying character line.
Brief description of the drawings
Fig. 1 a system shows the perspective view of the dynamic random access memory of one embodiment of the invention.
Fig. 1 b system shows the part top view of the dynamic random access memory of one embodiment of the invention, and character is buried in its demonstrationLine and auxiliary character line.
Fig. 2 a～Figure 13 a is the profile along the A-A ' tangent line of Fig. 1 a, and its dynamic random that shows one embodiment of the invention is depositedThe generalized section of the manufacture method of access to memory.
Fig. 2 b～Figure 13 b is the profile along the B-B ' tangent line of Fig. 1 a, and its dynamic random that shows one embodiment of the invention is depositedThe generalized section of the manufacture method of access to memory.
Main element symbol description:
The 100～zero felt pad; 110～the first insulation hard mask layers;
200～substrate; 201,211,219,247～end face;
202～the first felt pads; 204～the first resistance barrier bed courses;
206～the first metal strip things; 207～the first conducting objects;
208～bit line contact thing;
209,246,416,423～bottom surface;
210～diffusion region; 212,212a～the second felt pad;
214～the first insulants; 216～high K dielectric matter;
218～the second insulating barriers; 220～carbon hard mask layer;
220a～carbon hard mask pattern; 222～nitride hard mask layer;
224～photoresistance pattern; 226～hole;
229,223,230,414a, 415a, 414b, 415b～sidewall;
232,232a, 232b～thermal oxide layer;
234,234a, 234b～the second resistance barrier bed course;
236～metal material;
236a, 236b～the second metal strip thing;
240～insulating materials; 244～bury character line;
244a～auxiliary character line; 250～buried bit lines;
312～electric capacity;
314,316,318～substrate portion;
410～first direction; 412～the first grooves;
420～second direction; 422～the second grooves;
500～dynamic random access memory;
510～part.
Detailed description of the invention
Fig. 1 a system show one embodiment of the invention dynamic random access memory structure cell (hereinafter to be referred as DRAM) 500 thoroughlyView, Fig. 1 b system shows part 510 top views of the dynamic random access memory of one embodiment of the invention, its demonstration is buriedHide character line and auxiliary character line. Show for convenience buried bit lines, auxiliary character line and the configuration of burying character line, at thisWill not show the insulant that buries character line and auxiliary character line in order to isolated difference, and buried bit lines and bury character lineBetween structure, right unrestricted the present embodiment. The unit cell dimension of DRAM500 is as shown in Figure 1a 4F2(wherein FFor minimum half pitch (halfpitch), or claim unit size). As shown in Figure 1a, above-mentioned DRAM500 is arranged at a baseIn plate 200, it comprises at least one pair of buried bit lines 250, at least one pair of buries character line 244 and at least one auxiliary character line(auxiliarywordline) 244a. As shown in Figure 1a, buried bit lines 250 is that to be arranged at substrate 200 interior along one first each otherIn one first groove 412 that direction 410 is extended, above-mentioned buried bit lines 250 is to comprise a bit line contact thing 208, along firstDirection 410 is arranged on the single sidewall (singleside) 414 of the first groove 412 continuously. Burying character line 244 is respectivelyBe arranged in the pair of sidewalls 230 of interior one second groove 422 extending along a second direction 420 of substrate 200. In addition,As shown in Figure 1 a, 1 b, DRAM500 more comprises an auxiliary character line 244a, is arranged at the along first direction 410In the upper portion side wall of one groove 412, wherein the two ends of auxiliary character line 244a connect respectively a pair of character line 244 that buries.As shown in Figure 1 a, 1 b, bury character line 244 and hinder barrier bed course 234a and part the second metal strip thing by part second236a forms, and auxiliary character line 244a hinders barrier bed course 234b and part the second metal strip thing 236b structure by part secondBecome, note as shown in Figure 1 b, the second resistance barrier bed course 234a, 234b are the different piece of same the second resistance barrier bed course, andThe second metal strip thing 236a, 236b are the different piece of same the second metal strip thing.
In embodiment as shown in Figure 1a, the bit line contact thing 208 of the buried bit lines 250 of DRAM500, bury characterLine 244, adjacent to the substrate portion 314 of bit line contact thing 208, at the two adjacent substrates that bury between character line 244Part 316 and another substrate portion 318 being positioned in substrate portion 316 can form a vertical transistor, its neutrality lineContactant 208 is the drain electrode contactant as vertical transistor, bury character line 244 and auxiliary character line 244a system asThe gate of vertical transistor, and the substrate portion 314 vertically stacking, substrate portion 316 and substrate portion 318 are as hanging downStraight transistorized drain region, channel region and source area. In addition, DRAM500 more comprises an electric capacity 312, in electrical contact hanging downStraight transistorized source area (substrate portion 318). Bit line contact thing 208 that it should be noted that buried bit lines 250 only withBe positioned at drain region (substrate portion 314) contact of one side, so the gate of each vertical transistor is by being positioned at vertical crystalA pair of directly over the drain region (substrate portion 314) of pipe buries character line 244 and is away from one of above-mentioned buried bit lines 250Individual auxiliary character line 244a forms.
Fig. 2 a, Fig. 2 b to Figure 13 a, Figure 13 b system show the manufacture of the dynamic random access memory of one embodiment of the inventionThe generalized section of method, wherein Fig. 2 a～Figure 13 a is the profile along the A-A ' tangent line of Fig. 1 a, and Fig. 2 b～Figure 13 bFor the profile of the B-B ' tangent line along Fig. 1 a. As shown in Fig. 2 a, Fig. 2 b, first, provide a substrate 200. At thisIn a bright embodiment, substrate 200 can be silicon substrate. In other embodiments, can utilize SiGe (SiGe), bulk partly to leadBody (bulksemiconductor), strain semiconductor (strainedsemiconductor), compound semiconductor (compoundSemiconductor), silicon-on-insulator (silicononinsulator, SOI), or other conventional semiconductor substrates are as basePlate 200. The implantable p-type of substrate 200 or N-shaped admixture, need to change its conduction type for design. Afterwards, can profitOn substrate 200, cover one the 0th felt pad 100 with chemical vapour deposition technique (CVD), it is as the follow-up substrate that is formed atThe etching hard mask of the first groove in 200. In an embodiment of the present invention, the 0th felt pad 100 can be silicon nitride.
Then, please refer to Fig. 2 a, Fig. 2 b, can utilize photoetching and etching manufacturing process, patterning the 0th felt pad 100,And define the formation position of the first groove 412. Then, can carry out an etching manufacturing process, the 0th exhausted with patterningEdge pad 100, as etching hard mask, forms parallel to each other along first direction 410 as shown in Figure 1 in substrate 200The first groove 412. Then,, respectively at forming a buried bit lines 250 in each first groove 412, it comprises a bit lineContactant 208, a sidewall 414a who is arranged at the first groove 412 bottoms along first direction 410 is upper, one first felt pad202, compliance covers sidewall 414a, 415a and a bottom surface 416 of the first groove 412 bottoms, and in abutting connection with bit line contactant208, and one first conducting objects 207, fill the first groove 412 bottoms, and cover the first felt pad 202 and bit line connectsTouch thing 208. In an embodiment of the present invention, the first conducting objects 207 comprises one first resistance barrier bed course 204 and one first metalBar 206, wherein the first resistance barrier bed course 204 is to be formed in the first groove 412, and covers the first felt pad 202With bit line contact thing 208, and the first metal strip thing 206 is to fill the first groove 412 bottoms, and covers the first resistance barrier padLayer 204. In an embodiment of the present invention, the first felt pad 202 can comprise monoxide, mononitride or its combination, theOne resistance barrier bed course can comprise a layered structure, and its material comprises titanium, titanium nitride or its combination, and bit line contact thing 208 canComprise DOPOS doped polycrystalline silicon. In an embodiment of the present invention, can be by ionic-implantation or by the admixture of bit line contact thing 208Diffuse to the mode of substrate 200, in substrate 200, form the diffusion region 210 in abutting connection with bit line contactant 208 sidewalls. At thisInvent in an embodiment, diffusion region 210 is positioned at substrate portion 314 (drain region) as shown in Figure 1a, and it can be as buryingThe diffused junction (diffusionjunction) of the drain electrode of bit line and vertical transistor, and the first conducting objects 207 is by bit lineContactant 208 and diffusion region 210 are electrically connected to the drain electrode of vertical transistor.
Refer again to Fig. 2 a, Fig. 2 b, after forming buried bit lines 250, can utilize chemical vapour deposition technique (CVD) or thingReason vapour deposition process (PVD), compliance form one second felt pad 212, cover the first groove 412 tops sidewall 414b,415b, the end face 201 of buried bit lines 250 and the 0th felt pad 100. Then, can utilize for example high density plasma enhanced chemical gasThe depositional mode of phase sedimentation (HDP-CVD) and follow-up etch-back (etchingback) step, with in the first groove 412Middle formation the first insulant 214, its cover part second felt pad 212. In an embodiment of the present invention, the first insulant214 and second felt pad 212 be different materials, for instance, in the time that the first insulant 214 is oxide, second is exhaustedEdge pad 212 is nitride.
Then, please refer to Fig. 3 a, Fig. 3 b, in an embodiment of the present invention, must will be positioned at the side on the first groove 412 topsThe thickness reduction of the second felt pad 212 of wall 414b, 415b, being beneficial to can be in the first groove 412 extra formation canThe a pair of auxiliary character line that buries character line with follow-up formation. As shown in Figure 3 a, 3 b, can utilize for example wet etching sideThe thinning manufacturing process of formula, removes the second insulating blanket that part is not covered by the first insulant 214, and thinning is positioned at firstThe thickness of the second insulating blanket of sidewall 414b, the 415b on groove 412 tops. In an embodiment of the present invention, can selectThe etchant that the first insulant 214 is had to high etching selectivity, can not damage while being beneficial to remove part the second insulating blanketThe first insulant 214. After thinning manufacturing process, the second felt pad system not covered by the first insulant 214 forms theTwo felt pad 212a, and be positioned at the thickness of the second felt pad 212a of sidewall 414b, the 415b on the first groove 412 topsT can be between 1nm～10nm.
Then, please refer to Fig. 4 a, Fig. 4 b, the depositional mode of recycling for example spin-coating method (spin-on) and follow-up returningEtching (etchingback) step forms a high K dielectric matter 216 on the first insulant 214, and its end face is lowIn the end face 201 of the 0th felt pad 100. In an embodiment of the present invention, high K dielectric matter 216 is at the first grooveHeight and position in 412 system, with follow-up to bury character line in another groove formation a pair of identical, is beneficial to follow-up replacement Gao JieThe auxiliary character line that electric constant dielectric medium 216 positions form can be connected to and bury character line.
Then, refer again to Fig. 4 a, Fig. 4 b, recycling for example high density plasma enhanced chemical vapor deposition method (HDP-CVD)Depositional mode, comprehensive formation one second insulating barrier 218, fills the first groove 412 and covered substrate 200, Qi ZhongOne end face of two insulating barriers 218 is essentially a flat surfaces. In an embodiment of the present invention, the second felt pad 212a,The material of the first insulant 214 and the second insulating barrier 218 can comprise monoxide, mononitride or its combination, Qi ZhongOne insulant 214 and the second insulating barrier 218 can be identical material, the first insulant 214 and the second insulating barrier 218Material is all different from the material of the second felt pad 212a. For example the first insulant 214 and the second insulating barrier 218 are all oxidationThing, and the second felt pad 212a is nitride.
The generation type of the second groove 422 is then described, as shown in Figure 1a, the first groove 412 and the second groove 422 areBe designed to setting intersected with each other. Please refer to Fig. 5 a, Fig. 5 b, can utilize chemical vapour deposition technique (CVD), in the second insulationOn layer 218, sequentially form a carbon hard mask layer 220 and mononitride hard mask layer 222. Afterwards, can utilize coating (coating)Mode, comprehensive formation one photoresistance, recycling one is buried character linear light cover and is carried out a lithographic fabrication processes, with along second partyTo a plurality of photoresistance patterns 224 of 420 formation. In an embodiment of the present invention, carbon hard mask layer 220, nitride hard maskLayer 222 is the hard mask as the etching manufacturing process of the second groove 422 of formation tool high-aspect-ratio, in order to avoid etchingThe damage during manufacturing process, substrate 200 and the 0th felt pad 100 surfaces being caused.
Then, please refer to Fig. 6 a, Fig. 6 b, carry out for example one of dry ecthing anisotropic etching step, remove not by photoresistanceThe nitride hard mask layer 222 that pattern 224 covers is to form nitride hard mask pattern (figure does not show), now photoresistance pattern224 can be removed during manufacturing process. Afterwards,, enter as etching hard mask taking nitride hard mask pattern (figure does not show)For example one of dry ecthing anisotropic etching step of row, removes that not to be nitrided the carbon that thing hard mask pattern (figure do not show) covers hardMask layer 220 is to form carbon hard mask pattern 220a, and now nitride hard mask pattern can be removed during manufacturing process.Then, taking carbon hard mask pattern 220a as etching hard mask, carry out for example one of dry ecthing anisotropic etching step, moveExcept the 0th felt pad 100, the second insulating barrier 218 and the substrate 200 that are not covered by carbon hard mask pattern 220a are (as Fig. 6 bShown in). Because the first groove 412 and the second groove 422 are to be designed to setting intersected with each other, so forming the second grooveDuring 422 etching manufacturing process, also can remove and be arranged in the first groove 412 and do not covered by carbon hard mask pattern 220aThe first insulant 214, high K dielectric matter 216, until expose not first exhausted by those photoresistance pattern coversTill edge thing 214, to form the second groove 422 along second direction 420 in substrate 200, wherein as shown in Figure 6 b,Part substrate 200 plates come out from the bottom surface 423 of the second groove 422. As shown in Fig. 1, Fig. 6 a, Fig. 6 b, firstGroove 412 and the setting intersected with each other of the second groove 422, and the bottom surface 423 of the second groove 422 can design be positioned at the first ditchThe top of the bottom surface 416 of groove 412, but not higher than the bottom surface of high K dielectric matter 216, follow-up in second to guaranteeWhat groove 422 sidewalls formed bury, and character line can be connected to replaces auxiliary that high K dielectric matter 216 positions formCharacter line.
Then, please refer to Fig. 7 a, Fig. 7 b, can utilize dry ecthing mode, remove carbon hard mask pattern 220a.
Then, please refer to Fig. 8 a, Fig. 8 b, can utilize dilute hydrofluoric acid (DHF) to carry out a clean manufacturing process, to removeBe positioned at for example native oxide (nativeoxide) on the sidewall 230 of the second groove 422, and remove the first groove simultaneouslyHigh K dielectric matter 216 in 412, and expose the part on upper portion side wall 414b, the 415b of the first grooveTwo felt pad 212a.
Then, please refer to Fig. 9 a, Fig. 9 b, can carry out a wet etching manufacturing process, remove the second felt pad coming out212a so that substrate 200 from the top of the first groove 412 pair of sidewalls 414b, 415b part come out, with shapeBecome by pair of sidewalls 414b, 415b, the first insulant 214 and the second insulation out of the upper exposed of the first groove 412The holes 226 that layer 218 surrounds, the wherein upper exposed of the first groove 412 pair of sidewalls 414b, 415b outTwo ends connect respectively the pair of sidewalls 230 of the second groove 422. In this step, because remove final form dynamically withNear nitride (that is the high K dielectric that comes out shown in Fig. 8 a, Fig. 8 b existing the passage of machine access memoryMatter 216 and the second felt pad 212a), the passage that therefore can improve existing dynamic random access memory is neighbouring because existingSilicon nitride and cause element critical voltage decline cause electric leakage problem.
Then, please refer to Figure 10 a, Figure 10 b, utilize for example thermal oxidation method (thermaloxidation), in the second groove 422Pair of sidewalls 230 and bottom surface 423, and in the upper exposed of the first groove 412 pair of sidewalls 414b, 415b outThe upper thermal oxide layer 232 that simultaneously forms. For convenience of description, in pair of sidewalls 230 and the bottom surface of the second groove 422The part thermal oxide layer forming on 423 is denoted as thermal oxide layer 232a (as shown in Figure 10 a), and upper in the first groove 412The part thermal oxide layer of the upper formation of pair of sidewalls 414b, 415b that portion comes out is denoted as thermal oxide layer 232b (as Figure 10 bShown in), notice that thermal oxide layer 232a and 232b are that same step forms.
Then, please refer to Figure 11 a, Figure 11 b, can utilize chemical vapour deposition technique (CVD) or atomic layer deposition method (ALD),Compliance forms one second resistance barrier bed course 234, extends and covers the second groove 422 from an end face 219 of the second insulating barrier 218Sidewall 230 and Figure 10 a shown in the sidewall in hole 226. Then, can utilize chemical vapour deposition technique (CVD), comprehensivelyProperty form a metal material 236, cover the second resistance barrier bed course 234, and fill the second groove 422 and hole 226. Afterwards,Can carry out the planarization manufacturing process of for example chemical mechanical milling method (CMP), with the surface of planarization material material 236.
Then, please refer to Figure 12 a, Figure 12 b, can utilize etch-back (etchingback) step, remove and be positioned at the second insulationThe metal material 236 of one end face 219 of layer 218 and the second resistance barrier bed course 234 (for example make the second groove 422 to certain depthIn metal material 236 and the end face of the second resistance barrier bed course 234 lower than substrate 200 surfaces). Then, utilize chemical gaseous phaseSedimentation (CVD) compliance forms one first insulation hard mask layer 110. In an embodiment of the present invention, the first insulation is hard hidesThe material of cover layer 110 can be silicon monoxide.
Then, please refer to Figure 13 a, Figure 13 b, utilizing the first insulation hard mask layer 110 is an etching hard mask, carries out exampleAs an anisotropic etching manufacturing process of dry ecthing, be arranged in the metal material 236, second of the second groove 422 to blockResistance barrier bed course 234 and thermal oxide layer 232a, until expose the mid portion of the bottom surface 423 of the second groove 422,To form formed by the second resistance barrier bed course and the second metal strip thing a pair of in the pair of sidewalls 230 in the second groove 422Bury character line 244. In embodiment as shown in Figure 13 b, sudden and violent when going out the mid portion of bottom surface 423 of the second groove 422After exposing, can continue again to carry out anisotropic etching manufacturing process a period of time (meaning crosses etching (overetching)),Until remove part substrate 200. Above-mentioned cross that etching system guarantees to form a pair of bury that character line 244 can not interconnect andProduce short circuit. As shown in Figure 12 a, form when burying character line 244, lie in the first groove 412, form one auxiliaryCharacter line 244a, is embedded in the hole 226 as shown in Fig. 9 a along first direction 410 as shown in Figure 1a. For sideJust for the purpose of explanation, through after above-mentioned manufacturing process, form part the second resistance barrier bed course and second that buries character line 244Metal strip thing is denoted as respectively the second resistance barrier bed course 234a and the second metal strip thing 236a (as shown in Figure 13 a), and structureBecome part the second resistance barrier bed course and the second metal strip thing of auxiliary character line 244a to be denoted as respectively the second resistance barrier bed course234b and the second metal strip thing 236b (as shown in Figure 13 b), note as shown in Figure 1 b, the second resistance barrier bed course 234a,234b is the different piece of same the second resistance barrier bed course, and the second metal strip thing 236a, 236b are same the second bonding jumperThe different piece of shape thing.
As shown in Fig. 1 b, Figure 13 a, the two ends of auxiliary character line 244a connect respectively and are positioned at channel region (substrate portion) 318The a pair of character line 244 that buries of both sides. To assist character line 244a to increase the channel width of vertical transistor, Jin ErzengAdd the On current of vertical transistor. And auxiliary character line 244a and the buried bit lines under it 250 are by the first insulating barrier 214Isolated each other with the second felt pad 212. In an embodiment of the present invention, auxiliary character line 244a is by from the second groove 422Pair of sidewalls 230 extend part the second resistance barrier bed course 234b and the part being embedded in the hole 226 as shown in Fig. 9 aThe second metal strip thing 236b forms, and wherein second of auxiliary character line 244b the resistance barrier bed course 234b system surrounds the second metalBar 236b. Afterwards, can comprehensive formation one insulating materials 240, cover the second insulating barrier 218 end face 219 andInsert the second groove 422. Then, then carry out follow-up manufacturing process, to form one embodiment of the invention as shown in Figure 1aDynamic random access memory 500.
Embodiment of the present invention system provides a kind of dynamic random access memory 500, due in order to form first of buried bit linesGroove and to bury the second groove of character line intersected with each other in order to form, thereby the thermal oxide that formation can be buried to character lineLayer, barrier layer and metal strip thing extend to the top of buried bit lines and form an auxiliary character line and completely cut off with buried bit lines,And this auxiliary character line, because of nearer apart from diffusion region, can significantly increase the conducting of the vertical transistor of dynamic random access memoryElectric current (on-current), thereby can not need to form larger diffusion region, (meaning is ascended the throne just to make the bit line contact thing of buried bit linesLine contactant) preferably linked with the inverting channel (inversionchannel) of vertical transistor generation. The invention processThe manufacture method of the dynamic random access memory 500 of example can remove near the nitrogenize existing passage in manufacturing processSilicon, near the silicon nitride because of existence of passage that therefore can improve existing dynamic random access memory causes element to faceBoundary's voltage drop causes the problem of electric leakage.
Although the present invention discloses as above with embodiment, so it is not in order to limit the present invention, anyly has the knack of this skill person,Without departing from the spirit and scope of the present invention, when doing a little change and retouching, therefore protection scope of the present invention is worked asDefined and be as the criterion with claim scope of the present invention.
Claims (16)
1. a dynamic random access memory, is characterized in that, described dynamic random access memory comprises:
One buried bit lines, is arranged at respectively in the bottom of one first groove extending along a first direction in a substrate;
The a pair of character line that buries, an offside of one second groove extending along a second direction in the substrate described in being arranged at respectivelyOn wall; And
One auxiliary character line, is arranged at another buried bit lines that is parallel to described buried bit lines along described first directionTop, and isolated with described another buried bit lines, the two ends of wherein said auxiliary character line connect respectively described to buryingHide character line, described buried bit lines and another described buried bit lines comprise respectively:
One bit line contact thing, is arranged at continuously along described first direction on a sidewall of the first described groove.
2. dynamic random access memory as claimed in claim 1, is characterized in that,
Described buried bit lines and another described buried bit lines comprise respectively:
One first insulating blanket, described sidewall and a bottom surface of the bottom of the first groove described in covering, and in abutting connection with describedBit line contact thing; And
One first conducting objects, fills the bottom of the first described groove, and covers the first described insulating blanket and described positionLine contactant.
3. dynamic random access memory as claimed in claim 2, is characterized in that, described dynamic random access memoryDevice more comprises:
One second insulating blanket, described sidewall and the described buried bit lines on the first groove top described in covering;
One first insulant, the first groove top described in filling part, and cover bottom surface and the bottom of described the second insulating blanketSidewall; And
One second insulating barrier, the first groove top described in filling part, and cover the upper portion side wall of described the second insulating blanket,Wherein said auxiliary character line is between the first described insulant and described the second insulating barrier.
4. dynamic random access memory as claimed in claim 2, is characterized in that, the first described conducting objects more comprises:
One first resistance barrier bed course, is formed in the first described groove, and covers the first described insulating blanket and described positionLine contactant; And
One first metal strip thing, fills the first described groove, and covers the first described resistance barrier bed course.
5. dynamic random access memory as claimed in claim 3, is characterized in that, each buries character line by a heatOxide layer Part I, one second resistance barrier bed course and a pair of the second metal strip thing form, wherein said thermal oxide layer firstPart covers this oppose side wall of the second described groove, and the second described resistance barrier bed course is between described thermal oxide layer FirstPoint and described the second metal strip thing between.
6. dynamic random access memory as claimed in claim 5, is characterized in that, described auxiliary character line is by a warmOxide layer Part II, extend from the described oppose side wall of the second described groove the portion that is embedded in another described buried bit linesThe second metal strip thing described in the second resistance barrier bed course and part described in point forms, wherein said thermal oxide layer Part IIDirectly cover the described sidewall on the top of the first described groove of another described buried bit lines, wherein said optional wordThe second described resistance barrier bed course of unit's line surrounds the second described metal strip thing.
7. dynamic random access memory as claimed in claim 6, is characterized in that, described thermal oxide layer Part IITwo ends connect respectively each and bury the described thermal oxide layer Part I of character line.
8. dynamic random access memory as claimed in claim 1, is characterized in that, the first described groove and describedThe setting intersected with each other of the second groove, and the described bottom surface of the second described groove is positioned at a bottom surface of described the first grooveTop.
9. a manufacture method for dynamic random access memory, is characterized in that, described dynamic random access memoryManufacture method comprises the following steps:
One substrate is provided;
In described substrate, form one first groove parallel to each other and another first groove along a first direction;
In the bottom of the first described groove and described another the first groove, form a buried bit lines and another buried bit lines,Wherein, described buried bit lines and another described buried bit lines comprise respectively:
One bit line contact thing, is arranged at continuously along described first direction on a sidewall of the first described groove;
In the top of another described the first groove, form a high K dielectric matter;
In described substrate, form one second groove along a second direction;
Remove described high K dielectric matter, and the pair of sidewalls on the top of another described the first groove is exposedCome;
In the pair of sidewalls of the second described groove, form a pair of character line that buries; And
On the upper exposed of another described the first groove this oppose side wall out, form an auxiliary character line, wherein saidThe two ends of auxiliary character line connect respectively this to burying character line.
10. the manufacture method of dynamic random access memory as claimed in claim 9, the manufacture of dynamic random access memoryMethod the first groove or described another first groove and described the second groove setting intersected with each other, and the second described grooveA bottom surface be positioned at the top of a bottom surface of the first described groove.
The manufacture method of 11. dynamic random access memory as claimed in claim 10, the system of dynamic random access memoryMaking method buried bit lines and another described buried bit lines comprise respectively:
One first insulating blanket, described sidewall and a bottom surface of the first groove bottom described in covering, and in abutting connection with described positionLine contactant; And
One first conducting objects, fills the first described groove bottom, and covers the first described insulating blanket and described bit lineContactant.
The manufacture method of 12. dynamic random access memory as claimed in claim 11, is characterized in that, described in formingBuried bit lines and another described buried bit lines more comprise afterwards:
Compliance forms one second insulating blanket, covers the described sidewall on the first described groove top, the described position of buryingOne end face of line and described another buried bit lines and described substrate;
Form one second insulant, the second insulating blanket described in cover part, wherein said high K dielectric matter is coveredThe sidewall of the second insulating blanket described in the second insulant that lid is described and part; And
Remove not by the second insulating blanket described in the part of the second described insulant covering.
The manufacture method of 13. dynamic random access memory as claimed in claim 12, is characterized in that, described in formingAfter high K dielectric matter, more comprise:
Comprehensive formation 1 the 3rd insulating barrier, fills the first described groove and covers described substrate, and the wherein said the 3rdOne end face of insulating barrier is essentially a flat surfaces.
The manufacture method of 14. dynamic random access memory as claimed in claim 13, is characterized in that, described in formingThe second groove more comprises:
On the 3rd described insulating barrier, sequentially form a carbon hard mask layer and mononitride hard mask layer;
Utilize one to bury character linear light cover, form and form a plurality of photoresistance patterns along described second direction;
Carry out an anisotropic etching step, remove not by the described nitride hard mask layer of described photoresistance pattern covers,Described carbon hard mask layer, the 3rd described insulating barrier, described substrate, described high K dielectric matter, until sudden and violentExpose not by till the second described insulant of described photoresistance pattern covers, wherein the described substrate of part is from described theCome out in the described bottom surface of two grooves; And
Photoresistance pattern described in removing, described nitride hard mask layer and described carbon hard mask layer.
The manufacture method of 15. dynamic random access memory as claimed in claim 14, is characterized in that, described in removingHigh K dielectric matter, and this oppose side wall on the top of another described the first groove is come out comprise:
Carry out a clean manufacturing process, remove described high K dielectric matter, and expose the second described insulation of partBed course;
Carry out a wet etching manufacturing process, remove the second insulating blanket described in the part coming out, to form by describedThis oppose side wall out of the upper exposed of another the first groove, described the second insulant and the 3rd described insulating barrier surroundOne hole, second described in the two ends of the upper exposed of wherein said another the first groove this oppose side wall out connect respectivelyThis oppose side wall of groove.
The manufacture method of 16. dynamic random access memory as claimed in claim 15, is characterized in that, forms this to buryingHiding character line more comprises:
In the upper exposed of this oppose side wall of the second described groove, described bottom surface and described another the first groove outOn this oppose side wall, form a thermal oxide layer;
Compliance forms one second resistance barrier bed course, extends and covers the second described groove from an end face of the 3rd described insulating barrierThis oppose side wall and the sidewall in described hole, and cover described thermal oxide layer;
Comprehensive formation one metal material, covers the second described resistance barrier bed course and fills the second described groove and described skyCave; And
Remove the described metal material on the described end face that is positioned at the 3rd described insulating barrier, the second described resistance barrier padLayer, and part is positioned at the described metal material of the second groove mid portion, the second described resistance barrier bed course and describedThermal oxide layer, until expose a mid portion of the described bottom surface of the second described groove.
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| CN113053897B (en) * | 2021-03-04 | 2022-06-17 | 长鑫存储技术有限公司 | Memory and preparation method thereof |
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| US6537870B1 (en) * | 2000-09-29 | 2003-03-25 | Infineon Technologies Ag | Method of forming an integrated circuit comprising a self aligned trench |
| CN1819205A (en) * | 2004-11-30 | 2006-08-16 | 因芬尼昂技术股份公司 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array |
| CN102034759A (en) * | 2009-09-30 | 2011-04-27 | 海力士半导体有限公司 | Semiconductor device with buried bit lines and fabrication method thereof |
| TW201118984A (en) * | 2009-11-19 | 2011-06-01 | Taiwan Memory Company | Buried bit lines and single side bit line contact process and scheme |
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| TWI368315B (en) * | 2008-08-27 | 2012-07-11 | Nanya Technology Corp | Transistor structure, dynamic random access memory containing the transistor structure, and method of making the same |
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| US6537870B1 (en) * | 2000-09-29 | 2003-03-25 | Infineon Technologies Ag | Method of forming an integrated circuit comprising a self aligned trench |
| CN1819205A (en) * | 2004-11-30 | 2006-08-16 | 因芬尼昂技术股份公司 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array |
| CN102034759A (en) * | 2009-09-30 | 2011-04-27 | 海力士半导体有限公司 | Semiconductor device with buried bit lines and fabrication method thereof |
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