CN102880217A - Stabilized power circuit used in high-voltage direct current-direct current (DC-DC) converter - Google Patents

Abstract

The invention discloses a stabilized power circuit used in a high-voltage direct current-direct current (DC-DC) converter. The problem of interference between internal power supplies of the conventional converter is mainly solved. The stabilized power circuit comprises a band-gap reference circuit (1), a soft start and bias circuit (2), a combined differential linear voltage stabilizer (3) and a power grouping isolation circuit (4), wherein the band-gap reference circuit (1) is used for generating current and soft starting voltage VSOFT; the soft start voltage VSOFT provides reference voltage for the combined differential linear voltage stabilizer (3) before reference voltage VBR is set, and rough internal analogue power VCCA is generated through the power grouping isolation circuit (4) to enable the band-gap reference circuit (1) to work; after the reference voltage VBG is set, the combined differential linear voltage stabilizer (3) automatically switches the reference voltage from the soft start voltage VSOFT to the reference voltage VBG to generate an accurate voltage signal VCC, and transmits the VCC to the power grouping isolation circuit (4); and by the conversion of the power grouping isolation circuit (4), four paths of non-interfering internal power are output, and are supplied to the analogue module, the digital module, a power module and a bootstrap capacitor in the converter. The internal power is non-interfering when a chip normally works.

Description

Be applied to the voltage-stabilized power supply circuit of high pressure DC-DC converter inside

Technical field

The invention belongs to the electronic circuit technology field, relate to voltage-stabilized power supply circuit, can be used in the high pressure DC-DC converter.

Background technology

The integrated DC-DC converter of switching mode makes it become the preferred option of power management in automobile electronics owing to have very high efficient.But the application requirements of the wide input voltage of automotive electronics and wide loading range has brought new challenge to the design of converter.To general high pressure DC-DC converter, all need to have two power supplys of height, wherein high input power is that internal high pressure drives and the correlation module power supply, and the low pressure internal electric source then is inner low-voltage module power supply, so just need to produce the power supply that a high pressure turns low pressure at chip internal.

Fig. 1 has shown the system chart of pulse-length modulation Peak Current Mode high pressure Buck DC-DC, is chip internal structure in the dotted line frame wherein, and other is peripheral circuit.Wherein the mimic channel such as error amplifier EA, PWM comparer needs constant low-tension supply voltage in the chip normal operation; Low side drives Low Side Driver constant power module needs larger transient current; The digital modules such as logic Logic can allow supply voltage that the shake of hundreds of millivolt is arranged; At NMOS pipe MN ₂During unlatching, low-tension supply will be given bootstrap capacitor C _BSTCharge, to guarantee NMOS pipe MN ₁Normal operation, because this bootstrap capacitor is generally in the nF level, charged electrical fails to be convened for lack of a quorum larger, therefore system needs several groups of different internal power source voltage VCCA, VCCD, VCCP, VCCB respectively to the simulation part, numerical portion, power section and bootstrap capacitor power supply, these several groups of supply voltages need to be accomplished good isolation simultaneously, to reduce mutual interference.

The conventional high-tension power management chip adopts the breakdown reverse voltage of voltage stabilizing diode to provide power supply to benchmark and rear class error amplifier usually.Fig. 2 has provided the stabilized voltage supply structure of conventional high-tension power management chip inside, high input voltage power supply V _INBe connected to feedback voltage V by resistance R 1 and zener diode D1 _FBResistance R 1 is connected to NPN pipe Q1, the emitter output voltage V of NPN pipe Q1 with the common port of zener diode D1 _REG, and provide power supply for benchmark and error amplifier A; The in-phase input end of error amplifier A and inverting input connect respectively reference voltage and feedback voltage V _FBThe output terminal of error amplifier A links to each other with the adjustment pipe; Adjust pipe and be connected to ground by feedback resistance R2 and R3, the common port voltage of feedback resistance R2 and feedback resistance R3 is V _FB, and be connected to error amplifier A, thus consist of a negative feedback structure; Adjust the common port of pipe and feedback resistance R2 as the output of inner mu balanced circuit circuit, output stabilized voltage supply V _OTraditional interior voltage-stabilized power supply structure has only produced an internal electric source, be simultaneously chip internal simulation part, numerical portion, power section and bootstrap capacitor power supply, therefore can not effectively isolate the interference between each internal electric source, and owing to be subject to the restriction of technique, zener diode is not easy of integration yet in integrated circuit.

Summary of the invention

The object of the invention is to for existing high pressure DC-DC converter inside low-voltage circuit powerup issue, a kind of voltage-stabilized power supply circuit that is applied to high pressure DC-DC converter inside has been proposed, mutually isolate to produce four groups, non-interfering chip internal stabilized voltage supply, give respectively analog module, digital module, power model and bootstrap capacitor power supply, so that each internal electric source is separate when chip works, do not interfere with each other.

For achieving the above object, the present invention includes for generation of the zero-temperature coefficient reference voltage V _BGWith bias voltage V _BIASBand-gap reference circuit 1, it is characterized in that: also comprise soft starting circuit 2, composite difference linear voltage regulator 3 and power supply grouping buffer circuit 4;

Described soft and biasing circuit 2 are used to interior voltage-stabilized power supply that bias current I is provided _BIASWith soft voltage V _SOFT, and be connected to composite difference linear voltage regulator 3;

Described composite difference linear voltage regulator 3 is used for finishing soft voltage V of soft and biasing circuit 2 inputs _SOFTReference voltage V with band-gap reference circuit 1 input _BGSwitching between the two, and output voltage signal VCC and bias current signal I _S2To power supply grouping buffer circuit 4;

Described power supply grouping buffer circuit 4, with the voltage signal VCC of composite difference linear voltage regulator 3 input be converted to four groups mutually isolate, non-interfering internal electric source VCCA, VCCD, VCCP and VCCB, be respectively analog module, digital module, power model and the bootstrap capacitor power supply of high pressure DC-DC converter inside.

Above-mentioned voltage-stabilized power supply circuit, wherein soft and biasing circuit 2, comprise that withstand voltage is greater than high voltage PMOS pipe M9 ~ M13 of 12V between 5 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M8 of 5V between 8 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M14 ~ M16 of 12V between 3 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M17 ~ M20 and the resistance R 1 of 5V between 4 sources, the drain electrode;

Described low pressure PMOS pipe M6 ~ M8, its grid link to each other with self drain electrode respectively and consist of diode structure, and connect and be connected across high input voltage power supply V _INAnd between the drain electrode of high pressure NMOS pipe M14;

Described high pressure NMOS pipe M14, its grid and source electrode are connected to ground jointly;

Described low pressure PMOS pipe M5, its source electrode and high input voltage power supply V _INLink to each other; Drain electrode links to each other with the grid of low pressure PMOS pipe M8; Its grid links to each other with the grid of low pressure PMOS pipe M1 ~ M4;

Described high voltage PMOS pipe M13, its source electrode and high input voltage power supply V _INLink to each other; Its grid links to each other with the drain electrode of low pressure PMOS pipe M5; Its drain electrode links to each other with the source electrode of low pressure NMOS pipe M17;

Described low pressure PMOS pipe M1 ~ M4 and high voltage PMOS pipe M9 ~ M12 consist of the common-source common-gate current mirror structure; The drain electrode of high voltage PMOS pipe M9 and M10 links to each other with the drain electrode of low pressure NMOS pipe M17 and the drain electrode of high pressure NMOS pipe M16 respectively; The drain electrode of high voltage PMOS pipe M12 is as the first output terminal of soft and biasing circuit 2, output offset electric current I _BIASThe drain electrode of high voltage PMOS pipe M11 links to each other with the drain electrode of low pressure NMOS pipe M20; This low pressure NMOS manages M20, and its source electrode is connected to ground; Its grid links to each other with the drain electrode of self, and as the second output terminal of soft and biasing circuit 2, exports the soft voltage V that opens _SOFT

Described low pressure NMOS pipe M17, its drain electrode formation diode structure that links to each other with self grid; Its source electrode links to each other with the drain electrode of high pressure NMOS pipe M15;

Described high pressure NMOS pipe M15, M16 and low pressure NMOS pipe M18, M19 consist of the common-source common-gate current mirror structure; The source electrode of low pressure NMOS pipe M18 is connected to ground; The source electrode of low pressure NMOS pipe M19 is connected to ground by resistance R 1.

Above-mentioned voltage-stabilized power supply circuit, wherein the composite difference linear voltage regulator 3, comprise current mirror 31, withstand voltage is greater than high voltage PMOS pipe M8 ~ M10 of 12V between 3 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M7 of 5V between 7 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M11, the M12 of 12V between 2 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M13 ~ M15 of 5V between 3 sources, the drain electrode;

Described current mirror 31 is with the bias current I of soft and biasing circuit 2 inputs _BIASBe converted to the two-way electric current I _S1And I _S2I wherein _S1Flow into the drain electrode of high voltage PMOS pipe M8, for composite difference linear voltage regulator 3 provides tail current; I _S2Flow into power supply grouping buffer circuit 4;

Described low pressure PMOS pipe M4 ~ M6 and high voltage PMOS pipe M8 ~ M10 consist of the common-source common-gate current mirror structure; The source electrode of low pressure PMOS pipe M4 ~ M6 all with high input voltage power supply V _INLink to each other; The drain electrode of high voltage PMOS pipe M9 links to each other with the source electrode of low pressure PMOS pipe M7; The drain electrode of described high voltage PMOS pipe M10 links to each other with the drain electrode of high pressure NMOS pipe M12;

Described low pressure PMOS pipe M7, its grid links to each other with the drain electrode of self and consists of diode structure, and is connected to the source electrode of low pressure PMOS pipe M1 and M3;

Described low pressure PMOS pipe M1, M2 and M3 consist of the composite difference input to structure; Its grid respectively with the reference voltage V of band-gap reference circuit 1 input _BG, 2 inputs of soft and biasing circuit soft voltage V _SOFTAnd feedback voltage V _FBLink to each other; The drain electrode of low pressure PMOS pipe M1 links to each other with the source electrode of low pressure PMOS pipe M2;

Described low pressure NMOS pipe M13 and M14, its grid link to each other and consist of current mirror; Its drain electrode links to each other with the drain electrode of low pressure PMOS pipe M3 with low pressure PMOS pipe M2 respectively; Its source electrode is connected to ground jointly;

Described high pressure NMOS pipe M12, its grid and self the drain electrode formation diode structure that links to each other, and as the output terminal of composite difference linear voltage regulator 3, output voltage signal VCC; Its source electrode links to each other with the drain electrode of low pressure NMOS pipe M15;

Described low pressure NMOS pipe M15, its grid links to each other with the drain electrode of low pressure PMOS pipe M2; Its source electrode is connected to ground;

Described high pressure NMOS pipe M11, its drain electrode is connected to high input voltage power supply V _INIts grid connects voltage signal VCC.

Above-mentioned voltage-stabilized power supply circuit, power supply grouping buffer circuit 4 wherein, comprise that withstand voltage is greater than high voltage PMOS pipe M6 ~ M8 of 12V between 3 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M5 of 5V between 5 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M9 ~ M15 of 12V between 7 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M16 ~ M20 and 1 triode Q1 of 5V between 5 sources, the drain electrode;

Described high pressure NMOS pipe M9 ~ M12, its grid all are connected with the VCC of composite difference linear voltage regulator 3 inputs; Its drain electrode all with high input voltage voltage V _INLink to each other; Its source electrode links to each other with the drain electrode of low pressure NMOS pipe M16 ~ M19 respectively;

The bias voltage V that described low pressure NMOS pipe M16 ~ M19, its grid all input with band-gap reference circuit 1 _BIASLink to each other; Its source electrode all is connected to ground; The drain electrode of low pressure NMOS pipe M16 is exported internal simulation power supply VCCA as the first output terminal of power supply grouping buffer circuit 4; The drain electrode of low pressure NMOS pipe M17 is exported internal digital power supply VCCD as the second output terminal of power supply grouping buffer circuit 4; The drain electrode of low pressure NMOS pipe M18 and M19 links to each other with the grid of low pressure PMOS pipe M4 and M5 respectively;

Described low pressure PMOS pipe M1 ~ M3 and high voltage PMOS pipe M6 ~ M8 consist of the common-source common-gate current mirror structure; The source electrode of low pressure PMOS pipe M1 ~ M3 all with high input voltage power supply V _INLink to each other; The electric current I of the drain electrode of high voltage PMOS pipe M6 and 3 inputs of composite difference linear voltage regulator _S2Link to each other; The drain electrode of high voltage PMOS pipe M7 links to each other with the emitter of triode Q1; The drain electrode of high voltage PMOS pipe M8 links to each other with the source electrode of low pressure PMOS pipe M5; The drain electrode of this low pressure PMOS pipe M5 is connected to ground;

Described triode Q1, its base stage links to each other with the source electrode of low pressure PMOS pipe M4; Its collector links to each other with the drain electrode of low pressure PMOS pipe M4, and is connected to ground;

Described high pressure NMOS pipe M15, its drain electrode and high input voltage power supply V _INLink to each other; Its grid links to each other with the source electrode of low pressure PMOS pipe M5; Its source electrode is exported internal power power supply VCCP as the 3rd output terminal of power supply grouping buffer circuit 4;

Described low pressure NMOS pipe M20, its drain electrode links to each other with internal power power supply VCCP; The bias voltage V of its grid and band-gap reference circuit 1 input _BIASLink to each other; Its source electrode is connected to ground;

Described high pressure NMOS pipe M13 and M14, its grid links to each other, and is connected to the emitter of triode Q1; Its source electrode links to each other; The drain electrode of high pressure NMOS pipe M14 is exported inner bootstrap power supply VCCB as the 4th output terminal of power supply grouping buffer circuit 4.

The present invention compared with prior art has the following advantages:

1. the present invention has realized soft voltage V well owing to added soft and biasing circuit and composite difference input linear voltage regulator _SOFTWith the zero-temperature coefficient reference voltage V _BGSwitching, effectively solved the starting problem of internal electric source.

2. the power supply among the present invention grouping buffer circuit is by adopting grouping lifting V _GSThe method of voltage has produced four groups and has mutually isolated, and does not interfere with each other and with the internal electric source of certain load capacity, has suppressed well the phase mutual interference between each internal electric source.

Description of drawings

Fig. 1 is the system chart of pulse-length modulation Peak Current Mode high pressure Buck type DC-DC converter;

Fig. 2 is the stabilized voltage supply structural drawing of conventional high-tension power management chip inside;

Fig. 3 is high pressure DC-DC converter inside voltage-stabilized power supply circuit block diagram of the present invention;

Fig. 4 is soft starting circuit schematic diagram of the present invention;

Fig. 5 is that composite difference of the present invention is inputted linear voltage regulator circuit schematic diagram;

Fig. 6 is power supply grouping buffer circuit schematic diagram.

Embodiment

The invention will be further described below in conjunction with accompanying drawing and embodiment.

With reference to Fig. 3, voltage-stabilized power supply circuit of the present invention comprises: band-gap reference circuit 1, soft and biasing circuit 2, composite difference input linear voltage regulator 3 and power supply grouping buffer circuit 4, wherein: described band-gap reference circuit 1, for generation of the reference voltage V of zero-temperature coefficient _BGWith bias voltage V _BIAS, this reference voltage V _BGBe connected to composite difference input linear voltage regulator 3, the composite difference input linear voltage regulator 3 during for normal operation provides reference voltage, this bias voltage V _BIASBe connected to power supply grouping buffer circuit 4, for part low pressure NMOS in the power supply grouping buffer circuit 4 provides voltage bias; Described soft and biasing circuit 2 are for generation of soft voltage V _SOFTWith bias current I _BIAS, and be connected to composite difference input linear voltage regulator 3, this soft voltage V _SOFTComposite difference input linear voltage regulator 3 during for startup provides reference voltage; Bias current I _BIASFor composite difference input linear voltage regulator 3 provides current offset; Described composite difference input linear voltage regulator 3, its first input end be connected input end and connect respectively soft voltage V of soft and biasing circuit 2 inputs _SOFTWith bias current I _BIAS, the reference voltage V of its 3rd input end connecting band gap reference circuit 1 input _BG, be used for finishing soft voltage V _SOFTWith reference voltage V _BGSwitching between the two, thus the starting problem of voltage-stabilized power supply circuit solved, and output voltage signal VCC and current signal I _S2To power supply grouping buffer circuit 4; Described power supply grouping buffer circuit 4, its first input end be connected input end and connect respectively voltage signal VCC and the current signal I of 3 inputs of composite difference input linear voltage regulator _S2, the bias voltage V of its 3rd input end and band-gap reference circuit 1 input _BIASLink to each other, this power supply grouping buffer circuit 4 with voltage signal VCC be converted to four groups mutually isolate, non-interfering internal electric source VCCA, VCCD, VCCP and VCCB, be respectively analog module, digital module, power model and the bootstrap capacitor power supply of high pressure DC-DC converter inside.

With reference to Fig. 4, soft and biasing circuit 2 of the present invention, comprise that withstand voltage is greater than high voltage PMOS pipe M9 ~ M13 of 12V between 5 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M8 of 5V between 8 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M14 ~ M16 of 12V between 3 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M17 ~ M20 and the resistance R 1 of 5V between 4 sources, the drain electrode;

Described low pressure PMOS pipe M6 ~ M8, its grid link to each other with self drain electrode respectively and consist of diode structure, and connect and be connected across between the drain electrode of high input voltage power supply VIN and high pressure NMOS pipe M14;

Described high pressure NMOS pipe M14, its grid and source electrode are connected to ground jointly;

Described high voltage PMOS pipe M13, its source electrode links to each other with high input voltage power supply VIN; Its grid links to each other with the drain electrode of low pressure PMOS pipe M5; Its drain electrode links to each other with the source electrode of low pressure NMOS pipe M17;

Described low pressure PMOS pipe M5, its source electrode and high input voltage power supply V _INLink to each other; Drain electrode links to each other with the grid of low pressure PMOS pipe M8; Its grid links to each other with the grid of low pressure PMOS pipe M1, M2, M3 and M4;

Above-mentioned low pressure PMOS pipe M5 ~ M8, high voltage PMOS pipe M13, M14 consists of start-up circuit, wherein M14 is the high pressure NMOS pipe, electric leakage by the high pressure NMOS pipe, the grid potential of high voltage PMOS pipe M13 is reduced, thereby raise the grid potential of pressing NMOS pipe M15, produce bias current so that back-end circuit is broken away from equilibrium state, low pressure PMOS pipe M5 raised the grid potential of high voltage PMOS pipe M13 by current mirror after bias current produced, turn-off M13, start-up course finishes, because start-up course is to finish by the electric leakage of high pressure NMOS, so start-up circuit consumes quiescent current hardly.

Described low pressure PMOS pipe M1 ~ M4, its source electrode is connected to high input voltage power supply V jointly _INIts drain electrode links to each other with the source electrode of high voltage PMOS pipe M9 ~ M12 respectively; Its grid links to each other, and is connected to the drain electrode of M1;

Described high voltage PMOS pipe M9 ~ M12, its grid links to each other, and is connected to M9; The drain electrode of high voltage PMOS pipe M9 and M10 links to each other with the drain electrode of low pressure NMOS pipe M17 and the drain electrode of high pressure NMOS pipe M16 respectively; The drain electrode of high voltage PMOS pipe M11 links to each other with the drain electrode of low pressure NMOS pipe M20; The drain electrode of high voltage PMOS pipe M12 is as the first output terminal of soft and biasing circuit 2, output offset electric current I _BIASTo composite difference input linear voltage regulator 3, for it provides current offset;

Above-mentioned low pressure PMOS pipe M1 ~ M4 and high voltage PMOS pipe M9 ~ M12 consist of the common-source common-gate current mirror structure, improve the Power Supply Rejection Ratio of soft and biasing circuit 2.

Described low pressure NMOS pipe M20, its source electrode is connected to ground; Its grid links to each other with the drain electrode of self, and as the second output terminal of soft and biasing circuit 2, exports the soft voltage V that opens _SOFTTo composite difference input linear voltage regulator 3; Soft voltage V _SOFTBefore bandgap voltage reference is set up, provide reference voltage to composite difference input linear voltage regulator 3, to produce rough internal simulation power supply VCCA bandgap voltage reference is set up, after the 1.2V bandgap voltage reference was set up, composite difference input linear voltage regulator 3 can be with reference to voltage voltage V from soft _SOFTAutomatically switch to bandgap voltage reference V _BG, to produce accurately 5V internal power source voltage.

Described low pressure NMOS pipe M17, its drain electrode formation diode structure that links to each other with self grid; Its source electrode links to each other with the drain electrode of high pressure NMOS pipe M15;

Described high pressure NMOS pipe M15 and M16, its source electrode link to each other with the drain electrode of low pressure NMOS pipe M19 with low pressure NMOS pipe M18 respectively; Its grid links to each other, and the drain electrode that is connected to M15 links to each other;

Described low pressure NMOS pipe M18 and M19, the source electrode of low pressure NMOS pipe M18 is connected to ground; The source electrode of low pressure NMOS pipe M19 is connected to ground by resistance R 1; Its grid links to each other, and is connected to the drain electrode of M18;

Above-mentioned high pressure NMOS pipe M15, M16 and low pressure NMOS pipe M18, M19 consist of the common-source common-gate current mirror structure, improve the Power Supply Rejection Ratio of soft and biasing circuit 2.

Above-mentioned low pressure PMOS pipe M1, M2, high voltage PMOS pipe M9, M10, high pressure NMOS pipe M15, M16 and low pressure NMOS pipe M18, M19 consist of bias current and produce structure, it adopts common-source common-gate current mirror structure mirror image can improve Power Supply Rejection Ratio, reduces channel-length modulation to the impact of bias current.Suppose low pressure NMOS pipe M18 and the wide appearance of M19 with, and the number of M19 be M18 K doubly because M18, the grid potential of M19 is identical, then can obtain formula 1):

$\sqrt{\frac{{2I}_{\mathrm{out}}}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}W/L}}+V_{\mathrm{THN}}=\sqrt{\frac{2I_{\mathrm{out}}}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\mathrm{KW}/L}}+V_{\mathrm{THN}}+I_{\mathrm{out}}{R}_1---1)$

V wherein _THNBe the threshold voltage of low pressure NMOS pipe, W is the grid width of M18, and L is the grid length of M18, μ _nBe electron mobility, C _OXBe unit area gate oxidation electric capacity.I _OUTBe the bias current that biasing circuit produces, ignore bulk effect, formula 2 is arranged):

$\sqrt{\frac{{2I}_{\mathrm{out}}}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}W/L}}(1-\frac{1}{\sqrt{K}})=I_{\mathrm{out}}{R}_1---2)$

By formula 2) can get,

$I_{\mathrm{out}}=\frac{2}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}W/L}\frac{1}{{R_1}^2}{(1-\frac{1}{\sqrt{K}})}^2---3)$

Therefore, after bias current generating circuit is set up stable operating point, the bias current of its generation basically with independent of power voltage.

With reference to Fig. 5, composite difference input linear voltage regulator 3 of the present invention, comprise current mirror 31, withstand voltage is greater than high voltage PMOS pipe M8 ~ M10 of 12V between 3 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M7 of 5V between 7 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M11, the M12 of 12V between 2 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M13 ~ M15 of 5V, 3 resistance R 1, R2, R3 and capacitor C 1 between 3 sources, the drain electrode;

Described current mirror 31 is with the bias current I of soft and biasing circuit 2 inputs _BIASBe converted to the two-way electric current I _S1And I _S2I wherein _S1Flow into the drain electrode of high voltage PMOS pipe M8, for composite difference linear voltage regulator 3 provides tail current; I _S2Flow into power supply grouping buffer circuit 4, for it provides current offset;

Described low pressure PMOS pipe M4 ~ M6, its source electrode all with high input voltage power supply V _INLink to each other; Its drain electrode links to each other with the source electrode of high voltage PMOS pipe M8 ~ M10 respectively; Its grid links to each other, and is connected to the drain electrode of M4;

Described high voltage PMOS pipe M8 ~ M10, its grid links to each other, and is connected to the drain electrode of M8; The drain electrode of high voltage PMOS pipe M9 links to each other with the source electrode of low pressure PMOS pipe M7; The drain electrode of described high voltage PMOS pipe M10 links to each other with the drain electrode of high pressure NMOS pipe M12;

Above-mentioned low pressure PMOS pipe M4 ~ M6 and high voltage PMOS pipe M8 ~ M10 consist of common-source common-gate current mirror, improve the Power Supply Rejection Ratio of composite difference linear voltage regulator 3.

Described low pressure PMOS pipe M7, its grid links to each other with the drain electrode of self and consists of diode structure, and is connected to the source electrode of low pressure PMOS pipe M1 and M3;

Described low pressure PMOS pipe M1 and M3, its grid respectively with the reference voltage V of band-gap reference circuit 1 input _BGAnd feedback voltage V _FBLink to each other; Its drain electrode links to each other with the source electrode of low pressure PMOS pipe M2 and the drain electrode of low pressure NMOS pipe M14 respectively;

Described low pressure PMOS pipe M2, soft voltage V of its soft of grid connection and biasing circuit 2 inputs _SOFTIts drain electrode utmost point links to each other with the drain electrode of low pressure NMOS pipe M13;

Above-mentioned low pressure PMOS pipe M1 ~ M3, the composite difference input of formation is to structure, in reference voltage V _BGBefore the foundation, by soft voltage V _SOFTReference voltage is provided; After reference voltage was set up, reference voltage automatically switched to reference voltage V _BG

Described low pressure NMOS pipe M13 and M14, its grid link to each other and consist of current mirror; Its source electrode is connected to ground jointly;

Described high pressure NMOS pipe M12, its grid and self the drain electrode formation diode structure that links to each other, and as the output terminal of composite difference linear voltage regulator 3, output voltage signal VCC; Its source electrode links to each other with the drain electrode of low pressure NMOS pipe M15;

Described low pressure NMOS pipe M15, its grid links to each other with the drain electrode of low pressure PMOS pipe M2; Its source electrode is connected to ground;

Described capacitor C 1 is connected with resistance R 1, and the drain electrode that is connected across low pressure NMOS pipe M15 links to each other with grid; Be used for loop compensation, to guarantee loop stability.

Described high pressure NMOS pipe M11, its drain electrode is connected to high input voltage power supply V _INIts grid connects voltage signal VCC; Its source electrode is connected to ground by resistance R 2 and resistance R 3; Resistance R 2 is V with the common port voltage of resistance R 3 _FBAnd be connected to the grid that low pressure PMOS manages M3, thereby consist of feedback loop.

This composite difference input linear voltage regulator, electric current I _BIASBy soft and biasing circuit 2 generations, for this linear voltage regulator provides bias current, in reference voltage V _BGBefore the foundation, by soft voltage V _SOFTReference voltage is provided, after reference voltage is set up, inputs structure by the composite difference that is formed by PMOS pipe M1 ~ M3, automatically switch to reference voltage V with reference to voltage _BGBecause reference voltage V _BGBe the zero-temperature coefficient voltage that is produced by band-gap reference circuit 1, the conducting state by negative feedback structure control high pressure NMOS pipe M11 can obtain stable accurately voltage VCC, and its value can be expressed as formula 4).

Wherein, V _GS1Poor for grid and the source voltage of high pressure NMOS pipe M11, by the value of resistance R 2, R3 is set, can obtain required output voltage values.Because supply voltage can change to 24V from 3V, so common-source common-gate current mirror has adopted high voltage bearing device.The composite difference input is received the source electrode that low pressure PMOS manages M7 to the substrate of M1 ~ M3, because body bias effect, the right threshold voltage of composite difference input will increase, and can guarantee that like this M1 ~ M3 is operated in the saturation region preferably.

With reference to Fig. 6, power supply grouping buffer circuit 4 of the present invention, comprise that withstand voltage is greater than high voltage PMOS pipe M6 ~ M8 of 12V between 3 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M5 of 5V between 5 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M9 ~ M15 of 12V between 7 sources, the drain electrode, withstand voltage is less than low pressure NMOS pipe M16 ~ M20 of 5V, 4 capacitor C 1 ~ C4 and 1 triode Q1 between 5 sources, the drain electrode;

Described high pressure NMOS pipe M9 ~ M12, its grid all are connected with the VCC of composite difference linear voltage regulator 3 inputs; Its drain electrode all with high input voltage voltage V _INLink to each other; Its source electrode links to each other with the drain electrode of low pressure NMOS pipe M16 ~ M19 respectively;

The bias voltage V that described low pressure NMOS pipe M16 ~ M19, its grid all input with band-gap reference circuit 1 _BIASLink to each other; Its source electrode all is connected to ground; The drain electrode of low pressure NMOS pipe M16 is as the first output terminal of power supply grouping buffer circuit 4, and output internal simulation power supply VCCA is connected with capacitor C 1 between this internal simulation power supply VCCA and the ground, is used for the filtering high fdrequency component; The drain electrode of low pressure NMOS pipe M17 is as the second output terminal of power supply grouping buffer circuit 4, and output internal digital power supply VCCD is connected with capacitor C 2 between this internal digital power supply VCCD and the ground, is used for the filtering high fdrequency component; The drain electrode of low pressure NMOS pipe M18 and M19 links to each other with the grid of low pressure PMOS pipe M4 and M5 respectively;

Described low pressure PMOS pipe M1 ~ M3, its source electrode all with high input voltage power supply V _INLink to each other; Its drain electrode links to each other with the source electrode of high voltage PMOS pipe M6 ~ M8 respectively; Its grid links to each other, and is connected to the drain electrode of M1;

Described high voltage PMOS pipe M6 ~ M8, its grid links to each other, and is connected to the drain electrode of M6; The electric current I of the drain electrode of high voltage PMOS pipe M6 and 3 inputs of composite difference linear voltage regulator _S2Link to each other; The drain electrode of high voltage PMOS pipe M7 links to each other with the emitter of triode Q1; The drain electrode of high voltage PMOS pipe M8 links to each other with the source electrode of low pressure PMOS pipe M5; The drain electrode of this low pressure PMOS pipe M5 is connected to ground;

Above-mentioned low pressure PMOS pipe M1 ~ M3 and high voltage PMOS pipe M6 ~ M8 consist of the common-source common-gate current mirror structure, are used for improving the Power Supply Rejection Ratio of power supply grouping buffer circuit 4.

Described triode Q1, its base stage links to each other with the source electrode of low pressure PMOS pipe M4; Its collector links to each other with the drain electrode of low pressure PMOS pipe M4, and is connected to ground;

Described high pressure NMOS pipe M15, its drain electrode and high input voltage power supply V _INLink to each other; Its grid links to each other with the source electrode of low pressure PMOS pipe M5; Its source electrode is as the 3rd output terminal of power supply grouping buffer circuit 4, and output internal power power supply VCCP is connected with capacitor C 3 between this internal power power supply VCCP and the ground, is used for the filtering high fdrequency component;

Described low pressure NMOS pipe M20, its drain electrode links to each other with internal power power supply VCCP; The bias voltage V of its grid and band-gap reference circuit 1 input _BIASLink to each other; Its source electrode is connected to ground;

Described high pressure NMOS pipe M13 and M14, its grid links to each other, and is connected to the emitter of triode Q1; Its source electrode links to each other; The drain electrode of high pressure NMOS pipe M14 is exported inner bootstrap power supply VCCB as the 4th output terminal of power supply grouping buffer circuit 4, is connected with capacitor C 4 between this inside bootstrap power supply VCCB and the ground, is used for the filtering high fdrequency component.

The voltage signal VCC of composite difference input linear voltage regulator 3 inputs through high pressure NMOS pipe M9 and M10, is converted to internal simulation power supply VCCA and internal digital power supply VCCD, and its expression formula is respectively:

VCCA=VCC-V _GS2 5）

VCCD=VCC-V _GS3 6）

Wherein, V _GS2And V _GS3Be respectively the grid of high pressure NMOS pipe M9 and M10 and the voltage difference between the source electrode.

With formula 4) substitution formula 5) and formula 6) can get:

$\mathrm{VCCA}=V_{\mathrm{BG}}(1+\frac{R2}{R3})+V_{\mathrm{GS}1}-V_{\mathrm{GS}2}---7)$

$\mathrm{VCCD}=V_{\mathrm{BG}}(1+\frac{R2}{R3})+V_{\mathrm{GS}1}-V_{\mathrm{GS}3}---8)$

In the less situation of internal simulation power supply VCCA and internal digital power supply VCCD load, approximately can think V _GS1With V _GS2, V _GS3Equate that the approximate voltage value that then can obtain internal simulation power supply VCCA and internal digital power supply VCCD is:

$\mathrm{VCCA}=V_{\mathrm{BG}}(1+\frac{R2}{R3})---9)$

$\mathrm{VCCD}=V_{\mathrm{BG}}(1+\frac{R2}{R3})---10)$

Because reference voltage V _BGThe zero-temperature coefficient voltage that is produced by band-gap reference circuit 1, so by changing the value of resistance R 2 and R3, can obtain stable accurately internal simulation power supply VCCA and internal digital power supply VCCD.

Because internal power power supply VCCP, the required load current of inner bootstrap power supply VCCB is larger, need to carry out shunt to it separately and isolates, in like manner, by lifting V _GSMethod, can obtain formula 11) and 12).

VCCP=VCC-V _GS4+V _GS5-V _GS6 11)

VCCB=VCC-V _GS7+V _GS8+V _BE-V _GD 12)

Wherein, V _GS4, V _GS5, V _GS6, V _GS7And V _GS8Be respectively the grid of metal-oxide-semiconductor M12, M5, M15, M11 and M4 and the voltage difference between the source electrode; V _BEBe the base stage of triode Q1 and the voltage difference between the emitter; V _GDBe the grid of metal-oxide-semiconductor M14 and the voltage difference between the drain electrode.The electric current that flows through low pressure NMOS pipe M16 ~ M17 and low pressure PMOS pipe M2, M3 rationally is set, when load current hour, convolution 4), formula 11) and formula 12), the approximate voltage value that can obtain internal power power supply VCCP and inner bootstrap power supply VCCB is:

$\mathrm{VCCP}=V_{\mathrm{BG}}(1+\frac{R2}{R3})---13)$

$\mathrm{VCCB}=V_{\mathrm{BG}}(1+\frac{R2}{R3})+V_{\mathrm{BE}}---14)$

When load current was larger, because high pressure NMOS pipe M15, the number of tubes of M14 was more and breadth length ratio is very large, so internal power power supply VCCP and inner bootstrap power supply VCCB are limited with load variations.Internal simulation power supply VCCA, internal digital power supply VCCD are set in typical case, internal power power supply VCCP is 5V, then inner bootstrap power supply VCCB is than the high V of 5V voltage _BE, this is the gate source voltage of upper power tube when improving chip operation, reduces the conducting resistance of upper power tube, improves the efficient of DC-DC converter.M14 is an inverted high pressure NMOS, is used for preventing the anti-power supply that is poured into of inner bootstrap power supply VCCB voltage.

Principle of work of the present invention is: during chip power, the start-up circuit in soft and the biasing circuit 2 is started working, and the biasing circuit of controlling in soft and the biasing circuit 2 starts, and produces bias current I _BIASWith soft voltage V _SOFTThis moment soft voltage V _SOFTAs the reference voltage of composite difference linear voltage regulator 3, and produce rough voltage signal VCC to power supply grouping buffer circuit 4; Rough voltage signal VCC exports rough internal simulation power supply VCCA through the conversion of power supply grouping buffer circuit 4, so that band-gap reference circuit 1 work, reference voltage V _BGSet up.When the 1.2V reference voltage V _BGAfter the foundation, composite difference input linear voltage regulator 3 can be with reference to voltage voltage V from soft _SOFTAutomatically switch to reference voltage V _BG, to produce accurately voltage signal VCC to power supply grouping buffer circuit 4; Through the conversion of power supply grouping buffer circuit 4, export four tunnel accurate and non-interfering internal electric sources, be respectively internal simulation power supply VCCA, internal digital power supply VCCD, internal power power supply VCCP and inner bootstrap power supply VCCB.

Below only be a preferred example of the present invention, do not consist of any limitation of the invention, obviously under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.

Claims (4)

1. a voltage-stabilized power supply circuit that is applied to high pressure DC-DC converter inside comprises for generation of the zero-temperature coefficient reference voltage V _BGWith bias voltage V _BIASBand-gap reference circuit (1), it is characterized in that: also comprise soft and biasing circuit (2), composite difference linear voltage regulator (3) and power supply grouping buffer circuit (4);

Described soft and biasing circuit (2) are used to interior voltage-stabilized power supply that bias current I is provided _BIASWith soft voltage V _SOFT, and be connected to composite difference linear voltage regulator (3);

Described composite difference linear voltage regulator (3) is used for finishing soft voltage V of soft and biasing circuit (2) input _SOFTReference voltage V with band-gap reference circuit (1) input _BGSwitching between the two, and output voltage signal VCC and bias current signal I _S2To power supply grouping buffer circuit (4);

Described power supply grouping buffer circuit (4), with the voltage signal VCC of composite difference linear voltage regulator (3) input be converted to four groups mutually isolate, non-interfering internal electric source VCCA, VCCD, VCCP and VCCB, be respectively analog module, digital module, power model and the bootstrap capacitor power supply of high pressure DC-DC converter inside.

2. voltage-stabilized power supply circuit according to claim 1, it is characterized in that soft and biasing circuit (2), comprise that withstand voltage is greater than high voltage PMOS pipe M9 ~ M13 of 12V between 5 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M8 of 5V between 8 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M14 ~ M16 of 12V between 3 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M17 ~ M20 and the resistance R 1 of 5V between 4 sources, the drain electrode;

Described low pressure PMOS pipe M6 ~ M8, its grid link to each other with self drain electrode respectively and consist of diode structure, and connect and be connected across high input voltage power supply V _INAnd between the drain electrode of high pressure NMOS pipe M14;

Described high pressure NMOS pipe M14, its grid and source electrode are connected to ground jointly;

Described low pressure PMOS pipe M5, its source electrode and high input voltage power supply V _INLink to each other; Drain electrode links to each other with the grid of low pressure PMOS pipe M8; Its grid links to each other with the grid of low pressure PMOS pipe M1 ~ M4;

Described high voltage PMOS pipe M13, its source electrode and high input voltage power supply V _INLink to each other; Its grid links to each other with the drain electrode of low pressure PMOS pipe M5; Its drain electrode links to each other with the source electrode of low pressure NMOS pipe M17;

Described low pressure PMOS pipe M1 ~ M4 and high voltage PMOS pipe M9 ~ M12 consist of the common-source common-gate current mirror structure; The drain electrode of high voltage PMOS pipe M9 and M10 links to each other with the drain electrode of low pressure NMOS pipe M17 and the drain electrode of high pressure NMOS pipe M16 respectively; The drain electrode of high voltage PMOS pipe M12 is as the first output terminal of soft and biasing circuit (2), output offset electric current I BIAS; The drain electrode of high voltage PMOS pipe M11 links to each other with the drain electrode of low pressure NMOS pipe M20; This low pressure NMOS manages M20, and its source electrode is connected to ground; Its grid links to each other with the drain electrode of self, and as the second output terminal of soft and biasing circuit (2), exports the soft voltage V that opens _SOFT

Described low pressure NMOS pipe M17, its drain electrode formation diode structure that links to each other with self grid; Its source electrode links to each other with the drain electrode of high pressure NMOS pipe M15;

Described high pressure NMOS pipe M15, M16 and low pressure NMOS pipe M18, M19 consist of the common-source common-gate current mirror structure; The source electrode of low pressure NMOS pipe M18 is connected to ground; The source electrode of low pressure NMOS pipe M19 is connected to ground by resistance R 1.

3. voltage-stabilized power supply circuit according to claim 1, it is characterized in that composite difference linear voltage regulator (3), comprise current mirror (31), withstand voltage is greater than high voltage PMOS pipe M8 ~ M10 of 12V between 3 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M7 of 5V between 7 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M11, the M12 of 12V between 2 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M13 ~ M15 of 5V between 3 sources, the drain electrode;

Described current mirror (31) is with the bias current I of soft and biasing circuit (2) input _BIASBe converted to the two-way electric current I _S1And I _S2I wherein _S1Flow into the drain electrode of high voltage PMOS pipe M8, for composite difference linear voltage regulator (3) provides tail current; I _S2Flow into power supply grouping buffer circuit (4);

Described low pressure PMOS pipe M4 ~ M6 and high voltage PMOS pipe M8 ~ M10 consist of the common-source common-gate current mirror structure; The source electrode of low pressure PMOS pipe M4 ~ M6 all with high input voltage power supply V _INLink to each other; The drain electrode of high voltage PMOS pipe M9 links to each other with the source electrode of low pressure PMOS pipe M7; The drain electrode of described high voltage PMOS pipe M10 links to each other with the drain electrode of high pressure NMOS pipe M12;

Described low pressure PMOS pipe M7, its grid links to each other with the drain electrode of self and consists of diode structure, and is connected to the source electrode of low pressure PMOS pipe M1 and M3;

Described low pressure PMOS pipe M1, M2 and M3 consist of the composite difference input to structure; Its grid respectively with the reference voltage V of band-gap reference circuit (1) input _BG, the input of soft and biasing circuit (2) soft voltage V _SOFTAnd feedback voltage V _FBLink to each other; The drain electrode of low pressure PMOS pipe M1 links to each other with the source electrode of low pressure PMOS pipe M2;

Described low pressure NMOS pipe M13 and M14, its grid link to each other and consist of current mirror; Its drain electrode links to each other with the drain electrode of low pressure PMOS pipe M3 with low pressure PMOS pipe M2 respectively; Its source electrode is connected to ground jointly;

Described high pressure NMOS pipe M12, its grid and self the drain electrode formation diode structure that links to each other, and as the output terminal of composite difference linear voltage regulator (3), output voltage signal VCC; Its source electrode links to each other with the drain electrode of low pressure NMOS pipe M15;

Described low pressure NMOS pipe M15, its grid links to each other with the drain electrode of low pressure PMOS pipe M2; Its source electrode is connected to ground;

Described high pressure NMOS pipe M11, its drain electrode is connected to high input voltage power supply V _INIts grid connects voltage VCC.

4. voltage-stabilized power supply circuit according to claim 1, it is characterized in that power supply grouping buffer circuit (4), comprise that withstand voltage is greater than high voltage PMOS pipe M6 ~ M8 of 12V between 3 sources, the drain electrode, withstand voltage is less than low pressure PMOS pipe M1 ~ M5 of 5V between 5 sources, the drain electrode, withstand voltage is greater than high pressure NMOS pipe M9 ~ M15 of 12V between 7 sources, the drain electrode, and withstand voltage is less than low pressure NMOS pipe M16 ~ M20 and 1 triode Q1 of 5V between 5 sources, the drain electrode;

Described high pressure NMOS pipe M9 ~ M12, its grid all are connected with the voltage signal VCC of composite difference linear voltage regulator (3) input; Its drain electrode all with high input voltage voltage V _INLink to each other; Its source electrode links to each other with the drain electrode of low pressure NMOS pipe M16 ~ M19 respectively;

Described low pressure NMOS pipe M16 ~ M19, its grid all link to each other with the bias voltage VBIAS of band-gap reference circuit (1) input; Its source electrode all is connected to ground; The drain electrode of low pressure NMOS pipe M16 is as divide into groups the first output terminal of buffer circuit (4) of power supply, output internal simulation power supply VCCA; The drain electrode of low pressure NMOS pipe M17 is as divide into groups the second output terminal of buffer circuit (4) of power supply, output internal digital power supply VCCD; The drain electrode of low pressure NMOS pipe M18 and M19 links to each other with the grid of low pressure PMOS pipe M4 and M5 respectively;

Described low pressure PMOS pipe M1 ~ M3 and high voltage PMOS pipe M6 ~ M8 consist of the common-source common-gate current mirror structure; The source electrode of low pressure PMOS pipe M1 ~ M3 all with high input voltage power supply V _INLink to each other; The electric current I of the drain electrode of high voltage PMOS pipe M6 and composite difference linear voltage regulator (3) input _S2Link to each other; The drain electrode of high voltage PMOS pipe M7 links to each other with the emitter of triode Q1; The drain electrode of high voltage PMOS pipe M8 links to each other with the source electrode of low pressure PMOS pipe M5; The drain electrode of this low pressure PMOS pipe M5 is connected to ground;

Described triode Q1, its base stage links to each other with the source electrode of low pressure PMOS pipe M4; Its collector links to each other with the drain electrode of low pressure PMOS pipe M4, and is connected to ground;

Described high pressure NMOS pipe M15, its drain electrode and high input voltage power supply V _INLink to each other; Its grid links to each other with the source electrode of low pressure PMOS pipe M5; Its source electrode is as divide into groups the 3rd output terminal of buffer circuit (4) of power supply, output internal power power supply VCCP;

Described low pressure NMOS pipe M20, its drain electrode links to each other with internal power power supply VCCP; The bias voltage V of its grid and band-gap reference circuit (1) input _BIASLink to each other; Its source electrode is connected to ground;

Described high pressure NMOS pipe M13 and M14, its grid links to each other, and is connected to the emitter of triode Q1; Its source electrode links to each other; The drain electrode of high pressure NMOS pipe M14 is exported inner bootstrap power supply VCCB as divide into groups the 4th output terminal of buffer circuit (4) of power supply.

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