CN102880087A - Method for controlling power supply and power supply controller - Google Patents
Method for controlling power supply and power supply controller Download PDFInfo
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- CN102880087A CN102880087A CN2012104088262A CN201210408826A CN102880087A CN 102880087 A CN102880087 A CN 102880087A CN 2012104088262 A CN2012104088262 A CN 2012104088262A CN 201210408826 A CN201210408826 A CN 201210408826A CN 102880087 A CN102880087 A CN 102880087A
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Abstract
The invention discloses a method for controlling a power supply. The method for controlling the power supply is applied to a power supply controller composed of a CPU (central processing unit) and more than two power supply control chips. The CPU is connected with the power supply chips through an I2C (inter-integrated circuit) bus, and the chips are in cascade connection with each other. The first-stage power supply control chip receives a normal operation signal of the next-stage power supply control chip prior to outputting a power enable signal, and the next-stage power supply control chip is informed of the normal operation signal. After the optional-stage power supply control chip between the first-stage power supply control chip and the last-stage power supply control chip is started, the normal operation signal is sent to the upper-stage power supply control chip and the next-stage power supply control chip, a normal operation signal of the upper-stage power supply control chip and a normal operation signal of the next-stage power supply control chip are received, and the power enable signal is output. The normal operation signal is sent to the upper-stage power supply control chip after the last-stage power supply control signal is started, and the power enable signal is output. The invention further discloses a power supply controller. The capability of protecting a single board and the power supply control chips can be improved.
Description
Technical field
The application relates to power supply control technology field, relates in particular to method and the power control of control power supply.
Background technology
At present, in design of electronic products, function and the design of product become increasingly complex, circuit level is also more and more higher, in a lot of situations, an ASIC(Application Specific Integrated Circuit special IC) chip need to provide 5～10 kinds of different power supplys, and the sequence requirement of the lower electricity that powers on is arranged.If veneer adopts n asic chip to design, then need control nearly (n * 5)～(n * 10) plant in addition the powering on of more kinds of different electrical power under electricity sequentially, to satisfy the power-on and power-off requirement of subscriber equipment.
Existing power supply power-on and power-off power supply control chip is mainly the asic chip with voltage control function, ADM1065 chip such as ADI company, each power supply control chip at most power supply number of control is 10, control more power supply and must adopt a plurality of power supply control chips.Generally be with direct in parallel use of a plurality of power supply control chips at present, processor CPU each power supply control chip after to parallel connection carries out centralized control, to regulate the power-on and power-off order between each power supply and to carry out fault detect.Wherein, sequence power-on refers to successively out-put supply enable signal of power supply control chip, and the lower electricity of order refers to that power supply control chip stops the out-put supply enable signal successively.
The multiple power supplies control circuit synoptic diagram of above-mentioned implementation as shown in Figure 1, CPU passes through I
2The C bus links to each other with each power supply control chip, power-on and power-off order between each power supply can only rely on CPU to regulate, fault detect also is directly to be carried out by CPU, be that each power supply that each power supply control chip is controlled inputs to described power supply control chip with supply voltage by input pin (input 1～input 10) in advance, whether described power supply control chip is monitored each supply voltage of described input unusual; CPU passes through I
2Each power supply control chip of C bus poll, be that CPU can inquire power supply control chip one by one by predefined order, when arbitrary power supply control chip is arrived in inquiry, as long as it is unusual that any one supply voltage in each power supply of this power supply control chip monitoring occurs, then this power supply control chip sends the abnormity of power supply signal to CPU, and CPU passes through I
2The control signal of C bus electricity under this power supply control chip sending order after this power supply control chip receives described control signal, stops to send power enable signal to each power supply of this power supply control chip control, to control the sequentially lower electricity of described each power supply;
After this power supply control chip sequentially descended electricity with all power supplys of its control, CPU obtained the state that this power supply control chip has descended electricity to finish, and then, CPU passes through I by predefined order
2The C bus is notified the sequentially lower electricity of next power supply control chip and is obtained the state that it descend electricity to finish, until notified all power supply control chips so that all power supply control chips all the lower electricity of order finish.That is to say that unusual as long as arbitrary power supply occurs, all power supplys are all sequentially lower electric with the protection veneer.
Can find out from above-mentioned implementation procedure, although such scheme can be realized the order power-on and power-off control of multiple power supplies, only depend on CPU to pass through I
2The mode of C bus poll is come indirect failure judgement source, then according to the corresponding source of trouble, passes through I
2The control signal of electricity is carried out electricity under the order to power supply control chip under the C bus transmitting sequence, and there are the following problems:
1) adopt the mode of poll to carry out fault inquiry, search efficiency is lower.Such as, as shown in Figure 1, if problem has appearred in a certain road power supply of power supply control chip N control, but predefined polling sequence is to begin inquiry from power supply control chip 1, then inquires power supply control chip 2, until power supply control chip N, then CPU needs N-1 power supply control chip of inquiry front before the power supply that detects power supply control chip N control breaks down, and has wasted the plenty of time, search efficiency is lower, has the delay of fault handling and response.
2) can not direct interaction between each power supply control chip, pass through I by CPU
2C bus and each power supply control chip carry out alternately, and the efficient of information interaction is lower, and the time of finishing the one query cost is longer, has the delay of fault handling and response.
3) there is the delay of fault handling and response in CPU when task is busy.
All there is the problem of power fail response and processing delay in above-mentioned three kinds of situations, thereby can cause: after any one road power supply occurs unusually, the power supply that can't guarantee whole veneer is in time sequentially lower electric, so that the power supply control chip long period on the veneer is under the unusual power work environment, thereby can cause damage to power supply control chip, and then damage veneer.That is to say, adopt CPU to pass through I
2The mode of C bus poll is controlled order power-on and power-off and the monitoring power fail of veneer multiple power supplies, and is relatively poor to the protective capability of veneer and power supply control chip.
Summary of the invention
In view of this, the application proposes a kind of method of controlling power supply, can improve the protective capability to veneer and power supply control chip.
The application also proposes a kind of power control, can improve the protective capability to veneer and power supply control chip.
For achieving the above object, the technical scheme of the embodiment of the present application is achieved in that
A kind of method of controlling power supply is applied to by processor CPU and two power controls that above power supply control chip consists of, and CPU passes through I
2The C bus links to each other with two above power supply control chips, between the power supply control chip according to the in twos cascade of predefined order,
Power supply control chips at different levels are respectively according to starting separately start-up time;
After starting, receives the first order power supply control chip normal operation signal of time one-level power supply control chip, then out-put supply enable signal, and notice time one-level power supply control chip normal operation signal;
Arbitrary level power supply control chip between first order power supply control chip and the afterbody power supply control chip starts backward upper level and inferior one-level control chip sends the normal operation signal; Receive the normal operation signal of upper level and inferior one-level control chip, the out-put supply enable signal;
The afterbody power supply control chip starts backward upper level control chip and sends the normal operation signal; Receive the normal operation signal of upper level power supply control chip, the out-put supply enable signal.
A kind of power control, the processor CPU of this power control passes through I
2The C bus links to each other with two above power supply control chips, between the power supply control chip according to the in twos cascade of predefined order, wherein,
The control pin that is used for cascade in the adjacent two-stage power supply control chip on the previous stage power supply chip links to each other by the input pin that is used for cascade on first signal line and the inferior one-level power supply chip; The input pin that is used for cascade on this previous stage power supply chip links to each other by the control pin that is used for cascade on secondary signal line and this time one-level power supply control chip;
Each links to each other with the Voltage-output pin of an external power source respectively for the input pin of cascade on the power supply control chips at different levels, and each control pin that is used for cascade links to each other with the output control pin of an external power source respectively.
The application's beneficial effect is; directly each power supply of its control is carried out power-on and power-off sequential control and malfunction monitoring by power supply control chip; improved search efficiency; power supply control chip can in time respond and process the abnormity of power supply fault; can guarantee all power supplys all in time order power-on and power-off finish; avoid the power supply control chip long period on the veneer to be under the unusual power work environment, thereby can greatly improve the protective capability to veneer and power supply control chip.
Description of drawings
Fig. 1 is the veneer multiple power supplies control circuit synoptic diagram of prior art;
Fig. 2 is the one-board power supply control circuit structural drawing of the embodiment of the present application;
Fig. 3 is the method flow diagram of the embodiment of the present application;
Fig. 4 is the structure drawing of device of the embodiment of the present application;
Fig. 5 is a veneer 20 road power control circuit synoptic diagram of the embodiment of the present application.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below by specific embodiment and referring to accompanying drawing, the present invention is described in detail.
The application's method is applied to by processor CPU and two power controls that above power supply control chip consists of, and CPU passes through I
2The C bus links to each other with two above power supply control chips, and according to the in twos cascade of predefined order, power supply control chips at different levels are respectively according to starting separately start-up time between the power supply control chip;
After starting, receives the first order power supply control chip normal operation signal of time one-level power supply control chip, then out-put supply enable signal, and notice time one-level power supply control chip normal operation signal;
Arbitrary level power supply control chip between first order power supply control chip and the afterbody power supply control chip starts backward upper level and inferior one-level control chip sends the normal operation signal; Receive the normal operation signal of upper level and inferior one-level control chip, the out-put supply enable signal;
The afterbody power supply control chip starts backward upper level control chip and sends the normal operation signal; Receive the normal operation signal of upper level power supply control chip, the out-put supply enable signal.
Pass through I with respect to CPU of the prior art
2The mode of C bus poll is controlled multiple power supplies, and the application has proposed a kind of method of different control multiple power supplies, is not to adopt CPU to pass through I
2The mode of C bus poll, but adopt the mode of the distributed control of each power supply control chip, power supply control chip is cascade in twos, can realize sequence power-on and the lower electricity of all power supplys of veneer, and can control neatly the electrifying timing sequence of the various power supplys of veneer, solve well multiple power supplies order power-on and power-off control and Power Supply Monitoring problem on the veneer.
The one-board power supply control circuit of the embodiment of the present application as shown in Figure 2, processor CPU passes through I
2The C bus links to each other with at least 2 power supply control chips, the Voltage-output pin of each power supply of each power supply control chip control links to each other with the input pin of this power supply control chip, output control pin links to each other with the control pin of this power supply control chip, between the power supply control chip according to the in twos cascade of predefined order, link to each other with 2 signal wires between per 2 adjacent power supply control chips, wherein, a signal wire connects the input pin of previous stage power supply control chip in described 2 power supply control chips and the control pin of time one-level power supply control chip, and another root signal wire connects the control pin of described previous stage power supply control chip and the input pin of described one-level power supply control chip.
Also can use the signal wire more than 2 to link to each other between per 2 adjacent power supply control chips, that is to say, different signals can also can be received and dispatched with many signal wires with a signal wire transmitting-receiving, such as, the power supply normal signal of a power supply control chip and lower electric settling signal, can receive and dispatch with a signal wire, also can be with 2 signal wires, if use with 2 signal wires, a signal wire wherein is used for the transmitting-receiving of power supply normal signal, and another signal wire is used for the transmitting-receiving of lower electric settling signal.
Take Fig. 2 as example, the information interaction of interconnected signal wire is described as follows shown in the table 1 between the part power supply control chip:
Table 1
As known from Table 1, the input 10 of previous stage power supply control chip is interconnected with control 1 signal of time one-level power supply control chip, such as the input 10 of power supply control chip 1 and control 1 signal interconnection of power supply control chip 2; The input 1 of previous stage power supply control chip is interconnected with control 10 signals of time one-level power supply control chip, such as, the input 1 of power supply control chip 3 is interconnected with control 10 signals of power supply control chip 2, the consistance that can find out the annexation between each power supply control chip is better, the control pin that uses is identical, be difficult for makeing mistakes during the in twos cascade of a plurality of like this power supply control chips, the consistance of control program is also very similar simultaneously.Certainly, also can use different input pins and be connected pin and connect, as long as guarantee can carry out information interaction between two adjacent power supply control chips, such as, also the input 7 of power supply control chip 1 can be linked to each other with the control 2 of power supply control chip 2.
The method flow of the embodiment of the present application as shown in Figure 3, a kind of method of controlling power supply is applied to by processor CPU and two power controls that above power supply control chip consists of, CPU passes through I
2The C bus links to each other with two above power supply control chips, and according to the in twos cascade of predefined order, power supply control chips at different levels are respectively according to starting separately start-up time between the power supply control chip; When controlling power supply, carry out following steps:
Step 301: receive the normal operation signal of time one-level power supply control chip after first order power supply control chip starts, then out-put supply enable signal, and notice time one-level power supply control chip normal operation signal.
For example, as shown in Figure 2, after power supply control chip 1 starts, until by input 10 receive the normal operation signal of time one-level power supply control chip 2 after, power supply control chip 1 is according to the predefined time interval, by control pin (control 1～control 9), the Sequential output power enable signal is controlled each power supply sequence power-on of its control.After each power supply normal operation of power supply control chip 1 control, with the normal operation signal notice power supply control chip 2 of power supply control chip 1.
Step 302: the arbitrary level power supply control chip between first order power supply control chip and the afterbody power supply control chip starts backward upper level and inferior one-level control chip sends the normal operation signal; Receive the normal operation signal of upper level and inferior one-level control chip, the out-put supply enable signal.
For example, as shown in Figure 2, after power supply control chip 2 starts, after the normal operation, pass through respectively the normal operation signals of control 1 and control 10 transmission power supply control chips 2 to upper level power supply control chip 1 and time one-level power supply control chip 3, behind the normal operation signal that receives power supply control chip 1 and power supply control chip 3, power supply control chip 2 is according to the predefined time interval, by control pin (control 2～control 9), by the Sequential output power enable signal of setting.
Step 303: the afterbody power supply control chip starts backward upper level control chip and sends the normal operation signal; Receive the normal operation signal of upper level power supply control chip, the out-put supply enable signal.
The application can adopt the signal interlock mode between the most succinct a plurality of power supply control chips, realize the electrifying timing sequence control of multiple power supplies, if be applied to the design that the one-board power supply requirement powers on synchronously, can allow complicated design become simple and easily realization, when being used for the order power-on and power-off of control multiple power supplies, can expand to unlimited multiple power supplies in theory.
That is to say that the application's scheme can be supported order power-on and power-off control and the Power Supply Monitoring of any multiple power supplies, the relation between the quantity of the power supply control chip of employing and the controllable power supply number is as follows:
During 2 in twos cascades of power supply control chip, can realize power-on and power-off sequential control and the monitoring of 2 * 10-2 * 1=18 road power supply; During 3 in twos cascades of power supply control chip, can realize power-on and power-off sequential control and the monitoring of 3 * 10-2 * 2=26 road power supply; During 4 in twos cascades of power supply control chip, can realize power-on and power-off sequential control and the monitoring of 4 * 10-2 * 3=36 road power supply; Thereby can derive, during N in twos cascade of power supply control chip, can realize that N * 10-2 (N-1)=8N+2(N is positive integer) power-on and power-off sequential control and the monitoring of road power supply.Such as order power-on and power-off control and the monitoring that will realize 30 road power supplys, then calculate N=(30-2)/8=3.5, round numbers N=4 namely needs 4 in twos cascades of power supply control chip, can realize order power-on and power-off control and the monitoring of 30 road power supplys.
Preferably, during abnormity of power supply that the arbitrary power supply control chip before the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, then according to waterfall sequence to inferior one-level power supply control chip notice abnormity of power supply signal.
Power supply control chip can be controlled a plurality of power supplys, and each power supply inputs to power supply control chip with the input pin of its supply voltage by power supply control chip, and whether power supply control chip can be monitored each supply voltage of input unusual.
As shown in Figure 2, it is unusual that power supply control chip 2 monitors arbitrary out-put supply of this chip, namely power supply control chip 2 determine to be enabled by the power enable signal of this chip abnormity of power supply the time, power supply control chip 2 is sent to time one-level power supply control chip 3 from controlling 10 with its abnormity of power supply signal by signal wire.
When controlling 10 transmitted signal, such as, transmitted signal " 0 " expression abnormity of power supply, transmitted signal " 1 " expression power supply is normal.
Arbitrary power supply control chip between first order power supply control chip and afterbody power supply control chip is received the abnormity of power supply signal, then transmits the abnormity of power supply signal according to waterfall sequence to inferior one-level power supply control chip.
Because during the abnormity of power supply that arbitrary power supply control chip is determined to be enabled by the power enable signal of this chip on the veneer; just need to the power supply of all power supply control chip controls on the veneer is all sequentially lower electric; just can effectively protect veneer and power supply control chip; but realize among the application that lower electricity is at first from the afterbody power supply control chip; therefore; when arbitrary power supply control chip monitors abnormity of power supply; just need rapidly notice to the afterbody power supply control chip, with the power supply that guarantees all power supply control chips controls can both rapid sequential under electricity.
Realize just how making the power supply control chip of in twos cascade to transmit each other the abnormity of power supply signal to adjacent inferior one-level power supply control chip herein, so that the afterbody power supply control chip can be arrived by timely notice.
When arbitrary power supply control chip monitors abnormity of power supply, all can pass to time one-level power supply control chip by waterfall sequence, so repeatedly, until the afterbody power supply control chip is received the abnormity of power supply signal.
For example, as shown in Figure 2, when power supply control chip 2 receives the abnormity of power supply signal of upper level power supply control chip 1, power supply control chip 2 will send its abnormity of power supply signal to inferior one-level power supply control chip 3, when power supply control chip 3 was received the abnormity of power supply signal of power supply control chip 2, power supply control chip 3 can send the abnormity of power supply signal of power supply control chip 3 to inferior one-level power supply control chip 4.
When power supply control chip 4 was received power supply control chip 3 abnormity of power supply signal, processing was similar with power supply control chip 3, so repeatedly, until the afterbody power supply control chip is received the abnormity of power supply signal.
Realized that the timely notice of the power fail that arbitrary power supply control chip is monitored arrives after the afterbody power supply control chip; the below will discuss the power supply of how realizing all power supply control chip control, and all order is lower electric, with protection veneer and power supply control chip.
The afterbody power supply control chip is received the abnormity of power supply signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip.
Lower electricity is at first from the afterbody power supply control chip, then be the penultimate stage power supply control chip, repeatedly carry out successively, sequentially descend electricity to finish until first order power supply control chip is controlled each power supply of its control, namely the power supply of all power supply control chip controls all descends electricity to finish.
For example, as shown in Figure 2, when power supply control chip N-1 by signal wire from control 1 send its abnormity of power supply signal to afterbody power supply control chip N after, power supply control chip N stops the out-put supply enable signal, namely control the sequentially lower electricity of each power supply of its control, then, send its lower electric settling signal to power supply control chip N-1 by signal wire from controlling 1.
Afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip.
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
Owing to be in twos cascade between the power supply control chip, therefore, can be according to the order of connection of Board Power up source control chip, lower electricity successively.
Each power supply of afterbody power supply control chip control at first stops the out-put supply enable signal, the lower electricity of order is finished, therefore, the penultimate stage power supply control chip at first receives the lower electric settling signal of afterbody power supply control chip, second lower electricity finished, then send its lower electric settling signal to the upper level power supply control chip, it is level power supply control chip third from the bottom, so repeatedly, until first order power supply control chip stops the out-put supply enable signal, each power supply of controlling its control sequentially descends electricity to finish, and namely all power supply control chips each power supply of all having controlled separately control sequentially descends electricity to finish.
For example, as shown in Figure 2, power supply control chip N at first stops the out-put supply enable signal, then send its lower electric settling signal to power supply control chip N-1, power supply control chip N-1 stops the out-put supply enable signal after receiving described lower electric settling signal, sends its lower electric settling signal to power supply control chip N-2, so repeatedly, until power supply control chip 1 stops the out-put supply enable signal.So far, each power supply that power supply control chip 1～power supply control chip N has controlled separately control sequentially descends electricity to finish, and all power supplys on the veneer have been realized electricity under the rapid sequential, can improve the protective capability to veneer and power supply control chip.
Preferably, during abnormity of power supply that the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, stop the out-put supply enable signal and according to waterfall sequence to the lower electric settling signal of upper level power supply control chip notice;
Receive lower electric settling signal at afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip, then stop the out-put supply enable signal and notify lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
Preferably, during abnormity of power supply that power supply control chips at different levels are determined to be enabled by the power enable signal of this chip, the recording power abnormal signal also reports CPU.CPU can record the information of described abnormity of power supply, so that CPU sets up the fault inquiry daily record.Wherein, report the form of CPU, can adopt the form of interruption.
With respect to prior art; the application sets up the most succinct effective communication port between each power supply control chip; the power fail response of having avoided CPU to participate in the monitoring power supply fault and having caused and the drawback of processing delay; directly carry out monitoring and the power-on and power-off sequential control of power fail by power supply control chip, can protect in time the chip on the veneer and then protect whole veneer.
The apparatus structure of the embodiment of the present application as shown in Figure 4, a kind of power control, the processor CPU of this power control passes through I
2The C bus links to each other with two above power supply control chips, between the power supply control chip according to the in twos cascade of predefined order, wherein,
The control pin that is used for cascade in the adjacent two-stage power supply control chip on the previous stage power supply chip links to each other by the input pin that is used for cascade on first signal line and the inferior one-level power supply chip; The input pin that is used for cascade on this previous stage power supply chip links to each other by the control pin that is used for cascade on secondary signal line and this time one-level power supply control chip;
Each links to each other with the Voltage-output pin of an external power source respectively for the input pin of cascade on the power supply control chips at different levels, and each control pin that is used for cascade links to each other with the output control pin of an external power source respectively.
Preferably, after starting, receives the first order power supply control chip normal operation signal of time one-level power supply control chip, then out-put supply enable signal, and notice time one-level power supply control chip normal operation signal;
Arbitrary level power supply control chip between first order power supply control chip and the afterbody power supply control chip starts backward upper level and inferior one-level control chip sends the normal operation signal; Receive the normal operation signal of upper level and inferior one-level control chip, the out-put supply enable signal;
The afterbody power supply control chip starts backward upper level control chip and sends the normal operation signal; Receive the normal operation signal of upper level power supply control chip, the out-put supply enable signal.
Preferably, during abnormity of power supply that the arbitrary power supply control chip before the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, then according to waterfall sequence to inferior one-level power supply control chip notice abnormity of power supply signal;
Arbitrary power supply control chip between first order power supply control chip and afterbody power supply control chip is received the abnormity of power supply signal, then transmits the abnormity of power supply signal according to waterfall sequence to inferior one-level power supply control chip;
The afterbody power supply control chip is received the abnormity of power supply signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
Afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
Preferably, during abnormity of power supply that the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, stop the out-put supply enable signal and according to waterfall sequence to the lower electric settling signal of upper level power supply control chip notice;
Receive lower electric settling signal at afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip, then stop the out-put supply enable signal and notify lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
Preferably, during abnormity of power supply that power supply control chips at different levels are determined to be enabled by the power enable signal of this chip, the recording power abnormal signal also reports CPU.
Adopt the application's scheme; as long as it is unusual that the arbitrary power supply on the veneer occurs; just can realize controlling the lower electricity of the timely order of power supplys all on the veneer finishes; can not allow power supply control chip long period on the veneer be under the unusual power work environment and damage power supply control chip and veneer, thereby can improve the protective capability to veneer and power supply control chip.
Beneficial effect below by practical application explanation present techniques scheme:
As shown in Figure 5, at the little package module of high-end Ethernet switch 48 * 10G road SFP+(SMALL FORM FACTOR PLUGGABLE hot plug) in the design of light mouth line card veneer, because the 4 cover PP(Packet Processor that veneer adopts, data packet processor) and FAP (Fabric Adapter Processor, the switching network adaptation processor) the required voltage kind is many, and the power that various voltages need is also larger, therefore need to repartition power supply according to power supply chip to various voltages, 3.3V is arranged like this, 2.5V, 1.8V_Anlog, 1.8V_Digital, 1.65V, 1.5V_Serdes, 1.5V_RAM, 0.96_core1,0.96_core2,0.96_core3,0.96_core4,1.0V_core, 1.0V_serdes, 1.05V, 1.2V, 0.9V, 1.1V, 1.5V, 5V, 3.3V_SFP need to control the power-on and power-off sequential Deng 20 road power supplys.Each power supply that each power supply control chip is controlled inputs to described power supply control chip with supply voltage by input pin in advance, and whether each supply voltage that described power supply control chip is monitored described input is unusual and carry out the power-on and power-off sequential control.
If adopt two ADM1065 power supply control chips directly to carry out the power-on and power-off sequential control; a power supply control chip can be monitored at most 10 power supplys; can meet the demands from the quantity of monitoring; but owing to have mutual power-on and power-off requirement between a plurality of power supplys; and all power supplys all will descend electricity with the protection veneer after one road power issue occurring; if but adopt prior art; carry out power supply power-on and power-off sequential control and failure monitoring by CPU fully, the delay that the power fail response can occur and process.
This veneer adopts the application's scheme to test, and the power supply sequencing control circuit of veneer employing the application implementation as shown in Figure 5.Veneer adopts 3 power supply control chips to control, and power supply control chip is the ADM1065ASU of U.S. ADI company.
Power supply control chip 1,2,3 is respectively according to starting separately start-up time;
After starting, receives power supply control chip 1 the normal operation signal of power supply control chip 2, then out-put supply enable signal, and notice power supply control chip 2 normal operation signals;
Power supply control chip 2 starts backward power supply control chip 1 and power supply control chip 3 sends the normal operation signal; After receiving the normal operation signal of power supply control chip 1 and power supply control chip 3, out-put supply enable signal, each power supply sequence power-on of control power supply control chip 2;
Power supply control chip 3 starts backward power supply control chip 2 and sends the normal operation signal; After receiving the normal operation signal of power supply control chip 2, the out-put supply enable signal.
In 3 power supply control chips arbitrary out-put supply of arbitrary power supply control chip control occur unusual,, this power supply control chip sends its abnormity of power supply signal to inferior one-level power supply control chip by signal wire, until power supply control chip 3 receives the abnormity of power supply signal of power supply control chip 2.
Receive the abnormity of power supply signal of power supply control chip 2 when power supply control chip 3 after, power supply control chip 3 stops the out-put supply enable signal, namely control the sequentially lower electricity of each power supply of its control, then send its lower electric settling signal to the upper level power supply control chip, namely power supply control chip 2.
When power supply control chip 2 receives the lower electric settling signal of time one-level power supply control chip (power supply control chip 3), power supply control chip 2 stops the out-put supply enable signal, send 2 times electric settling signals of power supply control chip to upper level power supply control chip (power supply control chip 1), after last power supply control chip 1 receives 2 times electric settling signals of power supply control chip, stop the out-put supply enable signal.
Namely unusual as long as the arbitrary power supply on this veneer occurs; just can realize controlling the lower electricity of the timely order of power supplys all on the veneer finishes; can not allow power supply control chip long period on the veneer be under the unusual power work environment and damage power supply control chip and veneer, thereby can improve the protective capability to veneer and power supply control chip.
Simultaneously, the base plate in this example and buckle adopt the synchronous electrification control method of the embodiment of the present application, and be good through the duty of large scale test checking proof power supply and veneer, and one-board power supply has reached the Expected Results of design.
In the application's scheme; power supply control chip by veneer is directly monitored power fail; arbitrary road power supply on monitoring veneer occurs when unusual; all power supplys that each power supply control chip of veneer can be controlled on the veneer are in time sequentially lower electric, greatly improved the protective capability to veneer and power supply control chip.
Adopt the application's scheme, can control neatly electricity order under the powering on of all power supplys of veneer, solved well the control problem of multiple power supplies order power-on and power-off on the veneer, can support in theory the control of unlimited multiple power supplies.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (9)
1. a method of controlling power supply is applied to by processor CPU and two power controls that above power supply control chip consists of, and CPU passes through I
2The C bus links to each other with two above power supply control chips, it is characterized in that, between the power supply control chip according to the in twos cascade of predefined order,
Power supply control chips at different levels are respectively according to starting separately start-up time;
After starting, receives the first order power supply control chip normal operation signal of time one-level power supply control chip, then out-put supply enable signal, and notice time one-level power supply control chip normal operation signal;
Arbitrary level power supply control chip between first order power supply control chip and the afterbody power supply control chip starts backward upper level and inferior one-level control chip sends the normal operation signal; Receive the normal operation signal of upper level and inferior one-level control chip, the out-put supply enable signal;
The afterbody power supply control chip starts backward upper level control chip and sends the normal operation signal; Receive the normal operation signal of upper level power supply control chip, the out-put supply enable signal.
2. method according to claim 1 is characterized in that,
During abnormity of power supply that the arbitrary power supply control chip before the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, then according to waterfall sequence to inferior one-level power supply control chip notice abnormity of power supply signal;
Arbitrary power supply control chip between first order power supply control chip and afterbody power supply control chip is received the abnormity of power supply signal, then transmits the abnormity of power supply signal according to waterfall sequence to inferior one-level power supply control chip;
The afterbody power supply control chip is received the abnormity of power supply signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
Afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
3. method according to claim 1 is characterized in that,
During abnormity of power supply that the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, stop the out-put supply enable signal and according to waterfall sequence to the lower electric settling signal of upper level power supply control chip notice;
Receive lower electric settling signal at afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip, then stop the out-put supply enable signal and notify lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
4. according to claim 2 or 3 described methods, it is characterized in that during abnormity of power supply that power supply control chips at different levels are determined to be enabled by the power enable signal of this chip, the recording power abnormal signal also reports CPU.
5. power control, the processor CPU of this power control passes through I
2The C bus links to each other with two above power supply control chips, it is characterized in that, between the power supply control chip according to the in twos cascade of predefined order, wherein,
The control pin that is used for cascade in the adjacent two-stage power supply control chip on the previous stage power supply chip links to each other by the input pin that is used for cascade on first signal line and the inferior one-level power supply chip; The input pin that is used for cascade on this previous stage power supply chip links to each other by the control pin that is used for cascade on secondary signal line and this time one-level power supply control chip;
Each links to each other with the Voltage-output pin of an external power source respectively for the input pin of cascade on the power supply control chips at different levels, and each control pin that is used for cascade links to each other with the output control pin of an external power source respectively.
6. device according to claim 5 is characterized in that,
After starting, receives the first order power supply control chip normal operation signal of time one-level power supply control chip, then out-put supply enable signal, and notice time one-level power supply control chip normal operation signal;
Arbitrary level power supply control chip between first order power supply control chip and the afterbody power supply control chip starts backward upper level and inferior one-level control chip sends the normal operation signal; Receive the normal operation signal of upper level and inferior one-level control chip, the out-put supply enable signal;
The afterbody power supply control chip starts backward upper level control chip and sends the normal operation signal; Receive the normal operation signal of upper level power supply control chip, the out-put supply enable signal.
7. device according to claim 6 is characterized in that,
During abnormity of power supply that the arbitrary power supply control chip before the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, then according to waterfall sequence to inferior one-level power supply control chip notice abnormity of power supply signal;
Arbitrary power supply control chip between first order power supply control chip and afterbody power supply control chip is received the abnormity of power supply signal, then transmits the abnormity of power supply signal according to waterfall sequence to inferior one-level power supply control chip;
The afterbody power supply control chip is received the abnormity of power supply signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
Afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal and notifies lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
8. device according to claim 7 is characterized in that,
During abnormity of power supply that the afterbody power supply control chip is determined to be enabled by the power enable signal of this chip, stop the out-put supply enable signal and according to waterfall sequence to the lower electric settling signal of upper level power supply control chip notice;
Receive lower electric settling signal at afterbody power supply control chip to the arbitrary power supply control chip between the first order power supply control chip, then stop the out-put supply enable signal and notify lower electric settling signal according to waterfall sequence to the upper level power supply control chip;
First order power supply control chip is received lower electric settling signal, then stops the out-put supply enable signal.
9. device according to claim 5 is characterized in that,
During abnormity of power supply that power supply control chips at different levels are determined to be enabled by the power enable signal of this chip, the recording power abnormal signal also reports CPU.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888270A (en) * | 2014-03-25 | 2014-06-25 | 上海斐讯数据通信技术有限公司 | Interchanger power-on/power-off time sequence control system and method |
| CN105938332A (en) * | 2015-09-29 | 2016-09-14 | 杭州迪普科技有限公司 | Multi-power cascade-connection control unit and network device |
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| CN109725182A (en) * | 2018-07-25 | 2019-05-07 | 北京航天三优科技有限公司 | Electric control system and control method on single module in a kind of modular testing cabinet |
| CN111274196A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Start control device and method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030145239A1 (en) * | 2002-01-31 | 2003-07-31 | Kever Wayne D. | Dynamically adjustable cache size based on application behavior to save power |
| CN1780348A (en) * | 2004-11-17 | 2006-05-31 | 华为技术有限公司 | Power supply controlling method and system for telecommunication system |
| CN1960110A (en) * | 2005-11-01 | 2007-05-09 | 中兴通讯股份有限公司 | Method and device for switching supply power and protecting batteries |
| CN201039123Y (en) * | 2007-04-28 | 2008-03-19 | 杭州华三通信技术有限公司 | Seamless cascading multi-channel power on control circuit |
| CN201663546U (en) * | 2010-04-23 | 2010-12-01 | 中兴通讯股份有限公司 | Multi-power-supply power-up sequence control device and system |
-
2012
- 2012-10-24 CN CN201210408826.2A patent/CN102880087B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030145239A1 (en) * | 2002-01-31 | 2003-07-31 | Kever Wayne D. | Dynamically adjustable cache size based on application behavior to save power |
| CN1780348A (en) * | 2004-11-17 | 2006-05-31 | 华为技术有限公司 | Power supply controlling method and system for telecommunication system |
| CN1960110A (en) * | 2005-11-01 | 2007-05-09 | 中兴通讯股份有限公司 | Method and device for switching supply power and protecting batteries |
| CN201039123Y (en) * | 2007-04-28 | 2008-03-19 | 杭州华三通信技术有限公司 | Seamless cascading multi-channel power on control circuit |
| CN201663546U (en) * | 2010-04-23 | 2010-12-01 | 中兴通讯股份有限公司 | Multi-power-supply power-up sequence control device and system |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103888270A (en) * | 2014-03-25 | 2014-06-25 | 上海斐讯数据通信技术有限公司 | Interchanger power-on/power-off time sequence control system and method |
| CN105938332A (en) * | 2015-09-29 | 2016-09-14 | 杭州迪普科技有限公司 | Multi-power cascade-connection control unit and network device |
| CN105938332B (en) * | 2015-09-29 | 2019-09-06 | 杭州迪普科技股份有限公司 | The network equipment |
| CN109725182A (en) * | 2018-07-25 | 2019-05-07 | 北京航天三优科技有限公司 | Electric control system and control method on single module in a kind of modular testing cabinet |
| CN109100971A (en) * | 2018-08-20 | 2018-12-28 | 合肥华耀电子工业有限公司 | A kind of switching on and shutting down sequential control circuit with interlock function |
| CN109100971B (en) * | 2018-08-20 | 2024-02-09 | 合肥华耀电子工业有限公司 | On-off time sequence control circuit with interlocking function |
| CN109176523B (en) * | 2018-09-29 | 2021-05-18 | 苏州博众机器人有限公司 | Control circuit, circuit board and robot |
| CN109176523A (en) * | 2018-09-29 | 2019-01-11 | 苏州博众机器人有限公司 | A kind of control circuit, circuit board and robot |
| CN111274196A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Start control device and method |
| CN111274196B (en) * | 2018-12-05 | 2023-08-22 | 锐迪科（重庆）微电子科技有限公司 | Start control device and method |
| CN112152736B (en) * | 2020-09-22 | 2022-11-15 | Oppo（重庆）智能科技有限公司 | Client front-end device, failure detection method for client front-end device, and storage medium |
| CN112152736A (en) * | 2020-09-22 | 2020-12-29 | Oppo（重庆）智能科技有限公司 | Client front-end device, failure detection method for client front-end device, and storage medium |
| CN113835510A (en) * | 2021-09-27 | 2021-12-24 | 新华三信息安全技术有限公司 | Power supply control method and system |
| CN114204778A (en) * | 2021-11-29 | 2022-03-18 | 上海御渡半导体科技有限公司 | Power supply management device for ATE test platform |
| CN114204778B (en) * | 2021-11-29 | 2024-01-16 | 上海御渡半导体科技有限公司 | Power management device for ATE test platform |
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