CN102874744A - Photoelectrochemical method for separating p-type silicon micro-channel from substrate - Google Patents
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Abstract
The invention relates to the technical field of micro-electro-mechanical systems, and discloses a photoelectrochemical method for separating a p-type silicon micro-channel from a substrate. The method comprises the following steps: preprocessing positions and figures defining etching points until the etching points have inverted pyramid structures; vertically deeply etching to obtain the micro-channel; and adjusting the size of an etching voltage or an etching current to form transverse etching in order to realize the separation of the micro-channel with the substrate. The peeling of the silicon micro-channel from the silicon substrate through the utilization of the photoelectrochemistry in the invention avoids damages of physical polishing to the silicon micro-channel and damages of chemical corrosion to the silicon surface, so p-type macro-porous silicon (also called micro-channel) having a random depth within 300mum can be prepared.
Description
Technical field
The invention belongs to micro-electromechanical system field, relate to particularly a kind of PhotoelectrochemicalMethod Method that makes p-type silicon micro-channel and substrate separation.
Background technology
Porous silicon (porous silicon PS) is a kind of material that silicon forms by anodic solution in HF solution.Formation of porous silicon is to report when studying the electrochemical polish of silicon the 1950's at first.According to the criteria for classification of International Union of Pure and Applied Chemistry (International Union of Pure and Applied Chemistry IUPAC) to porous silicon, porous silicon can be divided into three kinds by the size (width or diameter) in hole: greater than grand hole of being called of 50nm (macroporous), between 2-50nm, be called mesopore (mesoporous), and size is less than the micropore that is called of 2nm.The size in the MCA hole that the present invention studies is generally in micron (um) rank, so be called again grand hole silicon.Since the nineties in last century the people such as Lehmann in article (
Lehmann et al, Formation Mechanism And Properties Of Electrochemically Etched Trenches In N-Type Silicon, J. Electrochemical Society, Vol.137, #2, pp. 653-659 (1990)) photoetching technique introduced the porous silicon etching since, photoetching technique is because it can make things convenient for define pattern to be widely used in the making of silicon micro-channel of various structures.
The technology of making at present the microchannel mainly is divided into two kinds of dry method and wet methods, wherein dry etching comprises reactive ion etching (reaction ion etching, RIE), deep reaction ion etching (deep reaction ion etching, DRIE), plasma etching (plasma etching), ion beam etching (ion beam etching, IBE) etc.Wet etching is because the different chemical etchings that are divided into, electrochemical etching and Optical Electro-Chemistry etching and the stress etching etc. of used condition and solution.Although dry etching is easy to operate, controllability is good, and precision is high, and cost is high, and depth-to-width ratio will be far below the microchannel of wet etching acquisition.It is low that wet etching then has a cost, the depth-to-width ratio advantages of higher of gained microchannel.
In fact, although innumerable about the document of the making of microchannel, mechanism, application, for how to separate the microchannel from silicon substrate, then rarely have report on the document.Be to have mentioned several separation methods commonly used, i.e. physics sanding and polishing, plasma etching and chemical thinning back side in 5,997,713 United States Patent (USP)s in the patent No..It seems from existing information, the physics sanding and polishing causes the structural strength of microchannel to reduce easily to the silicon chip injury, is unfavorable for following process; Plasma etching then cost compare is high, and chemical thinning back side mainly is to utilize KOH solution that the back side is corroded, and silicon micro-channel is come out, but because the anisotropic etch characteristic of alkaline solution, so that surface smoothness is short of to some extent.In addition, above several separation methods commonly used all must be proceeded in two phases: the one, obtain required MCA by anodised method; The 2nd, will process again after the ready-made MCA taking-up.And in fact, as far back as 2002, V.Lehmann just just mentioned in " electrochemistry of silicon " (Electrochemistry of Silicon) book by regulating the etching electric current to the maximum current J that forms greater than porous silicon
Ps, and make reaction from becoming porose area to be transitioned into polishing area, can realize in etching process the simple and easy separation method to the N-shaped silicon micro-channel.And in fact the method for the separation of p-type silicon micro-channel and not exclusively applicable, reason as V.Lehmann in " electrochemistry of silicon " book, point out in the forming process of the grand hole of p-type silicon, the current density of hole point is much smaller than crucial electric current J
Ps, this point keeps J with the grand hole of N-shaped silicon forming process mesopore point electric current always
PsVery large difference is arranged.This means and do not reach J at the etching electric current in the manufacturing process for the p-type microchannel
PsBefore, polishing has begun.
The present invention has overcome in the prior art physics sanding and polishing and chemical thinning back side to the structure of silicon micro-channel and the defective on the following process.Utilize the p-type silicon micro-channel in the characteristics of hole cusp current density less than crucial electric current Jps, the present invention propose a kind of make the p-type silicon micro-channel in etching process with the method for substrate separation.The present invention is by changing intensity of illumination, electric current, the conditions such as voltage are controlled course of reaction, easy and simple to handle, avoid the physics polishing to the damage that damage and the chemical attack of silicon micro-channel brings silicon face, can prepare 300um with the grand hole of the p-type of interior any degree of depth silicon (or claiming microchannel), had high-aspect-ratio, easily separate the advantage such as with low cost.
Summary of the invention
The present invention proposes a kind of PhotoelectrochemicalMethod Method that makes p-type silicon micro-channel and substrate separation, may further comprise the steps:
(1) preliminary treatment: at p-type silicon growth earth silicon mask layer, photoresist is applied to position and the figure of definition etching point on the described earth silicon mask layer; Carry out pre-etching again until the position of etching point presents inverted pyramid structure;
(2) deep etching: regulate light intensity and excite carrier concentration in the silicon chip, in corrosive liquid, utilize the etching electric current to carrying out vertical deep etching through the pretreated described p-type silicon of step (1), form the microchannel;
(3) peel off: in hydrofluoric acid solution, the size of regulating etch voltage or etching electric current makes the etching electric current carry out lateral etching in point position, the hole of described microchannel, forms separating of described microchannel and silicon substrate.
Wherein, form described earth silicon mask layer by thermal oxide or LPCVD growth in the step (1).Described inverted pyramid structure refers to p-type silicon is positioned over and carries out anisotropic etch in the alkaline solution, the structure when obvious cross pattern appears in the position that microscopically is observed etching point.Wherein, described alkaline solution is 25% tetramethyl ammonium hydroxide solution.
Wherein, control the degree of depth of described microchannel in the step (2) by the length of controlling the described deep etching time.Described corrosive liquid is the HF solution that contains the 2mol/L of deionized water and dimethyl formamide DMF, and the pH value is 1-4; And in order to the surfactant Triton-X 100 of the wetability that increases described p-type silicon and corrosive liquid.Described etching electric current is 5-10mA/cm
2, current constant during etching, bias voltage are 11-15V.
Wherein, the back side and the saturated aqueous common salt conducting solution even contact of p-type silicon in the step (2).Keep the etching electric current by the intensity of illumination that changes the p-type silicon back side in the step (2).
Wherein, by reducing described etching voltage or increasing the etching electric current, reach upper limit generation saltus step so that lamp is pressed in the step (3), with lateral etching electric current take in the etching electric current this moment, carries out lateral etching.Wherein, preferred etching voltage is 9-10V.
Among the present invention, p-type silicon refers to the oblique 7 degree silicon chips in p-type (100) crystal orientation, resistivity 2-5 Ω * cm.The earth silicon mask layer that utilizes the BOE etching solution to remove in the step (1) not have described photoresist to cover comes out the position of described etching point from the earth silicon mask layer, remove photoresist again, obtain etching point figure.
The present invention is by PhotoelectrochemicalTechnique Technique, and the size of regulating etch voltage or etching electric current forms lateral etching, until the hole wall on the horizontal direction is run through, realization p-type silicon micro-channel separates with substrate.When adjusting etching electric current increases hardly along with the increase of light intensity, illustrate that lateral etching occurs, and be vertical etching and lateral etching coexistence, and vertically reaction accounts for main.When continuing to increase the etching electric current, the lateral etching electric current occupies leading gradually, and lateral etching speed increases.Consider the upper voltage limit of the used LED infrared array lamp of experiment, general etching electric current is unsuitable excessive, is controlled at 15mA/cm
2In, so that optical pressure is unlikely to surpass the operating voltage of LED lamp.Regulate the etching lower voltage to etching voltage so that etching electric current when increasing hardly along with the increase of light intensity, at this moment lateral etching can not be ignored, and lateral etching namely occurs this moment.The present invention proposes to produce the lateral etching electric current by reducing etching voltage (or claiming bias voltage, etching bias voltage) or strengthening the etching electric current with innovating; And the present invention presses saltus step to judge whether to occur lateral encroaching by lamp.
Compared with prior art, the inventive method has avoided the physics polishing to the damage that damage and the chemical attack of silicon micro-channel brings silicon face, can produce 300um with the grand hole of the p-type of interior any degree of depth silicon (or claiming microchannel), has high-aspect-ratio, easily separate advantage with low cost.
Description of drawings
Fig. 1 is the flow chart that the present invention makes the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation.
Fig. 2 is that the present invention makes the position of etching point in the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation be the schematic diagram of inverted pyramid structure.
Fig. 3 is that the present invention makes etching tank apparatus structure schematic diagram used in the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation.
Fig. 4 (a) is that the inventive method is by reducing the schematic diagram of the microchannel after etching voltage is peeled off.
Fig. 4 (b) is that the inventive method is by reducing the partial enlarged drawing of the microchannel after etching voltage is peeled off.
Fig. 5 is the schematic diagram of the microchannel after peeling off by increase etching electric current by the inventive method.
Fig. 6 is the programme-control interface schematic diagram of the inventive method.
Fig. 7 is electric current, bias voltage, the lamp pressure temporal evolution figure that the inventive method is peeled off by increasing electric current, and wherein abscissa is the time, and unit is second; Ordinate is electric current, bias voltage, lamp pressure, and the unit of electric current is mA/cm
2, the unit that bias voltage and lamp are pressed is the V(volt).
Fig. 8 is electric current, bias voltage, the lamp pressure temporal evolution figure that the inventive method is peeled off by reducing etching voltage, and wherein abscissa is the time, and unit is second; Ordinate is electric current, bias voltage, lamp pressure, and the unit of electric current is mA/cm
2, the unit that bias voltage and lamp are pressed is the V(volt).
Fig. 9 is the partial schematic diagram by a sample of the inventive method gained.
The specific embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail, and protection content of the present invention is not limited to following examples.Under the spirit and scope that do not deviate from inventive concept, variation and advantage that those skilled in the art can expect all are included in the present invention, and take appending claims as protection domain.
This method makes the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation comprise preliminary treatment, deep etching and peels off three steps.
1. preliminary treatment, such as Fig. 1 (a) to shown in Fig. 1 (e):
(1) chooses (100) crystal orientation p-type silicon chip, resistivity 2-5 Ω * cm.
(2) by thermal oxide growth earth silicon mask layer.
(3) figure in lithographic definition hole.
(4) with BOE(Buffered oxide etchant) etching solution, the oxide layer of removal silicon comes out the hole that needs etching from the earth silicon mask layer, remove afterwards photoresist again, obtains required figure.
(5) in alkaline solution (tetramethyl ammonium hydroxide solution such as 25%), carry out anisotropic etch, when under microscope bottom, seeing obvious cross pattern, stop corrosion, namely obtained required inverted pyramid structure this moment.
2. deep etching (Optical Electro-Chemistry process), shown in Fig. 1 (f):
There is well the p-type silicon of inverted pyramid structure in the mixed liquor of hydrofluoric acid containing, to carry out Optical Electro-Chemistry etching, i.e. anodic oxidation etching; Wherein anodised corrosive liquid is the HF solution that is added with the 2mol/L of deionized water and dimethyl formamide (DMF), and suitably adds hydrochloric acid and regulate pH value to 1-4, and adds micro-surfactant Triton-X 100 (C
34H
62O
11) increase the wetability of silicon chip and corrosive liquid; In anode oxidation process, come the concentration of the required carrier of provocative reaction by regulating light intensity; The etching electric current generally is set in 5-10mA/cm
2, the constant current etching, bias voltage is set as: 11-15V, reaction is at room temperature carried out, and etch period is in 12 hours.
The contact at the back side of P type silicon is by the purpose that contact reach even contact of conducting solution (saturated aqueous common salt) with silicon chip in the Optical Electro-Chemistry etching.Excite electron hole pair in the silicon chip by the intensity of illumination that changes the P type silicon back side, under positive electric field action, electronics is shifted to saturated aqueous common salt one side, and with saturated aqueous common salt one side in hydrogen ion generation reduction reaction, hydrofluoric acid one side is then shifted in the hole, react with silicon, thereby keep the etching electric current.
In etching during along the most advanced and sophisticated deep etching of inverted pyramid because etch rate and the electric current of p-type silicon be directly proportional, when electric current one regularly, etching depth and etch period are directly proportional and can control etching depth by the length of control etch period.
3. peel off, shown in Fig. 1 (f):
When the microchannel reaches required etching depth, this moment is by strengthening the etching electric current, so that the etching electric current is when increasing hardly along with the increase of light intensity, illustrate that lateral etching occurs, and be vertical etching and lateral etching coexistence, and vertically reaction accounts for mainly, when continuing to increase the etching electric current, the lateral etching electric current occupies leading gradually, and lateral etching speed increases; Consider the upper voltage limit of the used LED infrared array lamp of experiment, general etching electric current is unsuitable excessive, is controlled at 15mA/cm
2In, so that optical pressure is unlikely to surpass the operating voltage of LED lamp.
According to document (Lehmann et al, The Physics of Macropore Formation in Low-Doped p-Type Silicon, Journal of The Electrochemical Society, 146 (8) 2968-2975 (1999)) the formation principle of the grand hole of described p-type silicon: the etching electric current is mainly wanted dissufion current to deduct drift current and is obtained i.e.: I etching=I diffusion-I drift (I etching=I sidewall+I hole point); Wherein dissufion current I diffusion is mainly by carrier concentration, and fluorinion concentration decision, drift current I drift are that institute's biasing determines by electric field then; In the silicon forming process of grand hole, since point effect, the I sidewall＜＜I hole point, so lateral etching can be ignored; And when bias voltage reduced, I sidewall, I hole point reduced, and when voltage dropped to the order of magnitude that makes them and can compare, at this moment lateral etching can not be ignored, and lateral etching namely occurs this moment.In fact, for so that detachment rate (being lateral encroaching) is fast, general voltage can not be too low, otherwise reaction is too slow; In the general experiment by progressively reducing etching voltage so that etching electric current when increasing hardly along with the increase of light intensity, this moment, voltage was optimal value.The about 5-10V of preferred voltage among the present invention.
By strengthening electric current so that the method that separate with silicon substrate the p-type microchannel is as follows:
1, chooses the p-type silicon chip of oblique 7 degree in (100) crystal orientation, resistivity 2-5 Ω * cm;
2, adopt thermal oxide to form silica as mask;
3, the good window of lithographic definition (2um*2um) array, and by developing, bottoming glue goes the step such as silica to define window;
The silicon chip that 4, will define window is put into TMAH (80 ℃ of TMAH) corrosion, and frequently pulls out under microscope bottom and watch, until see that clearly as shown in Figure 2, this moment, silicon chip was the silicon chip that is carved with inverted pyramid structure till the cross;
5, the silicon chip that will carve inverted pyramid is packed in the etching groove, install device, pour the hydrofluoric acid corrosive liquid of 2M into, the etching total current is set as 510mA, the etching groove bias voltage is set as 13V, the optical pressure upper limit is set as 11.5V, total time upper limit is set as 12h, splitting time is set as 25min, beginning Optical Electro-Chemistry etching; As shown in Figure 6, etching condition can carry out the parameter setting on computers, and can revise in etching process as required.
6, after the etching 5 hours, as shown in Figure 7, the etching current setting value is strengthened, be set as 19mA/cm
2The etching bias voltage remains unchanged, so that the lamp pressure holding is continuous rise to the lamp that sets and press near the limit till, this moment lamp occuring presses saltus step, it is transverse current that Partial Conversion is arranged in the etching electric current, and can not ignore, lateral encroaching has namely occured, this moment, vertically etched portions continued deep etching, but because lateral etching part position fixes, so that the impact of vertical etching that the degree of depth of the whole microchannel plate that separates is not meanwhile occured, shown in Fig. 4 (b), although below, separating interface place does not affect the degree of depth of microchannel, top because vertical etching has formed the passage of certain depth.We keep this state after 1 hour like this, the p-type silicon micro-channel of acquisition and substrate separation, as shown in Figure 5.
By reducing voltage so that the method that separate with silicon substrate the p-type microchannel is as follows:
1, chooses the p-type silicon chip in (100) crystal orientation, resistivity 2-5 Ω * cm;
2, adopt thermal oxide to form silica as mask;
3, the good window of lithographic definition (2um*2um) array, and by developing, bottoming glue goes the step such as silica to define window;
The silicon chip that 4, will define window is put into TMAH (80 ℃ of TMAH) corrosion, and frequently pulls out under microscope bottom and watch, until see that clearly as shown in Figure 2, this moment, silicon chip was the silicon chip that is carved with inverted pyramid structure till the cross;
5, the silicon chip that will carve inverted pyramid is packed in the etching groove, install device, pour the hydrofluoric acid corrosive liquid of 2M into, be 510mA with the etching current settings, the etching groove bias voltage is set as 13V, the optical pressure upper limit is set as 11.5V, total time upper limit is set as 12h, splitting time is set as 25min, beginning Optical Electro-Chemistry etching; Etching condition can carry out the parameter setting on computers, and can revise in etching process as required.
6, after the etching 5 hours, as shown in Figure 8, reduce etching voltage, be set as 5V, and the etching electric current remains unchanged so that the lamp pressure holding is continuous rise to the lamp that sets and press near the limit till, this moment lamp occuring presses saltus step, it is transverse current that Partial Conversion is arranged in the etching electric current, and can not ignore, and lateral encroaching has namely occured.Kept 1 hour, the p-type silicon micro-channel of acquisition and substrate separation, as shown in Figure 4.
Claims (11)
1. a PhotoelectrochemicalMethod Method that makes p-type silicon micro-channel and substrate separation is characterized in that, may further comprise the steps:
(1) preliminary treatment: at p-type silicon growth earth silicon mask layer, photoresist is applied to position and the figure of definition etching point on the described earth silicon mask layer; Carry out pre-etching again until the position of etching point presents inverted pyramid structure;
(2) deep etching: regulate light intensity and excite carrier concentration in the silicon chip, in corrosive liquid, utilize the etching electric current to carrying out vertical deep etching through the pretreated described p-type silicon of step (1), form the microchannel;
(3) peel off: in hydrofluoric acid solution, the size of regulating etch voltage or etching electric current makes the etching electric current carry out lateral etching in point top position, the hole of described microchannel, forms separating of described microchannel and silicon substrate.
2. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, form described earth silicon mask layer by thermal oxide or LPCVD growth in the step (1).
3. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, inverted pyramid structure described in the step (1) refers to p-type silicon is positioned over and carries out anisotropic etch in the alkaline solution, the structure when obvious cross pattern appears in the position that microscopically is observed etching point.
4. make as claimed in claim 3 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, described alkaline solution is 25% tetramethyl ammonium hydroxide solution.
5. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, control the degree of depth of described microchannel in the step (2) by the length of controlling the described deep etching time.
6. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, corrosive liquid described in the step (2) is the HF solution that contains the 2mol/L of deionized water and dimethyl formamide DMF, and the pH value is 1-4; With surfactant Triton-X 100.
7. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, the etching electric current is 5-10mA/cm described in the step (2)
2, current constant during etching, bias voltage are 11-15V.
8. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, the p-type silicon back side and saturated aqueous common salt conducting solution even contact in the step (2).
9. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, keep the etching electric current by the intensity of illumination that changes the p-type silicon back side in the step (2).
10. make as claimed in claim 1 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, make the lamp pressure reach upper limit generation saltus step by reducing described etching voltage or increasing described etching electric current in the described step (3), this moment, the lateral etching electric current became to take as the leading factor, carried out lateral etching.
11. make as claimed in claim 11 the PhotoelectrochemicalMethod Method of p-type silicon micro-channel and substrate separation, it is characterized in that, described etching voltage is 5-10V.
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| CN104233430A (en) * | 2014-07-29 | 2014-12-24 | 中国科学院西安光学精密机械研究所 | Preparation methods of nanopore-arrayed anodic alumina membrane and nanopore-arrayed anodic alumina microchannel plate |
| CN104587567A (en) * | 2015-01-05 | 2015-05-06 | 华南师范大学 | Preparation method for miniature hollow silicon needle |
| CN109292731A (en) * | 2018-09-11 | 2019-02-01 | 西南交通大学 | Micro-nano processing method based on electrochemistry friction induction |
| CN111261506A (en) * | 2018-11-30 | 2020-06-09 | 东泰高科装备科技有限公司 | Semiconductor device photochemical etching method and device |
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Cited By (4)
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| CN104233430A (en) * | 2014-07-29 | 2014-12-24 | 中国科学院西安光学精密机械研究所 | Preparation methods of nanopore-arrayed anodic alumina membrane and nanopore-arrayed anodic alumina microchannel plate |
| CN104587567A (en) * | 2015-01-05 | 2015-05-06 | 华南师范大学 | Preparation method for miniature hollow silicon needle |
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| CN111261506A (en) * | 2018-11-30 | 2020-06-09 | 东泰高科装备科技有限公司 | Semiconductor device photochemical etching method and device |
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Address after: 200062 Putuo District, Zhongshan North Road, No. 3663, Co-patentee after: Shanghai Putai technology venture Limited by Share Ltd Patentee after: East China Normal University Address before: 200062 Putuo District, Zhongshan North Road, No. 3663, Co-patentee before: Shanghai Optech Technology Carve Out Co., Ltd. Patentee before: East China Normal University |
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