CN102868411B - Cyclic redundancy check (CRC) inverted sequence serial decoding algorithm, expanded parallel inverted sequence serial decoding method and device - Google Patents

Abstract

The invention discloses a cyclic redundancy check (CRC) inverted sequence serial decoding algorithm, an expanded parallel inverted sequence serial decoding method and a device. By means of a last-in-first-out (LIFT) mode, correct decoding of zero initial state CRC coding can be achieved, correct decoding of non-zero initial state CRC coding can be achieved, and a clock can rapidly perform CRC decoding to a plurality of input bits. Compared with decoding algorithms, decoding methods and devices in prior art, the decoding algorithm, the decoding method and the device have the advantages that characteristics of CRC coding and decoding are fully used for performing inverted sequence decoding, zero filling operation is not required, and decoding of CRC coding in any initial state of a register can be performed; and by means of a parallel structure, arithmetic speeds are fast, robust, high-speed, parallel and length-variable CRC decoding is achieved, integration and implement of hardware are facilitated, electrical system overhead is saved, and system decoding efficiencies are improved.

Description

The parallel backward coding/decoding method of CRC backward serial decoding algorithm, expansion and device

Technical field

Relate to when this in communication technical field compiling and separate towering technology, it relates to a kind of cyclic redundancy check (CRC) (CRC, Cyclic Redundancy Check) decoding algorithm, backward coding/decoding method and device.

Background technology

CRC coding is a kind of conventional error check code, the CRC coding of multiple different length is all employ, to ensure the correctness of information transmission under various transformat in the agreement of each versions such as Wideband Code Division Multiple Access (WCDMA)/Time Division-Synchronous Code Division Multiple Access/long evolving system (WCDMA/TD-SCDMA/LTE).

CRC coding is a kind of systemic circulation code, and the data after coding are divided into information sequence and verification sequence two parts, and information sequence is on a left side, and verification sequence is on the right side.CRC coding is as a kind of cyclic code, and its verification sequence often circulates one, all may as the verification sequence of a certain particular message sequence.

General encoding and decoding principle:

Send information sequence b ₀b ₁b _n-1b _ncorresponding multinomial is M (X)=b ₀x ⁿ+ b ₁x ^n-1+ b _n-1x+b _n, generator polynomial G (X)=p _mx ^m+ p _m-1x ^m-1+ p ₁x+p ₀, verification sequence R (X)=M (X) × X ^mmod G (X) corresponding multinomial is R (X)=r _m-1x ^m-1+ r _m-2x ^m-2+ _r1X+r ₀, send sequence M _s(X)=M (X) × X ^m+ R (X); Receiving sequence M _r(X), if zero defect receives M _r(X)=M _s(X), then M _r(X) mod G (X)=0, otherwise make mistakes.

Generate CRC check position as from the foregoing and receiving sequence is verified and all realized by the mode doing division for mould with G (X); Division circuit uses feedback shift register to realize usually, Fig. 1 is that existing m level feedback shift register is to realize the structural representation of CRC encoder, dwell vessel original state is generally complete zero (i.e. zero initial state), G1, G2 are two switching circuits, when G1 is closed, G2 disconnects, generate verification sequence; When G1 disconnection, G2 close, output verification sequence.Fig. 2 is the CRC decoder architecture schematic diagram that existing m level shift register realizes decoding, and decoder is zero initial state, when G1 is closed, G2 disconnects, carries out error checking and correction; When G1 disconnection, G1 close, output verification result, full null sequence represents receiving sequence zero defect.

Existing CRC decoder majority all realizes based on this principle, adopts the CRC decoder of this structure to be the positive sequence processing mode of a kind of first in first out (FIFO); This decoder can realize the decoding of zero initial state, but cannot complete the channel error judgement work of non-zero initial state CRC coding.

Prior art also has the mode adopting parallel decoding, as application number be 200910085524.4, name is called " rapid cyclic redundancy check encoding method and device ", it discloses a kind of mode of parallel order decoding, this kind of mode limits the integral multiple that decoding sequence length should be concurrent operation bit wide, therefore when incoming bit stream number is not the integral multiple of parallel bit wide, zero bit adding some according to incoming bit stream length before it is needed to form decoding sequence, processing method relative complex, affects processing speed.

Summary of the invention

For the deficiencies in the prior art, the technical problem to be solved in the present invention is to provide a kind of CRC backward serial decoding algorithm and the parallel backward coding/decoding method according to the expansion of this backward serial decoding algorithm, it adopts the mode that last in, first out (LIFO), being correctly decoded of zero initial state CRC coding can not only be realized, and being correctly decoded of the CRC coding of non-zero initial state can be realized, CRC decoding rapidly can be carried out to multiple input bit by a clock.

For achieving the above object, technical scheme provided by the present invention is: a kind of CRC backward serial decoding algorithm, comprises the steps:

A: (p is set ₀, p ₁, p _m-1, p _m) (p ₀=1, p _m=1) be generator polynomial G (X)=p _mx ^m+ p _m-1x ^m-1+ _p1X+p ₀low order item to the coefficient of high-order term, the status switch arranging t register i is x _m(t) x _m-1(t) ... x ₂(t) x ₁t (), the deal with data arranging t input is b (t), X (t+1) for CRC coding circuit to be generated the buffer status in t+1 moment by information sequence b (t), and corresponding states sequence is x _m(t+1) x _m-1(t+1) ... x ₂(t+1) x ₁(t+1);

The coefficient p of i the item of B: defining polynomial G (X) _ifor i-th row the 1st of rank, m × 1 matrix P ' arranges, wherein i=1,2 ... m-1, P ' m the capable 1st be classified as 1, namely $P^{\′}=\left[\begin{array}{c}{p}_1\\ p_2\\ \·\·\·\\ p_{m-1}\\ 1\end{array}\right];$ The jth row the 1st of definition m rank square formation Γ is classified as jth row the 1st row of P ', j=1 in base, and 2 ... m, the jth row jth+1 of definition Γ is classified as 1, wherein, and j=1,2 ... m-1, other position of definition Γ is 0, namely $\mathrm{\Γ}=\left[\begin{array}{ccccc}{p}_1& 1& 0& \·\·\·& 0\\ p_2& 0& 1& \·\·\·& 0\\ \·\·\·& \·\·\·& \·\·\·& \·\·\·& \·\·\·\\ p_{m-1}& 0& 0& \·\·\·& 1\\ 1& 0& 0& \·\·\·& 0\end{array}\right];$

C: X (t+1) is reversed as x ₁(t+1) x ₂(t+1) ... x _m-1(t+1) x _mand be defined as X ' (t+1), according to relational expression (t+1) $X^{\′}\left(t\right)=\mathrm{\Γ}\⊗X^{\′}(t+1)\⊕\left[\begin{array}{c}0\\ \·\·\·\\ 0\\ b\left(t\right)\end{array}\right]$ Calculate t buffer status x ₁(t) x ₂(t) ... x _m-1(t) x _m(t), and be defined as X ' (t), in formula for modular two multiplication method, for nodulo-2 addition computing;

D: if the backward of gained X ' (t) is consistent with status switch X (t) during coding in step C, then decoding is correct, otherwise decoding error.

When CRC code registers status switch X (t) for complete zero time, judge whether X ' (t) is complete zero, if then CRC decoding is correct, otherwise decoding error; When CRC code registers status switch X (t) is for non-zero, judge that whether the backward of X ' (t) is equal with X (t), if then CRC decoding is correct, otherwise decoding error.

The present invention also provides a kind of parallel backward coding/decoding method according to above-mentioned CRC backward serial decoding algorithm expansion, comprises the steps:

The initial condition of the m level register of A: definition CRC coding is X _mx ₁, parallel processing bit wide is w, and described w satisfies condition 1≤w≤l-m, and wherein, l is decoding sequence length; Definition receiving sequence M _r(X), its backward is defined as decoding sequence a ₁a _l;

B: based on matrix P ', Γ, calculates inquiry matrix $P_w=[{\mathrm{\Γ}}^{w-1}\⊗P^{\′}{\mathrm{\Γ}}^{w-2}\⊗P^{\′}\·\·\·\mathrm{\Γ}\⊗P^{\′}{P}^{\′}];$

C: carry out CRC walk abreast backward decoding process, i.e. R=crc ^-1(m, w, P _w, a ₁α _l), step is as follows:

If L=l-m; for rounding operation;

Cycle calculations is carried out according to following formula:

$R=P_w\⊗{\left[\begin{array}{ccc}{a}_{i*w+1}& \·\·\·& q_{(i+1)*w}\end{array}\right]}^T,$

$\left[\begin{array}{ccc}{a}_{(i+1)*w+1}& \·\·\·& a_{(i+1)*\left(w\right)+m}\end{array}\right]=\left[\begin{array}{ccc}{a}_{(i+1)*w+1}& \·\·\·& a_{(i+1)*\left(w\right)+m}\end{array}\right]\⊕R^T,$

L=L-w, wherein, i is variable, and its value is the integer from 0 to k-1;

If L ≠ 0, continue according to following formulae discovery:

$R=P_L\⊗{\left[\begin{array}{ccc}{a}_{k*w+1}& \·\·\·& q_{k*w+L}\end{array}\right]}^T,$

$\left[\begin{array}{ccc}{a}_{l-m+1}& \·\·\·& a_l\end{array}\right]=\left[\begin{array}{ccc}{a}_{l-m+1}& \·\·\·& a_l\end{array}\right]\⊕R^T,$

Finally, R=[a is obtained _l-m+1α _l], be expressed as R=[ _sm ... s ₁];

D: by the backward s of status switch R ₁s _mwith X _mx ₁relatively, equal expression CRC decodes correct, does not wait and represents CRC decoding error.

Further, step C is by grouping or realization of once decoding.

As CRC code registers status switch X _mx ₁for complete zero time, judge s ₁s _mwhether be complete zero, if then CRC decoding is correct, otherwise decoding error; As CRC code registers status switch X _mx ₁during for non-zero, judge _s1 ... s _mwhether with X _mx ₁equal, if then CRC decoding is correct, otherwise decoding error.

The present invention also provides a kind of CRC to walk abreast backward decoding device, and it comprises:

CRC maps transfer matrix generation module, for the coefficient (p by CRC generator polynomial G (X) ₀, p ₁, p _m-1, p _m) in p _m-1to p ₁generate m × 1 column matrix P ' and m rank square formation Γ;

CRC map locating matrix generation module, for by P ' matrix and Γ matrix according to setting relational expression generator polynomial map locating matrix P _w;

CRC backward decoding process module, to walk abreast backward decoding algorithm for utilizing CRC

R=crc ^-1(m, w, P _w, α ₁α _l) obtain CRC buffer status sequence s _ms ₁;

Decoding sequence backward comparison module, for the status switch s that will obtain _ms ₁backward s ₁s _mwith X _mx ₁relatively, equal expression CRC decodes correct, does not wait and represents RC decoding error.

Technical scheme provided by the present invention, has following main feature:

(1) adopt the mode that last in, first out (LIFO) to decode, namely backward decoding is carried out to receiving sequence;

(2) zero initial state, non-zero initial state CRC are encoded, all can decode; The fail safe of CRC encoding channel transmission can be improved by the initial state of adjustment register, there is certain anti-ability of cracking.

(3) adopt parallel arithmetic mode, clock needed for computing is about the 1/w of clock needed for existing serial computing, improves operation efficiency, and wherein w is concurrent operation bandwidth;

(4) inquire about matrix to be generated by generator polynomial, parallel decoding figure place can be expanded arbitrarily according to w size;

(5) without the need to zero padding operation, can single decoding, also can packet decoding;

Compared with prior art, the present invention takes full advantage of the feature of CRC encoding and decoding, and backward is decoded, and can decode to the CRC coding of any initial state of register; Adopt parallel organization, fast operation, achieve robust, high speed variable the CRC of line length decode, be convenient to hardware integration and realization, save Circuits System expense, improve the decoding efficiency of system.

Accompanying drawing explanation

Fig. 1 is p _mx ^m+ p _m-1x ^m-1|+...+p ₁x ¹+ p ₀(p ₀=1, p _m=1) corresponding serial type coding circuit;

Fig. 2 is p _mx ^m+ p _m-1x ^m-1+ ...+p ₁x ¹+ p ₀(p ₀=1, p _m=1) corresponding FIFO serial type decoding circuit;

Fig. 3 is p _mx ^m+ p _m-1x ^m-1+ ...+p ₁x ¹+ p ₀(p ₀=1, p _m=1) corresponding LIFO serial type decoding circuit;

Fig. 4 is inquiry matrix P definition;

Fig. 5 is as w≤m, grouping CRC backward decoding algorithm schematic diagram;

Fig. 6 is as w > m, grouping CRC backward decoding algorithm schematic diagram;

Fig. 7 is as w=l-m, single CRC backward decoding algorithm schematic diagram;

Fig. 8 is CRC backward parallel decoding flow chart;

Fig. 9 is CRC backward apparatus for parallel decoding figure.

Embodiment

Below in conjunction with accompanying drawing, the present invention is further detailed explanation:

First the present invention provides a kind of CRC backward serial decoding algorithm, and this algorithm is applicable to one or more serial received signal, makes a concrete analysis of as follows:

Definition (p ₀, p ₁, p _m-1, p _m) (p ₀=1, p _m=1) for the low order item of generator polynomial G (X) is to the coefficient of high-order term; Verification sequence length is m; Parallel processing length is w; Existing CRC coding is generally all register zero initial equilibrium state, establishes x herein _it state that () (1≤i≤m) is t register i; The deal with data that b (t) inputs for t, in requisition for process information sequence b ₀b ₁b _n.

Carry out state analysis to Fig. 1 can obtain

$\left[\begin{array}{c}{x}_m(t+1)\\ x_{m-1}(t+1)\\ \·\·\·\\ x_2(t+1)\\ x_1(t+1)\end{array}\right]=\left[\begin{array}{ccccc}{p}_{m-1}& 1& 0& \·\·\·& 0\\ p_{m-2}& 0& 1& \·\·\·& 0\\ \·\·\·& \·\·\·& \·\·\·& \·\·\·& \·\·\·\\ p_1& 0& 0& \·\·\·& 1\\ p_0& 0& 0& \·\·\·& 0\end{array}\right]\⊗(\left[\begin{array}{c}{x}_m\left(t\right)\\ x_{m-1}\left(t\right)\\ \·\·\·\\ x_2\left(t\right)\\ x_1\left(t\right)\end{array}\right]\⊗\left[\begin{array}{c}b\left(t\right)\\ 0\\ \·\·\·\\ 0\\ 0\end{array}\right]),$

Order $F=\left[\begin{array}{ccccc}{p}_{m-1}& 1& 0& \·\·\·& 0\\ p_{m-2}& 0& 1& \·\·\·& 0\\ \·\·\·& \·\·\·& \·\·\·& \·\·\·& \·\·\·\\ p_1& 0& 0& \·\·\·& 1\\ p_0& 0& 0& \·\·\·& 0\end{array}\right],$

Above formula can be abbreviated as $X(t+1)=F\⊗(X\left(t\right)\⊕\left[\begin{array}{c}b\left(t\right)\\ \·\·\·\\ 0\\ 0\end{array}\right])---\left(1\right)$

By can be calculated determinant det (F)=p ₀there is inverse matrix F in=1 ≠ 0, F ^-1, obtained by elementary rank transform

$F^{-1}=\left[\begin{array}{ccccc}0& \·\·\·& 0& 0& 1\\ 1& \·\·\·& 0& 0& p_{m-1}\\ \·\·\·& \·\·\·& \·\·\·& \·\·\·& \·\·\·\\ 0& \·\·\·& 1& 0& p_2\\ 0& \·\·\·& 0& 1& p_1\end{array}\right],$

Therefore can be derived by (1) formula

$X\left(t\right)=F^{-1}\⊗X(t+1)\⊕\left[\begin{array}{c}b\left(t\right)\\ \·\·\·\\ 0\\ 0\end{array}\right],$

Order $\mathrm{\Γ}=\left[\begin{array}{ccccc}{p}_1& 1& 0& \·\·\·& 0\\ p_2& 0& 1& \·\·\·& 0\\ \·\·\·& \·\·\·& \·\·\·& \·\·\·& \·\·\·\\ p_{m-1}& 0& 0& \·\·\·& 1\\ 1& 0& 0& \·\·\·& 0\end{array}\right],$

Above formula is variable to be changed to

$\left[\begin{array}{c}{x}_1\left(t\right)\\ x_2\left(t\right)\\ \·\·\·\\ x_{m-1}\left(t\right)\\ x_m\left(t\right)\end{array}\right]=\left[\begin{array}{ccccc}{p}_1& 1& 0& \·\·\·& 0\\ p_2& 0& 1& \·\·\·& 0\\ \·\·\·& \·\·\·& \·\·\·& \·\·\·& \·\·\·\\ p_{m-1}& 0& 0& \·\·\·& 1\\ 1& 0& 0& \·\·\·& 0\end{array}\right]\⊗\left[\begin{array}{c}{x}_1(t+1)\\ x_2(t+1)\\ \·\·\·\\ x_{m-1}(t+1)\\ x_m(t+1)\end{array}\right]\⊗\left[\begin{array}{c}0\\ 0\\ \·\·\·\\ 0\\ b\left(t\right)\end{array}\right],$

Be abbreviated as

$X^{\′}\left(t\right)=\mathrm{\Γ}\⊗X^{\′}(t+1)\⊕\left[\begin{array}{c}0\\ \·\·\·\\ 0\\ b\left(t\right)\end{array}\right]---\left(2\right)$

(1) in formula, X (t) is the state of CRC code registers t, the verification sequence that X (t+1) is generated by information sequence b (t) for CRC coding circuit; By (2) formula, X ' (t) is calculated by X ' (t+1), b (t), if the state X (t) when the backward of X ' (t) and coding is consistent, inerrancy in transmitting procedure is described, the wrong generation of no person.As shown in Figure 3, require that list entries and status switch are all reverse, it is also reverse for finally obtaining system initial state X ' (t) to corresponding serial decoding circuitry (decoder is zero initial state), can judge the whether wrong generation of transmitting procedure accordingly.

As shown in Figure 8, according to as above analyzing, CRC serial backward coding/decoding method provided by the invention, comprises the steps:

A: (p is set ₀, p ₁, p _m-1, p _m) (p ₀=1, p _m=1) be generator polynomial G (X)=p _mx ^m+ p _m-1x ^m-1+ p ₁x+p ₀low order item to the coefficient of high-order term, the status switch arranging t register i is x _m(t) x _m-1(t) ... x ₂(t) x ₁t (), the deal with data arranging t input is b (t), X (t+1) for CRC coding circuit to be generated the buffer status in t+1 moment by information sequence b (t), and corresponding states sequence is x _m(t+1) x _m-1(t+1) ... x ₂(t+1) x ₁(t+1);

The coefficient p of i the item of B: defining polynomial G (X) _tfor i-th row the 1st of rank, m × 1 matrix P ' arranges, wherein i=1,2 ... m-1, P ' m the capable 1st be classified as 1, namely $P^{\′}=\left[\begin{array}{c}{p}_1\\ p_2\\ \·\·\·\\ p_{m-1}\\ 1\end{array}\right];$ The jth row the 1st of definition m rank square formation Γ is classified as jth row the 1st row of P ', wherein j=1, and 2 ... m, the jth row jth+1 of definition Γ is classified as 1, wherein, and j=1,2 ... m-1, other position of definition Γ is 0, namely $\mathrm{\Γ}=\left[\begin{array}{ccccc}{p}_1& 1& 0& \·\·\·& 0\\ p_2& 0& 1& \·\·\·& 0\\ \·\·\·& \·\·\·& \·\·\·& \·\·\·& \·\·\·\\ p_{m-1}& 0& 0& \·\·\·& 1\\ 1& 0& 0& \·\·\·& 0\end{array}\right];$

C: X (t+1) is reversed into x1 (t+1) x2 (t+1) ... xm-1 (t+1) xm (t+1) is also defined as X ' (t+1), according to relational expression $X^{\′}\left(t\right)=\mathrm{\Γ}\⊗X^{\′}(t+1)\⊕\left[\begin{array}{c}0\\ \·\·\·\\ 0\\ b\left(t\right)\end{array}\right]$ Calculate t buffer status X ' (t);

D: if the backward of gained X ' (t) is consistent with status switch X (t) during coding in step C, then decoding is correct, otherwise decoding error.

When CRC code registers status switch X (t) for complete zero time, judge whether X ' (t) is complete zero, if then CRC decoding is correct, otherwise decoding error; When CRC code registers status switch X (t) is for non-zero, judge that whether the backward of X ' (t) is equal with X (t), if then CRC decoding is correct, otherwise decoding error.

According to above-mentioned CRC serial backward decoding algorithm, the CRC that the invention allows for a kind of expansion walks abreast backward coding/decoding method, comprises the steps:

The initial condition of the m level register of A: definition CRC coding is X _m... X ₁, parallel processing bit wide is w, and described w satisfies condition 1≤w≤l-m, and wherein, l is decoding sequence length; Definition receiving sequence M _r(X), its backward is defined as decoding sequence a ₁a _l;

B: based on matrix P ', Γ, calculates inquiry matrix $P_w=[{\mathrm{\Γ}}^{w-1}\⊗P^{\′}{\mathrm{\Γ}}^{w-2}\⊗P^{\′}\·\·\·\mathrm{\Γ}\⊗P^{\′}{P}^{\′}];$

C: carry out CRC walk abreast backward decoding process, i.e. R=crc ^-1(m, w, P _w, a ₁a _l), finally, obtain R=[a _l-m+1a _l], be expressed as R=[s _ms ₁];

D: by the backward s of status switch R ₁s _mwith X _mx ₁relatively, equal expression CRC decodes correct, does not wait and represents CRC decoding error.

In above-mentioned steps C, CRC walk abreast backward decoding R=crc ^-1(m, w, P _w, a ₁a _l) processing mode flow process specific as follows:

If L=l-m; for rounding operation; Cycle calculations is carried out according to following formula:

$R=P_w\⊗{\left[\begin{array}{ccc}{a}_{i*w+1}& \·\·\·& q_{(i+1)*w}\end{array}\right]}^T,$

$\left[\begin{array}{ccc}{a}_{(i+1)*w+1}& \·\·\·& a_{(i+1)*\left(w\right)+m}\end{array}\right]=\left[\begin{array}{ccc}{a}_{(i+1)*w+1}& \·\·\·& a_{(i+1)*\left(w\right)+m}\end{array}\right]\⊕R^T,$

L=L-w, wherein, i is variable, and its value is the integer from 0 to k-1;

If L ≠ 0, continue according to following formulae discovery:

$R=P_L\⊗{\left[\begin{array}{ccc}{a}_{k*w+1}& \·\·\·& q_{k*w+L}\end{array}\right]}^T,$

$\left[\begin{array}{ccc}{a}_{l-m+1}& \·\·\·& a_l\end{array}\right]=\left[\begin{array}{ccc}{a}_{l-m+1}& \·\·\·& a_l\end{array}\right]\⊕R^T;$

Finally, R=[a is obtained _l-m+1a _l], be expressed as R=[s _ms ₁].On software simulating, undertaken by following table:

Note: due to P _lmiddle L < w, P as shown in Figure 4 _lbe included in P _win, need not regenerate.

As w≤m, CRC backward decoding algorithm is realized by grouping, as shown in Figure 5;

As w > m, CRC backward decoding algorithm is also realized by grouping, as shown in Figure 6;

As w=l-m, CRC backward decoding algorithm can once have been decoded, and once decoding comprises a matrix operation and an add operation, as shown in Figure 7;

So be the serial scheme in Fig. 3 when the parallel bit wide of CRC backward decoding need meet following condition 1≤w≤l-m, w=1.

Especially, when CRC is encoded to zero initial state, in the poly-D of step, judge that R is as complete zero, if then CRC check is correct, otherwise the wrong generation of receiving sequence.

Basic thought of the present invention is, utilize CRC serial inverse operation principle, a kind of CRC backward concurrent decoding algorithm protecting exhibition is proposed, by CRC generator polynomial map locating matrix, packet transaction is carried out by the bit wide arranging the decoding of Parallel CRC backward, finally obtain the dwell vessel original state of CRC encoder, complete the backward verification of CRC coding.

The present invention can use at the CRC decoding unit of the baseband chips such as WCDMA/TD-SCDMA/LTE, saves the required clock of CRC decoding, improves chip whole efficiency; The initial condition of CRC encoder also can be set, improve the fail safe of transfer sequence.

In order to can make technical scheme of the present invention and technical advantage more clear, further illustrate the quick CRC coding/decoding method of the present invention for baseband chip below in conjunction with embodiment.

Embodiment 1 (zero initial state):

All use code length is m=8 CRC is encoded to example with baseband chip in WCDMA/TD-SCDMA/LTE, parallel bit wide w=4, CRC generator polynomial of encoding is G (x)=X ⁸+ X ⁷+ X ⁴+ X ³+ X+1, information sequence M (x)=X ¹³+ X ¹²+ X ⁹+ X ⁸+ X ⁵+ X ⁴+ X ²+ X, corresponding sequence is: M (x)=[11001100110110], G (x)=[110011011].The present embodiment divides zero initial state, non-zero initial state two kinds of situations.

Under zero initial state, [X _mx ₁]=[0...0], after adopting CRC coding method shown in Fig. 1 to calculate R (x)=X ⁷+ X ⁴+ X ²+ X, corresponding R (x)=[10010110].

According to cardiopulmonary bypass in beating heart redundancy check backward decoding method decodes of the present invention:

Steps A, [X _mx ₁]=[0...0]; Information sequence M (x)=[11001100110110], verification sequence R (x)=[10010110],

Zero defect receiving sequence M _r(X) backward [a ₁a _l]=[0110100101101100110011]; W=4; L=22; M=8;

Step B, $P^{\&prime;}=\left[\begin{array}{c}1\\ 0\\ 1\\ 1\\ 0\\ 0\\ 1\\ 1\end{array}\right],$ $\mathrm{\&Gamma;}=\left[\begin{array}{cccccccc}1& 1& 0& 0& 0& 0& 0& 0\\ 0& 0& 1& 0& 0& 0& 0& 0\\ 1& 0& 0& 1& 0& 0& 0& 0\\ 1& 0& 0& 0& 1& 0& 0& 0\\ 0& 0& 0& 0& 0& 1& 0& 0\\ 0& 0& 0& 0& 0& 0& 1& 0\\ 1& 0& 0& 0& 0& 0& 0& 1\\ 1& 0& 0& 0& 0& 0& 0& 0\end{array}\right],$ $P_4=\left[\begin{array}{cccc}0& 0& 1& 1\\ 0& 0& 1& 0\\ 1& 0& 0& 1\\ 1& 1& 1& 1\\ 0& 1& 0& 0\\ 0& 0& 1& 0\\ 1& 0& 0& 1\\ 0& 1& 1& 1\end{array}\right];$

Step C, call R=crc ^-1(m, w, P _w, a ₁a _l) obtain [s _ms ₁]=[0...0] full null sequence;

Step D, [s ₁s _m]=[X _mx ₁], CRC check is correct.Obtain conclusion for being correctly decoded.

If positive sequence CRC decoding method decodes shown in employing Fig. 2:

It is M that zero defect receives verification sequence decoding sequence _r(x)=(b ₉b _nr _m-1r ₀), M _r(X)=[1100110011011010010110], calculate [X _mx ₁]=[00000000], full null sequence.The conclusion obtained is also for being correctly decoded.

Embodiment 2 (non-zero initial state):

Other condition, with embodiment 1, divides into [X at non-zero initial state _mx ₁]=[00110110], obtain R (x)=[0,110,001 1] after adopting CRC coding method shown in Fig. 1 to calculate.

According to cardiopulmonary bypass in beating heart redundancy check backward decoding method decodes of the present invention:

[a in steps A ₁a _l]=[1100011001101100110011], P ' Γ, P in step B ₄consistent with embodiment 1, step C calls R=crc ^-1(m, w, P _w, a ₁a ^l] calculate [s _ms ₁]=[01101100] and [X _mx ₁] backward identical, CRC check is correct.Obtain conclusion for being correctly decoded.

Adopt positive sequence CRC decoding method decodes shown in Fig. 2:

Zero defect receives verification sequence M _r(X)=[1100110011011001100011], calculate [X _mx ₁]=[11110101].Obtaining conclusion is decoded in error, and as can be seen here, positive sequence CRC coding/decoding method is only applicable to zero initial state, is not suitable for non-zero initial state.

Obtain above-mentioned CRC check result by existing serial approach and need 22 clocks, and the inventive method acquisition CRC check result only needs 4 clocks, backward is decoded and can be decoded to non-zero initial state CRC coding.

Parallel CRC backward coding/decoding method of the present invention can be realized by the mode of hardware circuit or software and hardware combining.

When for hardware implementing, after chip design completes, can not modify again.Therefore because the systems such as WCDMA/TD-SCDMA/LTE all support that different lengths CRC encodes, the inquiry matrix parameter corresponding to each CRC generator polynomial obtained by the inventive method need only be solidified in systems in which, hardware selects one of them hardware logic module to carry out computing according to register configuration can realize variable-length CRC decoding.

When realizing for hardware and software combination, the mode that chip internal adopts software to calculate calculates CRC decoding, then can carry out the CRC generator polynomial of real time modifying corresponding to it by the inquiry matrix parameter updated stored in memory, to meet edition upgrading, module is general waits requirement.

Present invention also offers a kind of cardiopulmonary bypass in beating heart redundancy check backward decoding device, as shown in Figure 9, comprising:

CRC maps transfer matrix generation module, for the coefficient (p by CRC generator polynomial G (X) ₀, p ₁, p _m-1, p _m) in p _m-1to p ₁generate m × 1 column matrix P ' and m rank square formation Γ;

CRC map locating matrix generation module, for by P ' matrix and Γ matrix according to setting relational expression generator polynomial map locating matrix P _w;

CRC backward decoding process module, to walk abreast backward decoding algorithm R=crc for utilizing CRC ^-1(m, w, P _w, a ₁a _l) obtain CRC registered state sequence s _ms ₁;

Decoding sequence backward comparison module, for the status switch s that will obtain _ms ₁backward s ₁s _mwith X _mx ₁relatively, equal expression RC decodes correct, does not wait and represents CRC decoding error.

Described CRC backward decoding algorithm is by grouping or realization of once decoding.

Especially, when CRC is encoded to zero initial state, judge [s _ms ₁] whether be complete zero, if then CRC check is correct, otherwise the wrong generation of receiving sequence.

Compared with prior art, the present invention takes full advantage of the feature of CRC encoding and decoding, and backward is decoded, and can decode to the CRC coding of any initial state of register; Adopt parallel organization, fast operation, achieve robust, high speed variable the CRC of line length decode, be convenient to hardware integration and realization, save Circuits System expense, improve the decoding efficiency of system.

Certainly; the present invention also can have other various embodiments; when without prejudice to the present invention's spirit and essence thereof, those of ordinary skill in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and distortion all should belong to protection scope of the present invention.

Claims (7)

1. a CRC backward serial decode method, is characterized in that, comprise the steps:

A: (p is set ₀, p ₁, p _m-1, p _m) (p ₀=1, p _m=1) be generator polynomial G (X)=p _mx ^m+ p _m-1x ^m-1+ p ₁x+p ₀low order item to the coefficient of high-order term, the status switch arranging t register i is x _m(t) x _m-1(t) ... x ₂(t) x ₁t (), the deal with data arranging t input is b (t), X (t+1) for CRC coding circuit to be generated the buffer status in t+1 moment by information sequence b (t), and corresponding states sequence is x _m(t+1) x _m-1(t+1) ... x ₂(t+1) x ₁(t+1);

The coefficient p of i the item of B: defining polynomial G (X) _ifor i-th row the 1st of rank, m × 1 matrix P ' arranges, wherein i=1,2 ... m-1, P ' m the capable 1st be classified as 1, namely $P^{\&prime;}=\left[\begin{array}{c}{p}_1\\ p_2\\ ...\\ p_{m-1}\\ 1\end{array}\right];$ The jth row the 1st of definition m rank square formation Γ is classified as jth row the 1st row of P ', wherein j=1, and 2 ... m, the jth row jth+1 of definition Γ is classified as 1, wherein, and j=1,2 ... m-1, other position of definition Γ is 0, namely $\mathrm{\&Gamma;}=\left[\begin{array}{ccccc}{p}_1& 1& 0& ...& 0\\ p_2& 0& 1& ...& 0\\ ...& ...& ...& ...& ...\\ p_{m-1}& 0& 0& ...& 1\\ 1& 0& 0& ...& 0\end{array}\right];$

C: X (t+1) is reversed as x ₁(t+1) x ₂(t+1) ... x _m-1(t+1) x _mand be defined as X ' (t+1), according to relational expression (t+1) $X^{\&prime;}\left(t\right)=\mathrm{\&Gamma;}\&CircleTimes;X^{\&prime;}(t+1)\&CirclePlus;\left[\begin{array}{c}0\\ ...\\ 0\\ b\left(t\right)\end{array}\right]$ Calculate t buffer status x ₁(t) x ₂(t) ... x _m-1(t) x _m(t), and be defined as X ' (t), in formula for modular two multiplication method, for nodulo-2 addition computing;

D: if the backward of gained X ' (t) is consistent with status switch X (t) during coding in step C, then decoding is correct, otherwise decoding error.

2. a kind of CRC backward serial decode method according to claim 1, it is characterized in that: when CRC code registers status switch X (t) for complete zero time, judge whether X ' (t) is complete zero, if then CRC decoding is correct, otherwise decoding error; When CRC code registers status switch X (t) is for non-zero, judge that whether the backward of X ' (t) is equal with X (t), if then CRC decoding is correct, otherwise decoding error.

3. adopt a parallel backward coding/decoding method for CRC backward serial decode method expansion described in claim 1, it is characterized in that, comprise the steps:

The initial condition of the m level register of A: definition CRC coding is X _mx ₁, parallel processing bit wide is w, and described w satisfies condition 1≤w≤l-m, and wherein, l is decoding sequence length; Definition receiving sequence M _r(X), its backward is defined as decoding sequence a ₁a _l;

B: based on matrix P ', Γ, calculates inquiry matrix $P_w=[{\mathrm{\&Gamma;}}^{w-1}\&CircleTimes;P^{\&prime;}{\mathrm{\&Gamma;}}^{w-2}\&CircleTimes;P^{\&prime;}...\mathrm{\&Gamma;}\&CircleTimes;P^{\&prime;}{P}^{\&prime;}];$

C: carry out CRC walk abreast backward decoding process, i.e. R=CRC ^-1(m, w, P _w, a ₁a _l), step is as follows:

If L=l-m; for rounding operation;

Cycle calculations is carried out according to following formula:

$R=P_w\&CircleTimes;{\left[\begin{array}{ccc}{a}_{i*w+1}& ...& a_{(i+1)*w}\end{array}\right]}^T,$

$\left[\begin{array}{ccc}{a}_{(i+1)*w+1}& ...& a_{(i+1)*\left(w\right)+m}\end{array}\right]=\left[\begin{array}{ccc}{a}_{(i+1)*w+1}& ...& a_{(i+1)*\left(w\right)+m}\end{array}\right]\&CirclePlus;R^T,$

L=L-w, wherein, i is variable, and its value is the integer from 0 to k-1;

If L ≠ 0, continue according to following formulae discovery:

$R=P_L\&CircleTimes;{\left[\begin{array}{ccc}{a}_{k*w+1}& ...& a_{k*w+L}\end{array}\right]}^T,$

$\left[\begin{array}{ccc}{a}_{l-m+1}& ...& a_l\end{array}\right]=\left[\begin{array}{ccc}{a}_{l-m+1}& ...& a_l\end{array}\right]\&CirclePlus;R^T;$

Finally, R=[a is obtained _l-m+1a _l], be expressed as R=[s _ms ₁];

D: by the backward s of status switch R ₁s _mwith X _mx ₁relatively, equal expression CRC decodes correct, does not wait and represents CRC decoding error.

4. the parallel backward coding/decoding method of CRC backward serial decode method expansion according to claim 3, is characterized in that: step C is by grouping or realization of once decoding.

5. the parallel backward coding/decoding method of CRC backward serial decode method expansion according to claim 3, is characterized in that: as CRC code registers status switch X _mx ₁for complete zero time, judge s ₁s _mwhether be complete zero, if then CRC decoding is correct, otherwise decoding error; As CRC code registers status switch X _mx ₁during for non-zero, judge s ₁s _mwhether with X _mx ₁equal, if then CRC decoding is correct, otherwise decoding error.

6. adopt CRC described in claim 3 to walk abreast the device of backward coding/decoding method, it is characterized in that: comprising:

CRC maps transfer matrix generation module, for the coefficient (p by CRC generator polynomial G (X) ₀, p ₁, p _m-1, p _m) in p _m-1to p ₁generate m × 1 column matrix P ' and m rank square formation Γ;

CRC map locating matrix generation module, for by P ' matrix and Γ matrix according to setting relational expression generator polynomial map locating matrix P _w;

CRC backward decoding process module, to walk abreast backward coding/decoding method for utilizing CRC

R=CRC ^-1(m, w, P _w, a ₁a _l) obtain CRC buffer status sequence s _ms ₁;

Decoding sequence backward comparison module, for the status switch s that will obtain _ms ₁backward s ₁s _mwith X _mx ₁relatively, equal expression CRC decodes correct, does not wait and represents CRC decoding error.

7. parallel backward decoding device according to claim 6, is characterized in that: described CRC backward decoding process module is by grouping or once realize decoding.