CN102866683B - Signal conversion device and automatic testing system - Google Patents
Signal conversion device and automatic testing system Download PDFInfo
- Publication number
- CN102866683B CN102866683B CN201210261778.9A CN201210261778A CN102866683B CN 102866683 B CN102866683 B CN 102866683B CN 201210261778 A CN201210261778 A CN 201210261778A CN 102866683 B CN102866683 B CN 102866683B
- Authority
- CN
- China
- Prior art keywords
- module
- control unit
- transistor
- logic level
- chromacoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a signal conversion device, which is used for receiving system control information from an upper computer and converting the system control information into a plurality of TTL (Transistor-Transistor Logic) level signals to be output. The signal conversion device comprises a master control unit, wherein the master control unit is used for receiving the system control information from the upper computer through a USB (Universal Serial Bus) communication protocol and converting the system control information into an I2C (Inter-Integrated Circuit) communication protocol data format; the system control information is transmitted outwards and external return information is received through an I2C bus; and the master control unit is also used for outputting the TTL level signals according to the system control information. The invention also discloses an automatic testing system using the signal conversion device. In such a mode, a drive is not required to be mounted, and the required TTL level signals can be flexibly output; and the signal conversion device and the automatic testing system are suitable for controlling complex conditions.
Description
Technical field
The present invention relates to signal switch technology field, particularly relate to a kind of chromacoder and Auto-Test System.
Background technology
TTL(Transistor-Transistor Logic) circuit is a kind of logical circuit conventional in Digital Electronic Technique.Transistor-Transistor Logic level signal is not high to power requirement when the device interior transmission of computing machine and control thereof, thermal losses is low, be connected with integrated circuit and do not need expensive line driver and acceptor circuit, the high speed data transfer of computerized equipment inside can be met, be therefore widely used.
And computing machine does not have TTL output port, usually need the USB(Universal Serial Bus of computer, USB (universal serial bus)) port, usb signal is converted to Transistor-Transistor Logic level signal.
The USB-TTL conversion of prior art exports TTL signal by simulating a serial port, and it needs to install driving, and its characteristic is identical with serial port.But the Transistor-Transistor Logic level number of signals that this conversion regime exports is few, and need driving is installed, be difficult to be applied to control complicated situation.
Summary of the invention
The technical matters that the present invention mainly solves is to provide a kind of chromacoder and Auto-Test System, can export multiple required Transistor-Transistor Logic level signal flexibly.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: provide a kind of chromacoder, for from the control information of host computer receiving system, convert multiple Transistor-Transistor Logic level signal to export, it comprises: main control unit, and main control unit converts I by usb communication agreement to from the control information of host computer receiving system
2c communication protocol data form, and pass through I
2c bus outside transmission system control information and receive outside back information.Wherein, main control unit also exports multiple Transistor-Transistor Logic level signal according to system control information.
For solving the problems of the technologies described above, another technical solution used in the present invention is: provide a kind of Auto-Test System, it comprises: host computer, above-mentioned chromacoder and rear class application circuit.Chromacoder is connected with host computer, for from the control information of host computer receiving system, and converts multiple Transistor-Transistor Logic level signal to and exports.Rear class application circuit comprises signal processing circuit and to be measured, signal processing circuit is connected with chromacoder, receives Transistor-Transistor Logic level signal and export required TTL control signal after carrying out signal transacting automatically to test to be measured from chromacoder.
Compared with prior art, the invention provides a kind of chromacoder that effectively can be obtained the Transistor-Transistor Logic level signal of demand by conputer controlled, convert I by usb communication agreement to from the control information of host computer receiving system
2c communication protocol data form, and export multiple Transistor-Transistor Logic level signal according to system control information, it does not need to install driving, can directly use, also very flexible with the collocation of peripheral circuit, send out control command corresponding and can obtain the TTL signal level of any needs by host computer, thus can be applicable to control complicated situation.Further, when chromacoder of the present invention is applied to Auto-Test System, can Automated condtrol be realized, reduce costs.
Accompanying drawing explanation
Fig. 1 is the structural representation of the chromacoder of first embodiment of the invention;
Fig. 2 is the structural representation of the main control unit of the chromacoder shown in Fig. 1;
Fig. 3 is the schematic diagram of a kind of embodiment of high speed IO PIC module of the present invention;
Fig. 4 is I in the present invention
2the schematic diagram of a kind of embodiment of C bus buffer module;
Fig. 5 is the schematic diagram of a kind of embodiment of channel switch module in the present invention;
Fig. 6 is the schematic diagram of a kind of embodiment of digital DIP module in the present invention;
Fig. 7 is the schematic diagram expanding a kind of embodiment of output module in the present invention;
Fig. 8 is the schematic diagram of a kind of embodiment of storer in the present invention;
Fig. 9 is the structural representation from control unit of the chromacoder shown in Fig. 1;
Figure 10 is the schematic flow sheet that chromacoder of the present invention realizes signal conversion;
Figure 11 is the main control unit of the chromacoder shown in Fig. 1 module diagram when carrying out initialization;
Module diagram when Figure 12 is the main control unit setting address of the chromacoder shown in Fig. 1;
Module diagram when Figure 13 is the main control unit output Transistor-Transistor Logic level signal of the chromacoder shown in Fig. 1;
Figure 14 be the chromacoder shown in Fig. 1 from control unit setting address time module diagram;
Figure 15 be the chromacoder shown in Fig. 1 from control unit export Transistor-Transistor Logic level signal time module diagram;
Module diagram when Figure 16 is resetting from control unit of the chromacoder shown in Fig. 1;
Figure 17 is the structural representation of a kind of embodiment of Auto-Test System of the present invention;
Figure 18 is the structural representation of the another kind of embodiment of Auto-Test System of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in embodiment of the present invention, be clearly and completely described the technical scheme in embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of protection of the invention.
Refer to Fig. 1, Fig. 1 is the structural representation of the chromacoder of first embodiment of the invention.
Chromacoder 10 is connected with host computer, for from the control information of host computer receiving system, converts multiple Transistor-Transistor Logic level signal to and exports.In embodiment of the present invention, host computer is such as computing machine, for passing through the control information of usb communication agreement output system to chromacoder 10.Chromacoder 10 comprises main control unit 100, and main control unit 100 converts I by usb communication agreement to from the control information of host computer receiving system
2c communication protocol data form, and pass through I
2c bus outside transmission system control information and receive outside back information.Main control unit 100 exports multiple Transistor-Transistor Logic level signal according to system control information.Outside back information is as the status information from the passback of control unit.
I
2c(Inter-Integrated Circuit) bus is a kind of twin wire universal serial bus, for connection control device and peripherals thereof, it is a kind of bus standard that microelectronics Control on Communication field extensively adopts, it is a kind of special shape of synchronous communication, there is interface line few, control simple, the little and traffic rate advantages of higher of device package form.
In the present embodiment, chromacoder 10 also comprises at least one from control unit 200.Usb signal is by the I of main control unit 100
2each chip that C bus controls main control unit 100 sends the Transistor-Transistor Logic level signal of needs, can also share to I from control unit 200 by main control unit 100
2c bus allows from each chip of control unit 200 and sends Transistor-Transistor Logic level signal.I is passed through with main control unit 100 from control unit 200
2c bus is connected, and passes through I
2c communication protocol from the control information of main control unit 100 receiving system, and convert to multiple Transistor-Transistor Logic level signal respectively from from control unit 200 export.
When the Transistor-Transistor Logic level signal needed is less, main control unit 100 can be stopped and from the communication controlled between unit 200, the multiple Transistor-Transistor Logic level signals only utilizing main control unit 100 to export.When the Transistor-Transistor Logic level number of signals that main control unit 100 cannot be satisfied the demand, main control unit 100 can control multiplely to export multiple Transistor-Transistor Logic level signal from control unit 200, meets actual demand.Such as, be 7 from control unit 200, allly pass through I from control unit 200 with main control unit 100
2c bus parallel connection connects.
See also Fig. 2 to Fig. 8, Fig. 2 is the structural representation of the main control unit of the chromacoder shown in Fig. 1.In order to clear display, also show in figure from control unit 200.
As shown in Figure 2, main control unit 100 comprises High-speed I/O PIC module 101, I
2c bus buffer module 102, the digital DIP module 104, first of first passage switch module 103, first are expanded output module 105 and second and are exported expansion module 106.
High-speed I/O PIC(Input/Output, input and output) (Peripheral Interface Controller, adopt single-chip data line and the order line time-sharing multiplex of CISC structure, i.e. so-called variational OR structure) module 101 for receiving the usb signal of host computer transmission, and usb signal is converted to I
2c format order, and via I
2c internal bus transmission I
2c format order.In the present embodiment, main control unit 100 also comprises USB impact damper 107, USB impact damper 107 and is connected with host computer, for receiving the usb signal of host computer transmission, and usb signal is sent to High-speed I/O PIC module 101.Access USB impact damper 107, can ensure usb signal stable transfer.
I
2c bus buffer module 102 is via I
2c internal bus receives I
2c format order, and via I
2c external bus outwards sends I
2c format order to from control unit 200.I
2c bus buffer module 102 is via I
2c external bus receives the I returned from control unit 200
2c format information, and via I
2c internal bus sends back to High-speed I/O PIC module 101.I
2c bus buffer module 102 can at I
2c external bus and I
2buffer action is played, with stable I between C internal bus
2the stable transfer of C format order.
First passage switch module 103 is such as multichannel dispense switch, and it comprises input channel and multiple output channel, and input channel and High-speed I/O PIC module 101 pass through I
2c internal bus is connected, and according to pattern setting by I
2c format order is sent to multiple output channel respectively.
First digital DIP(Dual In-line Package, is also dual-in-line package technology) module 104 passes through I with High-speed I/O PIC module 101
2c internal bus is connected, for set main control unit 100 or from the address of control unit 200, set each functional module reset, enable, forbid and the duty such as write-protect.Specifically, in embodiment of the present invention, the first digital DIP module 104 is for according to I
2c format order setting first passage switch module 103, first expands output module 105 and the second expansion duty of output module 106 and address of main control unit 100.Due at I
2in C bus rule, main control unit 100 needs to set different addresses, to prevent from clashing with from control unit 200.So the first digital DIP module 104 needs the address setting separately main control unit 100, the address of main control unit 100 can be set to 0.0.0 here.
1st output channel CH1(channel of the first expansion output module 105 and first passage switch module 103, passage) be connected, for according to I
2c format order exports one group of multidigit Transistor-Transistor Logic level signal.In the present embodiment, the first expansion output module 105 exports one group of 16 Transistor-Transistor Logic level signal.
Second expansion output module 106 is connected with the 1st output channel CH1 of first passage switch module 103, for according to I
2c format order exports other one group of multidigit Transistor-Transistor Logic level signal.In the present embodiment, the second expansion output module 106 exports one group of 16 Transistor-Transistor Logic level signal.
By the first expansion output module 105 and the second expansion output module 106, main control unit 100 can export 32 Transistor-Transistor Logic level signals.
Main control unit 100 also comprises the 3rd expansion output module 108.3rd expansion output module 108 is connected with the 1st output channel CH1 of first passage switch module 103, for according to I
2c format order exports 16 Transistor-Transistor Logic level signals.Wherein, have 8 Transistor-Transistor Logic level signals for specifying, other 8 then represent the address of main control unit 100.In the present embodiment, main control unit 100 also comprises a LED(Light Emitting Diode, light emitting diode) nixie display 109, one LED nixie display 109 and the 3rd is expanded output module 108 and is connected, for receiving 8 Transistor-Transistor Logic level signals of the address representing main control unit 100, then the corresponding LED of a LED nixie display 109 lights, to show the address of main control unit 100.One LED nixie display 109 can select 7 segment numeral LED pipe.
Main control unit 100 also comprises storer 110.Storer 110 is connected with the 2nd output channel CH2 of first passage switch module 103, and sets duty, storer 110 and I by the first digital DIP module 104
2c internal bus is connected, for storing I
2the data of C internal bus write.In the present embodiment, storer 110 is EEPROM(Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Read Only Memory).
Main control unit 100 also comprises the 4th expansion output module 111.4th expansion output module 111 is connected with the 3rd output channel CH3 of first passage switch module 103, for according to I
2c format order exports 16 Transistor-Transistor Logic level signals.16 Transistor-Transistor Logic level signals herein not as the output of main control unit 100, only main control unit 100 with from control unit 200 communicate time, activate from control unit 200 and detection from the state controlling unit 200.
In the present embodiment, the first digital DIP module 104 is also for setting the duty of described 3rd expansion output module 108, storer 110 and the 4th expansion output module 111.High-speed I/O PIC module 101 is also for sending the first digital DIP module 104 and the write protect signal of storer 110, the ready signal of main control unit 10 and reset signal.
Because all the other output channels of first passage switch module 103 do not use, not shown in Fig. 2.
In embodiments of the present invention, the High-speed I/O PIC module 101 of the main control unit 100 of chromacoder 10 is selected from PIC18F1XK50/PIC18LF1XK50 chip as shown in Figure 3, and 18,19 pins of this chip are for receiving usb signal.
I
2c bus buffer module 102 is selected from IES5502 chip as shown in Figure 4, and its pin 5 and pin 6 meet I
2c internal bus, pin 2 and pin 7 meet I
2c external bus.
First passage switch module 103 is selected from IES5507 chip as shown in Figure 5, and its pin 1, pin 2 and pin 13 are for accepting the address setting of the first digital DIP module 104.Pin 14 and pin 15 meet I
2c internal bus.
First digital DIP module 104 is selected from SW00347 chip as shown in Figure 6, and its pin 1 is connected I with pin 2
2c internal bus, this chip pin 9, pin 10 and pin 11 are in order to set the address of main control unit 100, and the address setting main control unit 100 to the mode on ground by pin 9, pin 10 and pin 11 being connect pull down resistor is 0.0.0.
First expansion output module 105, second exports expansion module 106, the 3rd expansion output module 108 and the 4th expansion output module 111 and is all selected from MCP23017 chip as shown in Figure 7, and the pin 15 of this chip, pin 16, pin 17 are in order to set address.In the present embodiment, pin 15, pin 16, pin 17 set first expansion output module 105 address as 1.0.0, second output expansion module 106 address as 0.1.0 to high level or connection pull down resistor to low level mode to connect pull-up resistor, and the 3rd expansion output module 108 address is 1.1.0.
Storer 110 is selected from 24xx256 chip as shown in Figure 8, and the pin 5 of this chip is connected I with pin 6
2c internal bus.Pin 7 is in order to write data.
Refer to Fig. 9, Fig. 9 is the structural representation from control unit of the chromacoder shown in Fig. 1.In order to clear display, in figure, also show main control unit 100.
The digital DIP module 202 of second channel switch module 201, second, the 5th expansion output module 203 and the 6th expansion output module 204 is comprised from control unit 200.
Second channel switch module 201 comprises input channel and multiple output channel.The I of main control unit 100 in input channel and Fig. 2
2c bus buffer module 102 passes through I
2c external bus connects, and according to pattern setting by I
2c format order is sent to the 5th output channel CH5.Only employ in multiple output channel due to second channel switch module 201, therefore all the other output channels are all not shown.
Second digital DIP module 202 and I
2c bus buffer module 102 passes through I
2c external bus is connected, for according to I
2the initial address of C format order setting second channel switch module 201.Here, initial address can be set as 1.1.1, and initial address can be reset by main control unit 100.
5th expansion output module 203 is connected with the 5th output channel CH5 of second channel switch module 201, for according to I
2c format order exports one group of 16 Transistor-Transistor Logic level signal.
6th expansion output module 204 is connected with the 5th output channel CH5 of second channel switch module 201, for according to I
2c format order exports one group of 16 Transistor-Transistor Logic level signal.
The 7th expansion output module 205 is also comprised from control unit 200.7th expansion output module 205 is connected with the 5th output channel CH5 of second switch channel module 201, for according to I
2c format order exports 16 Transistor-Transistor Logic level signals.Wherein, the address of 8 bit representation main control units 100 is had.In the present embodiment, the 2nd LED nixie display 206 and DB9 output port 207 is also comprised from control unit 200.2nd LED nixie display 206 and the 7th is expanded output module 205 and is connected, for receiving 8 the Transistor-Transistor Logic level signals of the 7th representative that export of expansion output module 205 from the address of control unit 200, then corresponding LED is lit, to show the address from control unit 200.DB9 output port 207 and the 7th is expanded output module 205 and is connected, for receiving all the other 8 Transistor-Transistor Logic level signals that the 7th expansion output module 205 exports.2nd LED nixie display 206 can select 7 segment numeral LED pipe.
8-1 data selector 208 and 3-8 code translator 209 is also comprised from control unit 200.8-1 data selector 208 is connected with the second digital DIP module 202, for receiving 8 Transistor-Transistor Logic level signals that the 4th expansion output module 111 exports, and the Transistor-Transistor Logic level signal selected by exporting.Second digital DIP module 202 exports decoded signal according to selected Transistor-Transistor Logic level signal.3-8 code translator 209 is connected with 8-1 data selector 208 and the second digital DIP module 202, for receiving the Transistor-Transistor Logic level signal and decoded signal that 8-1 data selector 208 exports, after the second digital DIP module 202 activates second channel switch module 201, return I to main control unit 100
2c format information, to represent the state from control unit 200.In the present embodiment, I
2c format information is octonary signal.
In the present embodiment, the second digital DIP module 202 is also for setting the 7th expansion duty of output module 205 and the initial address of 8-1 data selector 208.
No matter the main control unit 100 that present embodiment provides exports separately Transistor-Transistor Logic level signal, or export more Transistor-Transistor Logic level signal together with from control unit 200, all do not need to install and drive, can directly use, also very flexible with the collocation of peripheral circuit, send out control command corresponding and can obtain the TTL signal level of any needs by host computer, thus can be applicable to control complicated situation.
Concrete, second channel switch module 201 is selected from IES5507 chip as shown in Figure 5, and its pin 1, pin 2 and pin 13 are for accepting the address setting of the second digital DIP module 202.Pin 14 and pin 15 meet I
2c internal bus.In the present embodiment, the address of second channel switch module 201 is set to 1.1.1, and this address can be reset by main control unit 100 as required.
Second digital DIP module 202 is selected from SW00347 chip as shown in Figure 6, and its pin 1 is connected I with pin 2
2c internal bus, this chip pin 9, pin 10 and pin 11 are in order to the address of setting from control unit 200.Be different from the address of main control unit 100 from the address setting of control unit 200, and when being multiple from control unit 200, multiple address from control unit 200 is different.
5th expansion output module 203, the 6th expansion output module 204 and the 7th expansion output module 205 are all selected from MCP23017 chip as shown in Figure 7, and the pin 15 of this chip, pin 16, pin 17 are in order to set address.In the present embodiment, pin 15, pin 16, pin 17 set first expansion output module 105 address as 1.0.0, second output expansion module 106 address as 0.1.0 to high level or connection pull down resistor to low level mode to connect pull-up resistor, and the 3rd expansion output module 108 address is 1.1.0.
8-1 data selector 208 is selected from 74151 chips, and the pin 11 of this chip, pin 12 and pin 13 are in order to accept the address setting of the second digital DIP module 202.It is shown in Figure 2 that pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7 and pin 9 receive the 4th expansion output module 111() 8 Transistor-Transistor Logic level signals exporting, Transistor-Transistor Logic level signal selected by pin 14 exports, for the signal activation sent according to main control unit 100 or close and export decoded signal from the digital DIP module 202 of control unit 200, second according to selected Transistor-Transistor Logic level signal and control to open or close second channel switch module 201.In the present embodiment, this decoded signal is triad signal.
3-8 code translator 209 is selected from 74138 chips, and the pin 6 of this chip receives the Transistor-Transistor Logic level signal selected by 8-1 data selector 208, and pin 1, pin 2 and pin 3 receive the decoded signal that the second digital DIP module 202 exports, and decoding exports I
2c format information, and return I to main control unit 100
2c form status information, to represent the state from control unit 200.Concrete, first 3-8 code translator 209 returns I to the second digital DIP module 202
2c form status information, the second digital DIP module 202 passes through I again
2c bus buffer module 102 returns I to main control unit 100
2c form status information.In the present embodiment, I
2c form status information is eight signals.
Refer to Figure 10, Figure 10 is the schematic flow sheet that chromacoder of the present invention realizes signal conversion.Chromacoder realizes flow process that signal changes and is described into example based on the chromacoder 10 of the first embodiment, and its flow process realizing signal conversion comprises the following steps:
Step S101: High-speed I/O PIC module 101 pairs USB impact damper 107 carries out initialization.
Refer to Figure 11, Figure 11 is the main control unit of the chromacoder shown in Fig. 1 module diagram when carrying out initialization.Before reception usb signal, High-speed I/O PIC module 101 pairs of USB impact dampers 107 carry out initialization, to remove the data that USB impact damper 107 stores before this.After initialization, main control unit 100 is in standby condition.And High-speed I/O PIC module 101 outwards can send ready signal.Ready signal can be exported separately by High-speed I/O PIC module 101, also can pass through I
2c bus buffer module 102 is loaded into I
2c bus exports.
Step S102: High-speed I/O PIC module 101 receives the system control information of host computer, and sends I
2c format order, the first digital DIP module 104 is according to I
2the address of C format order setting main control unit 100.
Refer to Figure 12, module diagram when Figure 12 is the main control unit setting address of the chromacoder shown in Fig. 1.High-speed I/O PIC module 101 sends I
2c format order, the first digital DIP module 104 is according to I
2the address of C format order setting main control unit 100.First digital DIP module 104 has address setting pin, namely this address represents the address of main control unit 100, such as, is set as 0.0.0.Further, the first digital DIP module 104 is also according to I
2the address of C format order setting storer 110 and first passage switch module 103.I
2c format order also passes through I
2c bus buffer module 102 is loaded into I
2c bus exports, during to connect at main control unit 100 from control unit 200, from control unit 200 according to I
2c format order setting address.
Step S103: the first expansion output module 105 and the second expansion output module 106 are respectively according to I
2c format order exports one group of 16 Transistor-Transistor Logic level signal.
Refer to Figure 13, module diagram when Figure 13 is the main control unit output Transistor-Transistor Logic level signal of the chromacoder shown in Fig. 1.First switching channels module 103 is by I
2c format order is sent to the first expansion output module 105 respectively by an output channel and the second expansion output module 106, first expands output module 105 according to I
2c format order exports one group of 16 Transistor-Transistor Logic level signal, and the second expansion output module 106 is according to I
2c format order exports another group 16 Transistor-Transistor Logic level signals.Meanwhile, the first switching channels module 103 also passes through other passages by I
2c format order is sent to storer 110, to store the data of write.
When required signal is more, when needing utilization to export Transistor-Transistor Logic level signal from control unit 200, the mode that main control unit 100 controls to realize from control unit 200 signal conversion is further comprising the steps of:
Step S104: when main control unit 100 exports multiple Transistor-Transistor Logic level signal, activates second channel switch module 201 and detects the state from control unit 200.
Referring again to Figure 13, the first digital DIP module 104, after High-speed I/O PIC module 101 carries out initialization, also sets the address of the 4th expansion output module 111.First switching channels module 103 is by I
2c format order sends to the 4th expansion output module 111.When first expansion output module 105 and the second expansion output module 106 export Transistor-Transistor Logic level signal, 4th expansion output module 111 also exports 16 Transistor-Transistor Logic level signals, wherein 8 Transistor-Transistor Logic level signal activations are from the second channel switch module 201 controlling unit 200, and other 8 Transistor-Transistor Logic level input are from the state of control unit 200.
Step S105: activate second channel switch module 201 and set the address of second channel switch module 201.
Refer to Figure 14, Figure 14 be the chromacoder shown in Fig. 1 from control unit setting address time module diagram.Second channel switch module 201 is started working by the 4th expansion 8 Transistor-Transistor Logic level signal activations exporting of output module 111.And receive 8 Transistor-Transistor Logic level signals for activating second channel switch module 201 from the 8-1 data selector 208 of control unit 200, and select output one Transistor-Transistor Logic level signal, second digital DIP module 202 controls to open the digital DIP module 202 of second channel switch module 201, second according to selected Transistor-Transistor Logic level signal and passes through I
2c external bus receives I
2c format order, and according to I
2the setting of C format order is from the address of control unit 200, second channel switch module 201,8-1 data selector 208 and 3-8 code translator 209.The address of second channel switch module 201 and 8-1 data selector 208 is all set to 1.1.1.
Step S 106: export 32 Transistor-Transistor Logic level signals from control unit 200, and return I to main control unit 100
2c form status information.
Refer to Figure 15, Figure 15 be the chromacoder shown in Fig. 1 from control unit export Transistor-Transistor Logic level signal time module diagram.Second channel switch module 201 is by I
2c format order is sent to the 5th expansion output module 203 and the 6th expansion output module the 204, five expansion output module 203 and the 6th expansion output module 204 according to I
2c format order exports one group of 16 Transistor-Transistor Logic level signal respectively.And 8-1 data selector 208 receives 8 the Transistor-Transistor Logic level signals being used for detected state, and select output one Transistor-Transistor Logic level signal, second digital DIP module 202 exports decoded signal according to selected Transistor-Transistor Logic level signal, 3-8 code translator 209 receives this decoded signal and Transistor-Transistor Logic level signal, after decoding, return I to main control unit 100
2c form status information, represents the state from control unit 200.Concrete, first 3-8 code translator 209 returns I to the second digital DIP module 202
2c form status information, the second digital DIP module 202 passes through I again
2c bus buffer module returns I to main control unit
2c form status information.In the present embodiment, decoded signal is 3 binary signals, I
2c format information is eight signals.
Step S107: after exporting Transistor-Transistor Logic level signal from control unit 200, reset to from control unit 200.
Refer to Figure 16, module diagram when Figure 16 is resetting from control unit of the chromacoder shown in Fig. 1.Second digital DIP module 202 passes through I
2c external bus receives I
2c format order, according to I
2c format order resets to second channel switch module 201, the 5th expansion output module 203 and the 6th expansion output module 204, namely resets second channel switch module the 201, the 5th and expands output module 203 and the 6th expansion output module 204.
Should be understood that and be described from control unit 200 to control one above, when the chromacoder 10 of embodiment of the present invention comprise multiple parallel connection from control unit 200 time, to each from controlling the control mode of unit 200 as mentioned before, do not repeat them here.
Specifically, for 7 in parallel, from control unit, compared with prior art, the chromacoder of embodiment of the present invention has 32 TTL master ports, and 7 groups 32 from port, can be obtained the TTL signal level of any needs by the control of computing machine.
In sum, embodiment of the present invention provides a kind of device that effectively can be obtained the Transistor-Transistor Logic level signal of demand by conputer controlled, wherein, no matter main control unit 100 exports separately Transistor-Transistor Logic level signal, or export more Transistor-Transistor Logic level signal together with from control unit 200, all do not need to install and drive, can directly use, also very flexible with the collocation of peripheral circuit, send out control command corresponding and can obtain the TTL signal level of any needs by host computer, thus can be applicable to control complicated situation.
The chromacoder of embodiment of the present invention may be used in various Auto-Test System, the Transistor-Transistor Logic level signal that the chromacoder of embodiment of the present invention provides by the drives of back segment or can amplify the action that the various device of further control realizes robotization, to realize automatic control, reduce costs.
Described in brought forward, invention further provides a kind of Auto-Test System, it comprises host computer, the chromacoder 10 of rear class application circuit and the first embodiment.In most applications, host computer is computing machine.Chromacoder 10 is connected with host computer, for from the control information of host computer receiving system, and converts multiple Transistor-Transistor Logic level signal to and exports.Rear class application circuit comprises signal processing circuit and to be measured, signal processing circuit is connected with chromacoder 10, receives Transistor-Transistor Logic level signal and export required TTL control signal automatically to test to be measured after carrying out signal transacting from chromacoder 10.
Such as, refer to Figure 17, Figure 17 is the structural representation of a kind of embodiment of Auto-Test System of the present invention.In the present embodiment, automatic control system is that antenna beats test macro automatically.Chromacoder 10 is connected with host computer 301.
Signal processing circuit comprises the driving circuit 302, relay 303, programmable logic device (PLD) 304, solenoid valve 305 and the rotary cylinder 306 that connect successively.Driving circuit 302 is connected with chromacoder 10, receives Transistor-Transistor Logic level signal from chromacoder 10.
In present embodiment, to be measured is antenna 307.Host computer 301 sends system control information to chromacoder 10, and chromacoder 10 exports required Transistor-Transistor Logic level signal.Because the magnitude of voltage of Transistor-Transistor Logic level signal is lower, therefore Transistor-Transistor Logic level signal is driven into higher magnitude of voltage by driving circuit 302, such as 24V, the control signal needed for output.This control signal is pilot relay 303 as required, and after relay 303 conducting, programmable logic device (PLD) 304 brings into operation the program of inner pre-edit, and solenoid valve 305 drives rotary cylinder 306 action under program, rotary cylinder 306 and then beat antenna 307.In the present embodiment, relay 303 is 24V DC relay, and Programmadle logic device 304 is PLC(Programmable Logic Controller), rotary cylinder 306 is gas rotary cylinder.
Rotary cylinder 306 beats automatically, effectively can reduce the running time of tester, reduce costs.
It is the structural representation of the another kind of embodiment of Auto-Test System of the present invention referring again to Figure 18, Figure 18.In the present embodiment, automatic control system is radio-frequency (RF) switch automatic control system.Chromacoder 10 is connected with host computer 401.
Signal processing circuit comprises driving circuit 402, radio-frequency (RF) switch 403 and tester 404.To be measured 305 there is multiport.Radio-frequency (RF) switch 403 also has multiport.Wherein, host computer 401, chromacoder 10, driving circuit 402 are connected successively with radio-frequency (RF) switch 403.Radio-frequency (RF) switch 403 is corresponding with the port of to be measured 405 to be connected, and radio-frequency (RF) switch 403 goes back connecting test instrument 404.
Computing machine sends system control information to chromacoder 10, and chromacoder 10 exports required Transistor-Transistor Logic level signal.Transistor-Transistor Logic level signal driven circuit 402 is driven into 24V direct voltage output control signal, and then controls radio-frequency (RF) switch 403.Radio-frequency (RF) switch 403 controls the port of tester 404 and the corresponding port conducting of to be measured 405 further, to carry out relevant parameter test.In this manner, multiple ports of to be measured 405 can require test according to different test indexs by tested instrument 404, obtain the multiple parameters of to be measured 405.In the present embodiment, tester 404 is network analyzer.
Export Transistor-Transistor Logic level signal by chromacoder 10, automatically control radio-frequency (RF) switch and carry out corresponding test, effectively can reduce the running time of tester, reduce costs.
By the way, the chromacoder of embodiment of the present invention converts I by usb communication agreement to from the control information of host computer receiving system
2c communication protocol data form, and export multiple Transistor-Transistor Logic level signal according to system control information, and do not need driving is installed, be applicable to control complicated situation.When chromacoder of the present invention is applied to Auto-Test System, can Automated condtrol be realized, reduce costs.
The foregoing is only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize instructions of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (19)
1. a chromacoder, for from the control information of host computer receiving system, convert multiple Transistor-Transistor Logic level signal to and export, it is characterized in that, described chromacoder comprises:
Main control unit, described main control unit receives described system control information by usb communication agreement from described host computer and converts I to
2c communication protocol data form, and pass through I
2c bus is outwards transmitted described system control information and is received outside back information;
Wherein, main control unit also exports multiple Transistor-Transistor Logic level signal according to described system control information;
Described chromacoder also comprise at least one from control unit, described from control unit pass through I
2c communication protocol receives described system control information from described main control unit, and convert to multiple Transistor-Transistor Logic level signal respectively from described from control unit export;
Described main control unit comprises:
High-speed I/O PIC module, for receiving the usb signal of described host computer transmission, and is converted to I by described usb signal
2c format order, and via I
2c internal bus transmits described I
2c format order;
I
2c bus buffer module, described I
2c bus buffer module is via I
2c internal bus receives I
2c format order, and via I
2c external bus outwards sends I
2c format order is to described from control unit; Described I
2c bus buffer module is via I
2c external bus receives the described I from the passback of control unit
2c format information, and via I
2c internal bus sends back to described High-speed I/O PIC module.
2. chromacoder according to claim 1, is characterized in that, described main control unit comprises:
First passage switch module, it comprises input channel and multiple output channel, and described input channel and described High-speed I/O PIC module pass through I
2c internal bus is connected, and according to pattern setting by I
2c format order is sent to multiple described output channel respectively;
First digital DIP module, with described High-speed I/O PIC module by described I
2c internal bus is connected, for according to described I
2c format order sets described first passage switch module, described first expansion output module and the described second expansion duty of output module and the address of described main control unit;
First expansion output module, is connected with the 1st output channel of described first passage switch module, for according to described I
2c format order exports one group of multidigit Transistor-Transistor Logic level signal;
Second expansion output module, is connected with the 1st output channel of described first passage switch module, for according to described I
2c format order exports other one group of multidigit Transistor-Transistor Logic level signal.
3. chromacoder according to claim 1, is characterized in that, described main control unit also comprises the 3rd expansion output module, is connected, for according to described I with the 1st output channel of described first passage switch module
2c format order exports 16 Transistor-Transistor Logic level signals.
4. chromacoder according to claim 3, it is characterized in that, described main control unit also comprises a LED nixie display, expand output module be connected with the described 3rd, for receiving 8 Transistor-Transistor Logic level signals that described 3rd expansion output module exports, to show the address of described main control unit.
5. chromacoder according to claim 3, is characterized in that, described first digital DIP module is also for setting the duty of described 3rd expansion output module.
6. chromacoder according to claim 2, it is characterized in that, described main control unit comprises storer, is connected with the 2nd output channel of described first passage switch module, and set duty, described storer and described I by described first digital DIP module
2c internal bus is connected, for storing described I
2the data of C internal bus write.
7. chromacoder according to claim 6, is characterized in that, described main control unit also comprises the 4th expansion output module, is connected, for according to described I with the 3rd output channel of described first passage switch module
2c format order exports 16 Transistor-Transistor Logic level signals.
8. chromacoder according to claim 7, is characterized in that, described first digital DIP module is also for setting the duty of described storer and described 4th expansion output module.
9. chromacoder according to claim 2, it is characterized in that, described main control unit also comprises USB impact damper, is connected with described host computer, for receiving the usb signal of described host computer transmission, and described usb signal is sent to described High-speed I/O PIC module.
10. the chromacoder according to any one of claim 1 to 9, is characterized in that, described from control unit comprise:
Second channel switch module, it comprises input channel and multiple output channel, described input channel and described I
2c bus buffer module is by described I
2c external bus connects, and according to pattern setting by I
2c format order is sent to the 5th output channel;
Second digital DIP module, with described I
2c bus buffer module is by described I
2c external bus is connected, for according to described I
2c format order sets the initial address of described second channel switch module;
5th expansion output module, is connected with the 5th output channel of described second channel switch module, for according to described I
2c format order exports one group of 16 Transistor-Transistor Logic level signal;
6th expansion output module, is connected with the 5th output channel of described second channel switch module, for according to described I
2c format order exports other one group of 16 Transistor-Transistor Logic level signal.
11. chromacoders according to claim 10, is characterized in that, also comprise the 7th expansion output module, be connected, for according to described I with the 5th output channel of described second channel switch module described at least one from control unit
2c format order exports 16 Transistor-Transistor Logic level signals.
12. chromacoders according to claim 11, it is characterized in that, the 2nd LED nixie display is also comprised from control unit described at least one, expand output module be connected with the described 7th, for receiving 8 Transistor-Transistor Logic level signals that described 7th expansion output module exports, to show the address of described main control unit.
13. chromacoders according to claim 12, it is characterized in that, also comprising DB9 output port from control unit described at least one, expand output module be connected with the described 7th, expanding for receiving the described 7th all the other 8 Transistor-Transistor Logic level signals that output module exports.
14. chromacoders according to claim 11, is characterized in that, described second digital DIP module is also for setting the duty of described 7th expansion output module.
15. chromacoders according to claim 10, is characterized in that, describedly also comprise from control unit described at least one:
8-1 data selector, be connected with described second digital DIP module, for receiving 8 Transistor-Transistor Logic level signals that described 4th expansion output module exports, and the Transistor-Transistor Logic level signal selected by exporting, described second digital DIP module exports decoded signal according to selected Transistor-Transistor Logic level signal;
3-8 code translator, is connected with described 8-1 data selector and described second digital DIP module, for receiving the Transistor-Transistor Logic level signal and described decoded signal that described 8-1 data selector exports, and returns I
2c format information, to represent the described state from control unit, wherein, described I
2c format information is eight signals.
16. chromacoders according to claim 15, is characterized in that, described second digital DIP module is also for setting the initial address of described 8-1 data selector.
17. 1 kinds of Auto-Test Systems, is characterized in that, comprising:
Host computer;
Chromacoder according to any one of claim 1 to 16, described chromacoder is connected with described host computer, for from the control information of described host computer receiving system, and converts multiple Transistor-Transistor Logic level signal to and exports;
Rear class application circuit, it comprises signal processing circuit and to be measured, described signal processing circuit is connected with described chromacoder, receives described Transistor-Transistor Logic level signal and export required control signal after carrying out signal transacting automatically to test described to be measured from described chromacoder.
18. Auto-Test Systems according to claim 17, it is characterized in that, described Auto-Test System is that antenna beats test macro automatically, described signal processing circuit comprises driving circuit, relay, programmable logic device (PLD), solenoid valve and rotary cylinder, described to be measured is antenna, wherein, described host computer, described chromacoder, described driving circuit, described relay, described programmable logic device (PLD), described solenoid valve and described rotary cylinder connect successively, and described rotary cylinder is used for beaing described antenna.
19. Auto-Test Systems according to claim 17, it is characterized in that, described Auto-Test System is radio-frequency (RF) switch automatic control system, described signal processing circuit comprises driving circuit, radio-frequency (RF) switch and tester, described to be measured has multiport, wherein, described host computer, described chromacoder, described driving circuit, described radio-frequency (RF) switch and described tester connect successively, described radio-frequency (RF) switch controls the corresponding port conducting by the port of described tester and described to be measured, to carry out parameter testing by described control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261778.9A CN102866683B (en) | 2012-07-26 | 2012-07-26 | Signal conversion device and automatic testing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261778.9A CN102866683B (en) | 2012-07-26 | 2012-07-26 | Signal conversion device and automatic testing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102866683A CN102866683A (en) | 2013-01-09 |
| CN102866683B true CN102866683B (en) | 2014-12-17 |
Family
ID=47445606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210261778.9A Active CN102866683B (en) | 2012-07-26 | 2012-07-26 | Signal conversion device and automatic testing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102866683B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678066A (en) * | 2013-12-18 | 2014-03-26 | 北京航天测控技术有限公司 | Method and device for testing test signal set |
| CN104615039B (en) * | 2014-09-22 | 2017-09-26 | 中国电子科技集团公司第四十一研究所 | A kind of expansible multi-channel rf switching device of USB interface control |
| CN104460375B (en) * | 2014-11-26 | 2017-02-22 | 北京无线电测量研究所 | Multi-signal generation device and method used for combined grade product debugging |
| CN105739435B (en) * | 2016-05-10 | 2018-07-20 | 苏州新代数控设备有限公司 | Numerical control device |
| CN108494889B (en) * | 2018-02-07 | 2021-05-28 | 广州视源电子科技股份有限公司 | Communication circuit based on I2C bus and debugging method |
| CN108362989B (en) * | 2018-02-28 | 2020-11-17 | 环胜电子(深圳)有限公司 | Voltage stabilizer test system |
| CN109995397A (en) * | 2018-12-19 | 2019-07-09 | 安徽华东光电技术研究所有限公司 | 64 road Ka wave band array switch |
| CN114355796A (en) * | 2021-11-22 | 2022-04-15 | 杭州程天科技发展有限公司 | CAN communication interface extension method and extension circuit |
| CN114326370B (en) * | 2021-12-31 | 2024-04-30 | 节卡机器人股份有限公司 | Extended output circuit system and control method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101344874A (en) * | 2007-07-11 | 2009-01-14 | 深圳创维－Rgb电子有限公司 | Method and device for controlling I2C device |
| CN201919055U (en) * | 2010-12-28 | 2011-08-03 | 惠州Tcl移动通信有限公司 | Mobile terminal test box based on inter-integrated circuit (I2C) bus |
-
2012
- 2012-07-26 CN CN201210261778.9A patent/CN102866683B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101344874A (en) * | 2007-07-11 | 2009-01-14 | 深圳创维－Rgb电子有限公司 | Method and device for controlling I2C device |
| CN201919055U (en) * | 2010-12-28 | 2011-08-03 | 惠州Tcl移动通信有限公司 | Mobile terminal test box based on inter-integrated circuit (I2C) bus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102866683A (en) | 2013-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102866683B (en) | Signal conversion device and automatic testing system | |
| CN100568211C (en) | Realize method and the device of a plurality of I2C of visit with programming device from device | |
| CN102045608B (en) | Network device for optical communication and method thereof for automatically configuring exchange interface | |
| CN101256544B (en) | Method, apparatus and system for expansion of inside integrated circuit bus | |
| CN113608936B (en) | Multi-path interface test system and method | |
| CN105681145A (en) | FPGA-based FlexRay communication module | |
| CN202421950U (en) | External expanding unit for PCI (Peripheral Component Interconnect) bus board cards | |
| CN110968352B (en) | Reset system and server system of PCIE equipment | |
| CN100478935C (en) | PCIE channel expansion device, system and its collocation method | |
| CN102609376A (en) | Serial bus memory, serial bus transmission system and method | |
| CN106598886B (en) | I/O bus shared memory system | |
| CN114564428A (en) | Airborne electronic equipment I/O port expansion system | |
| CN102081586A (en) | Multiple I2C (Inter-IC) slot circuit system and method for transmitting I2C signal | |
| CN103488600A (en) | Universal auxiliary machine synchronous serial interface circuit | |
| CN109407574B (en) | Multi-bus selectable output control device and method thereof | |
| CN110781130A (en) | System on chip | |
| CN106155954A (en) | The system and method that a kind of module identification and COM1 distribute automatically | |
| CN102693196A (en) | Memory controller address and data pin multiplexing | |
| CN113626359A (en) | Signal switching device and method for flash memory chip of server | |
| CN100395744C (en) | Method and system for realizing central control of central control unit to single board | |
| CN103488601B (en) | A kind of clock delay, data access method, system and equipment | |
| CN112597732B (en) | Method and system for changing IIC device address through software configuration | |
| CN201698420U (en) | Small-sized pluggable optical receiving-sending module control device based on I2C bus | |
| CN201378316Y (en) | Universal input/output interface extension circuit and mobile terminal with same | |
| CN103218334A (en) | Computer peripheral cascade device based on USB (Universal Serial Bus) and RS485 bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180731 Address after: 233400 Huaiyuan County Economic Development Zone, Bengbu, Anhui Patentee after: Anhui Dafu Electromechanical Technology Co., Ltd. Address before: 215000 33 Torch Road, hi tech Zone, Suzhou, Jiangsu Patentee before: Suzhou Tatfook Communication Technology Co., Ltd. |