CN102856206B - A kind of semiconductor structure and manufacture method thereof - Google Patents
A kind of semiconductor structure and manufacture method thereof Download PDFInfo
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- CN102856206B CN102856206B CN201110182573.7A CN201110182573A CN102856206B CN 102856206 B CN102856206 B CN 102856206B CN 201110182573 A CN201110182573 A CN 201110182573A CN 102856206 B CN102856206 B CN 102856206B
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Abstract
The invention provides a kind of semiconductor structure and manufacture method thereof, the method comprises the following steps: substrate is provided, on described substrate, forms gate stack; On described substrate, form source/drain region and source/leakage epitaxial region, described source/leakage epitaxial region is connected with source/drain region, and its length is greater than the length of described source/drain region, and described length is the distance being parallel in the direction of channel length; Form the interlayer dielectric layer that covers described gate stack, described source/drain region and described source/leakage epitaxial region; On described source/leakage epitaxial region, form contact plug. Correspondingly, the present invention also provides a kind of semiconductor structure. The present invention is by increase source/leakage epitaxial region, and contact plug is placed on source/leakage epitaxial region, effectively reduced source/drain region area, and then reduced the area of whole semiconductor devices.
Description
Technical field
The manufacture field that the present invention relates to semiconductor devices, relates in particular to a kind of semiconductor devices and manufacture thereofMethod.
Background technology
Along with the development of semiconductor device processing technology, there is more high-performance and more powerful integrated circuitRequire larger component density, and between all parts, element or the size of each element self, largeLittle and space also needs further to dwindle, the therefore requirement to technology controlling and process in fabrication of semiconductor deviceHigher.
In traditional semiconductor technology, owing to being subject to the restriction of contact hole and drive current, so halfThe length of conductor device and width have certain restriction, are not suitable for too much reducing. In the present invention length andWidth is defined as: length is to be parallel to the namely distance in the direction of channel length of grid length, wideDegree is for being parallel to the namely distance in the direction of channel width of grid width. As everyone knows, source/drain regionWidth is relevant with the size of drive current, and width is larger, and drive current is larger. Conventionally, this width bePre-set as required when designing integrated circuit, can not arbitrarily change. On the other hand, source/drain regionLength relevant with the size of contact plug, its length must be longer than the length of contact plug, ensureing in source/On drain region, can form contact plug, so that source-drain electrode is drawn. In view of the restriction of length, width two aspects,In semiconductor structure, the area of source/drain region is difficult to reduce.
Below in conjunction with accompanying drawing, the semiconductor structure in traditional handicraft is described.
First with reference to figure 1, Fig. 1 is schematic diagram, is intended to clearly embody the structure pattern of metal-oxide-semiconductor, thereforeInterlayer dielectric layer is not shown in figure, can be used as sectional view reference. In figure, 110 is source/drain region, and 320 for connecingTouch plug, 230 be grid, and 400 is the metal wire when doing electrode and drawing. W is channel width, also can claimFor grid width; L is channel length, also can be described as grid long.
Secondly referring to figs. 2 and 3, Fig. 2 is the top view of conventional semiconductor structure, Fig. 3 is half shown in Fig. 2Conductor structure is along the cross-sectional view of A-A ' direction.
As shown in Figure 2,230 is grid, and 240 is side wall, and 320 is contact plug, and 300 is interlayer dielectric layer.Although from top view, cannot directly see the size of source/drain region, according to traditional etching technics, source/The length in drain region must be greater than the length of contact-making surface between contact plug 320. As shown in Figure 3, contact plug320 are positioned at gate stack both sides, and run through interlayer dielectric layer 300, are positioned on source/drain region 110. Thus canSee, contact plug 320 and source/drain region between the length of contact-making surface be less than the length of source/drain region.
As mentioned above, for the area that reduces semiconductor structure is to increase the integrated level of whole device, expectReduce length or the width of source/drain region. But the width that reduces source/drain region can directly cause semiconductor to driveStreaming current reduces, and semiconducting behavior declines. According to conventional semiconductor processing, because needs are on source/drain regionForm contact plug, therefore the design of source/drain region length is subject to the restriction of contact plug length. This two aspectRestriction has caused the area of source/drain region to be difficult to reduce, and correspondingly, semiconductor structure is difficult to reduce, semiconductorDevice integrated level is difficult to improve.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor devices and manufacture method thereof, for effectively reducing halfThe area of conductor structure, increases the integrated level of whole semiconductor devices.
According to an aspect of the present invention, provide a kind of manufacture method of semiconductor structure, the method comprisesFollowing steps:
(a) provide substrate, on described substrate, form gate stack;
(b) on described substrate, form source/drain region and source/leakage epitaxial region, described source/leakage epitaxial region with described inSource/drain region (110) is connected, and its length is greater than the length of described source/drain region;
(c) form interlayer Jie who covers described gate stack, described source/drain region and described source/leakage epitaxial regionMatter layer;
(d) on described source/leakage epitaxial region, form contact plug.
Correspondingly, according to another aspect of the present invention, provide a kind of semiconductor structure, this semiconductor junctionStructure comprises substrate, gate stack, side wall, interlayer dielectric layer, contact plug, wherein:
Source/drain region and source/leakage epitaxial region are formed among described substrate; Described gate stack is formed on described lining, described interlayer dielectric layer covers described source/drain region and described source/leakage epitaxial region at the end, and described side wall formsIn the side-walls of described gate stack,
It is characterized in that,
Described contact plug runs through described interlayer dielectric layer and extends to inside, described source/leakage epitaxial region, described source/The length of leaking epitaxial region is greater than the length of described source/drain region, and described length is to be parallel to orientationTolerance.
Compared with prior art, semiconductor structure provided by the invention and manufacture method thereof have following advantage:
Before forming source/drain region, in the time exposing composition, except forming source/drain region, also form oneSource/leakage epitaxial region, in the time forming contact plug, can be formed on source/leakage epitaxial region. Due to contact plugBe not formed on source/drain region, the area of source/drain region just can not be subject to the restriction of contact plug area so, thereforeCan effectively reduce the area of source/drain region, and then reduce the area of semiconductor structure, increase the integrated of deviceDegree.
Brief description of the drawings
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, thisIt is more obvious that bright other features, objects and advantages will become:
Fig. 1-Fig. 3 is the structural representation of semiconductor structure in prior art;
Fig. 4-Fig. 9 (b) is the structural representation of semiconductor structure, in accordance with the present invention in each fabrication stage;
Figure 10 is according to the flow chart of semiconductor making method of the present invention detailed description of the invention.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to thisBright embodiment is described in detail.
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, whereinSame or similar label represents same or similar element or has identical or similar functions from start to finishElement. Exemplary below by the embodiment being described with reference to the drawings, only for explaining the present invention, andCan not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different knot of the present inventionStructure. Of the present invention open in order to simplify, hereinafter the parts to specific examples and setting are described. WhenSo, they are only example, and object does not lie in restriction the present invention. In addition, the present invention can be notWith repeat reference numerals in example and/or letter. This repetition is in order to simplify and object clearly, itsBody is not indicated the relation between discussed various embodiment and/or setting. What the invention provides in addition, is eachPlant the example of specific technique and material, but those of ordinary skill in the art can recognize other techniquesThe property of can be applicable to and/or the use of other materials. In addition, First Characteristic described below is at Second CharacteristicIt " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can compriseThe embodiment of other Characteristics creation between the first and second features, such the first and second features mayIt not direct contact. It should be noted that illustrated parts are not necessarily drawn in proportion in the accompanying drawings. ThisBright omission the description of known assemblies and treatment technology and technique to avoid unnecessarily limiting the present invention.
Because semiconductor devices provided by the invention has several preferred structures, below respectively to each instituteStating preferred structure summarizes.
Embodiment mono-:
Please refer to Fig. 6 (a), Fig. 7, Fig. 8 (a) and Fig. 9 (a). Fig. 6 (a), Fig. 7, Fig. 8 (a)And Fig. 9 (a) is the plan structure signal according to each fabrication stage of a specific embodiment of the present inventionFigure. This semiconductor structure comprises outside substrate 100, gate stack, side wall 240, source/drain region 110 and source/leakageProlong district 120. Described gate stack is formed on described substrate 100, and side wall 240 is formed on this gate stackSide-walls. After planarization, the top of interlayer dielectric layer 300 and source/drain region 110, source/leakage epitaxial region 120Portion flushes, as shown in Figure 7. Above source/leakage epitaxial region 120, form the contact that runs through interlayer dielectric layer 300Hole 310, exposes source/leakage epitaxial region 120, as shown in Fig. 8 (a). And fill and connect in contact hole 310Touch metal, to form contact plug 320, as shown in Fig. 9 (a). Described gate stack comprises grid 230 HesGate dielectric layer 220 can be seen the grid 230 of gate stack from Fig. 6 (a). Preferably, described inThe top of the top of gate stack and contact plug 320 flush with plane on first medium layer 300 (herein,Term " flushes " and means difference in height between the two in the scope of fabrication error permission).
In addition, this semiconductor structure also comprises in described contact plug 320 and described substrate 100 and to exposeMetal silicide 130 between source/leakage epitaxial region 120.
Alternatively, this semiconductor structure also comprises the lining that is formed on described contact hole 310 inwalls and bottom(not illustrating in the drawings).
With reference to figure 9 (a), contact plug 320 is positioned at gate stack both sides, in some other embodiment, connectsThe formation position of touching plug 320 also has other arrangement, please refer to the description of embodiment bis-.
Embodiment bis-:
Please refer to Fig. 6 (b), Fig. 7, Fig. 8 (b) and Fig. 9 (b). Fig. 6 (b), Fig. 7, Fig. 8 (b)And Fig. 9 (b) shows according to the plan structure of another each fabrication stage of detailed description of the invention of the present inventionIntention. Be with the difference of embodiment mono-, each side of gate stack have two source/leakage epitaxial regions 120,Contact hole 310 and contact plug 320, multiple contact plugs can make the contact resistance of source/drain region can be less, carryThe overall performance of high device.
It should be noted that, above-mentioned two embodiment are only as exemplary illustration, not for limiting thisBright, the number of contact plug 320 and position can be adjusted as required, for example, can also make contact plug320 are positioned at gate stack down either side etc.
Hereinafter in connection with the manufacture method of semiconductor structure provided by the invention, above-mentioned two kinds of embodiment are enteredRow is further set forth.
Please refer to Figure 10, Figure 10 is a concrete reality of the manufacture method of semiconductor structure, in accordance with the present inventionThe flow chart of executing mode, the method comprises:
Step S101, provides substrate 100, on described substrate 100, forms gate stack;
Step S102 forms source/drain region 110 and source/leakage epitaxial region 120 on described substrate 100, described source/Leak epitaxial region 120 and be connected with described source/drain region, and its length is greater than the length of described source/drain region 110, described inLength be run through and the direction of vertical source electrode, gate stack and drain electrode on distance;
Step S103, forms and covers described gate stack, described source/drain region 110 and described source/leakage epitaxial region120 interlayer dielectric layer;
Step S104 forms contact plug 320 on described source/leakage epitaxial region 120.
Below in conjunction with Fig. 4 to Fig. 9 (b), step S101 is described Fig. 4 to Fig. 9 (b) to step S104That multiple detailed description of the invention according to the present invention are according to the flow manufacturing semiconductor devices process shown in Figure 10In each fabrication stage of this semiconductor devices structural representation of each (comprise sectional structure schematic diagram and bowingTV structure schematic diagram). It should be noted that, the accompanying drawing of each embodiment of the present invention is only in order to illustrateObject, is therefore not necessarily to scale.
Step S101, provides substrate 100. Substrate 100 comprises silicon substrate (for example silicon wafer). According to existingHave the known designing requirement of technology (for example P type substrate or N-type substrate), substrate 100 can comprise variousDoping configuration. In other embodiment, substrate 100 can also comprise other basic semiconductor, for example germanium. Or,Substrate 100 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.Typically, substrate 100 can have but be not limited to the thickness of about hundreds of micron, for example can beIn the thickness range of 400um-800um.
Fig. 4 one is formed with the overlooking of semiconductor structure of grid 230 and side wall 240 on substrate 100Schematic diagram, Fig. 5 is the generalized section along Fig. 4 center line A-A '. As shown in Figure 4 and Figure 5, at substrateOn 100, form gate stack, gate stack comprises gate dielectric layer 220 and grid 230. First, halfIn conductive substrate 100, deposit gate dielectric layer 220. Gate dielectric layer 220 is positioned in Semiconductor substrate 100,It can be thermal oxide layer, comprises silica, silicon oxynitride, also can be high K dielectric, for example HfAlON,In HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiONA kind of or its any combination, the thickness of gate dielectric layer 220 can be 1nm～5nm, as 2nm or 3nm.
On gate dielectric layer 220, deposit grid layer, for example by deposit spathic silicon, TaN, TaC, TiN,TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTaxIn a kind of or its combine to form. By photoresist composition and etching grid layer and gridDielectric layer forms gate stack.
Especially, can on the sidewall of described gate stack, form side wall 240, for gate stack is protectedProtect. Gate stack top can also be useful on the cap rock (not shown) of grill-protected stacks. Side wall240 can be by silicon nitride, silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materialsMaterial forms. Side wall 240 can have sandwich construction. Side wall 240 can be by comprising deposition-etch technique shapeBecome, its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Step S102 forms source/drain region 110 and source/leakage epitaxial region 120 on described substrate 100. Described source/Leak epitaxial region 120 and be connected with source/drain region 110, and its shape is at source/drain region 110 side extending projections, its planeSimilar wing, is called wing. Length that it should be noted that described source/leakage epitaxial region 120 is greater than described sourceThe length in/drain region 110, described length is the tolerance that is parallel to orientation. For example, its direction is for passing throughWear and the direction of vertical source electrode, gate stack and drain electrode on distance. Due to formation source/leakage epitaxial region 120That therefore the length of source/leakage epitaxial region 120 and width should be greater than respectively in order to form therein contact plug 320The length of at least one contact plug 320 and width. In addition, because contact plug 320 is formed at source/leakage epitaxial regionOn 120, therefore the length of source/drain region 110 can be much smaller than the length of contact plug 320, even source/drain region 110Width constant, also can effectively reduce its area, and then can reduce the area of whole semiconductor structure,Increase the integrated level of semiconductor devices.
Source/drain region 110 and source/leakage epitaxial region 120 can be by comprising photoetching, Implantation, diffusion, extension lifeMethods long and/or other appropriate process form, and can form prior to gate dielectric layer.
For example, can first on substrate 100, form mask pattern. Particularly, can be first at described substrateOn 100, cover one deck photoresist, but the material vinyl monomer material of photoresist, contain nitrine quinones chemical combinationThe material of thing or polyethylene laurate material, it is suitable need to select according to concrete manufactureMaterial. Secondly,, to this photoresist composition that exposes, form the region that needs Implantation, this districtThe position in territory is above substrate 100, and correspondence will form the position of described source/drain region 110 and source/leakage epitaxial region 120Put. Afterwards, connected to form to injecting P type or N-type alloy or impurity in substrate 100 according to described regionSource/drain region 110 and source/leakage epitaxial region 120. For nmos device, outside source/drain region 110 and source/leakageProlonging district 120 can be the Si of N-type doping, conventionally uses N-type ion as phosphorus, arsenic etc. inject, and injects denseDegree is about 1013～1016/cm2. For PMOS device, source/drain region 110 and source/leakage epitaxial region 120 canTo be the SiGe of P type doping, conventionally use P type ion to inject as boron, boron fluoride etc., implantation concentrationBe about 1013～1016/cm2. Owing to source/drain region 110 and source/leakage epitaxial region 120 carrying out Implantation simultaneously, itsDoping content is identical.
Step S103, forms and covers described gate stack, described source/drain region 110 and described source/leakage epitaxial region120 interlayer dielectric layer 300. Interlayer dielectric layer 300 can be by chemical vapour deposition (CVD) (ChemicalVaporDeposition, CVD), high-density plasma CVD, spin coating or other suitable method shapesBecome on substrate 100. The material of interlayer dielectric layer 300 can comprise SiO2, carbon doping SiO2、BPSG、PSG, UGS, silicon oxynitride, low-k materials or its combination. The thickness range of interlayer dielectric layer 300 can40nm～150nm, as 80nm, 100nm or 120nm.
In the present embodiment, to interlayer dielectric layer 300 and gate stack on this semiconductor devicesLearn the planarization of machine glazed finish (Chemical-MechanicalPolish, CMP), as shown in Figure 7,Make the upper surface flush of upper surface and the interlayer dielectric layer 300 of this gate stack, and expose described gridThe grid 230 of the stacking middle the superiors or cap rock (not shown) and side wall 240. When described grid pile stacked packageDraw together in the situation of dummy grid, can carry out replacement gate process. Specifically, first remove dummy grid, heavyLong-pending metal gate, carries out planarization to metal gate, and its top is flushed with interlayer dielectric layer 300.
Step S104 forms contact plug 320 on described source/leakage epitaxial region 120. Etching interlayer dielectric layer300 form source/leakage epitaxial region 120 contact hole 310 of exposure at least partly making on substrate 100, as figureShown in 8 (a) and Fig. 8 (b). In Fig. 8 (a), contact hole 310 is positioned at gate stack both sides, Fig. 8(b) in, contact hole 310 is positioned at gate stack both sides, each two contact holes 310 of every side. Should be appreciated thatAccompanying drawing is only example, contact hole 310 can also gate stack both sides respectively have multiple, and can be asymmetricArrange. Particularly, can use dry etching, wet etching or other suitable etching mode etch layerBetween dielectric layer 300 with form contact hole 310. In the time carrying out this etching, need first on grid, to form and coverMould layer is to protect this grid. After contact hole 310 forms, make the source/leakage epitaxial region 120 in substrate 100 sudden and violentReveal. Because gate stack is protected by side wall 240, even if therefore carried out in the time forming contact hole 310Etching can not cause the short circuit of grid and source/drain electrode yet. If source/leakage epitaxial region 120 is by outside selectiveThe source-drain electrode structure of the lifting that epitaxial growth forms, the top of its epitaxial part is higher than gate stack bottom,Contact hole 310 can be formed into source/leakage epitaxial region 120 inner with gate stack bottom the position that flushes beOnly, like this when at the interior filling contacting metal of contact hole 310 during with formation contact plug 320, this contacting metalCan contact with source/leakage epitaxial region 120 with bottom by the partial sidewall of contact hole 310, thereby furtherIncrease contact area and reduce contact resistance.
As shown in Fig. 8 (a) and Fig. 8 (b), the bottom of contact hole 310 is the source/leakage epitaxial regions that expose120, plated metal on this source/leakage epitaxial region 120, carries out forming metal silicide 130 after annealing in process.Particularly, first, by contact hole 310, adopt Implantation, deposited amorphous compound or selectively rawLong mode, carries out pre-amorphous processing to the source/leakage epitaxial region 120 exposing, and forms local amorphous silicon regionTerritory; Then utilize metal sputtering mode or chemical vapour deposition technique, on this source/leakage epitaxial region 120, formMetal level uniformly. Preferably, this metal can be nickel. Certainly this metal can be also that other are feasibleMetal, such as Ti, Co or Cu etc. Subsequently this semiconductor structure is annealed, in other enforcementIn example, can adopt other annealing process, as rapid thermal annealing, spike annealing etc. According to of the present inventionEmbodiment, adopt spike technique to anneal to device conventionally, for example, about more than 1000 DEG CTemperature is carried out Microsecond grade laser annealing, makes the metal of described deposition and these source/leakage epitaxial region 120 interior formationAmorphous compound reacts and forms metal silicide 130, finally can select the method for chemical etching to remove notThe described metal of the deposition of reaction. Described amorphous compound can be non-crystalline silicon, decrystallized SiGe or amorphousOne in SiClx carbon. The benefit that forms metal silicide 130 is to reduce connecing in contact plug 320Touch the resistivity between metal and source/leakage epitaxial region 120, further reduce contact resistance.
It should be noted that forming the step of metal silicide 130 is preferred steps, i.e. also shape notBecome metal silicide 130, directly in contact hole 310, fill contacting metal, form contact plug 320.
In contact hole 310, fill contacting metal by the method for deposition and form contact plug 320, as Fig. 9 (a)And shown in Fig. 9 (b). This contacting metal have with described substrate 100 in expose source/leakage epitaxial region 120(described " electrical connection " refers to the possible direct and substrate of lower part of contacting metal to the lower part being electrically connectedSource/leakage the epitaxial region 120 exposing in 100 contacts, also may be by the source/leakage extension exposing in substrate 100Source/leakage the epitaxial region 120 exposing in the metal silicide 130 forming in district 120 and substrate 100 forms realElectric connection in matter), this contacting metal runs through described interlayer dielectric layer 300 and exposes through contact hole 310Its top.
Preferably, the material of contacting metal is W. Certainly according to semi-conductive manufacture needs, contacting metalMaterial include but not limited in W, Al, TiAl alloy any or its combination. Alternatively, fillingBefore contacting metal, inwall and the bottom that can be chosen in contact hole 310 form lining (not in the drawingsIllustrate), this lining can be deposited on contact hole 310 by depositing operations such as ALD, CVD, PVDInwall and bottom, the material of this lining can be Ti, TiN, Ta, TaN, Ru or its combination, this liningThe thickness of layer can be 5nm-20nm, as 10nm or 15nm.
Complete subsequently the manufacture of this semiconductor devices according to the step of conventional semiconductor fabrication process.
The manufacture method of semiconductor structure of the present invention, and the semiconductor structure that adopts the present invention to manufacture,Contact plug is formed on source/leakage epitaxial region, has effectively reduced source/drain region length and area, partly lead in guaranteeWhen the performance of body structure, reduce its area, increased the integrated level of semiconductor devices.
Although describe in detail about example embodiment and advantage thereof, be to be understood that and do not departing from the present inventionSpirit and the situation of protection domain that limits of claims under, can carry out respectively these embodimentPlant variation, substitutions and modifications. For other examples, those of ordinary skill in the art should easily understandIn keeping in protection domain of the present invention, the order of processing step can change.
In addition, range of application of the present invention be not limited to the specific embodiment of describing in description technique,Mechanism, manufacture, material composition, means, method and step. From disclosure of the present invention, as thisThe those of ordinary skill in field will easily be understood, at present existed or be about to develop laterTechnique, mechanism, manufacture, material composition, means, method or step, wherein they are carried out and the present inventionIdentical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing, can according to the present inventionSo that they are applied. Therefore, claims of the present invention are intended to these technique, mechanism, systemMake, material composition, means, method or step be included in its protection domain.
Claims (8)
1. a manufacture method for semiconductor structure, is characterized in that, comprises the following steps:
(a) provide substrate (100), on described substrate (100), form gate stack;
(b) adopt the mode of Implantation on described substrate (100), to form source/drain region (110) simultaneouslyAnd source/leakage epitaxial region (120), described source/leakage epitaxial region (120) is connected with described source/drain region (110),And in source/drain region, (110) side is aerofoil profile projection along being parallel to orientation to its shape, and its length is largeIn the length of described source/drain region (110);
(c) form and cover described gate stack, described source/drain region (110) and described source/leakage epitaxial region (120)Interlayer dielectric layer (300);
(d) the upper contact plug (320) that forms in described source/leakage epitaxial region (120).
2. method according to claim 1, wherein, adopts the mode of Implantation at described substrate(100) upper source/drain region (110) and the source/leakage epitaxial region (120) of forming, further comprising the steps of:
(e) at the upper photoresist that forms of described substrate (100);
(f), to the photoresist composition that exposes, form and treat injection zone;
(g) Implantation is carried out in described region.
3. method according to claim 1, wherein, upper formation in described source/leakage epitaxial region (120)Contact plug (320), further comprising the steps of:
(h) in described interlayer dielectric layer (300), formation at least makes the institute on described substrate (100)State the contact hole (310) that source/leakage epitaxial region (120) part exposes;
(i) go up formation metal silicide in source/leakage epitaxial region (120) of the exposure of described substrate (100)(130)；
(j) in described contact hole (310), fill contacting metal.
4. method according to claim 1, wherein, described source/leakage epitaxial region (120) is wing.
5. a semiconductor structure, comprising: substrate (100), source/drain region (110) and source/leakage epitaxial region(120), gate stack, interlayer dielectric layer (300), contact plug (320), wherein:
Source/drain region (110) and source/leakage epitaxial region (120) are formed among described substrate (100); InstituteState gate stack and be formed on described substrate (100), described in described interlayer dielectric layer (300) coversSource/drain region (110) and described source/leakage epitaxial region (120),
It is characterized in that,
Described contact plug (320) runs through described interlayer dielectric layer (300) and extends to described source/leakage extensionDistrict (120), in source/drain region, edge, (110) side is parallel to the shape of described source/leakage epitaxial region (120)Orientation is aerofoil profile projection, and its length is greater than the length of described source/drain region (110), described lengthFor being parallel to the tolerance of orientation.
6. semiconductor structure according to claim 5, wherein, described source/leakage epitaxial region (120) isWing.
7. semiconductor structure according to claim 5, wherein, described source/leakage epitaxial region (120) heightIn described gate stack bottom, described contact plug (320) extends in described source/leakage epitaxial region (120)Portion.
8. semiconductor structure according to claim 5, wherein, position, described source/leakage epitaxial region (120)One or both sides on the width of source/drain region (110);
Semiconductor structure according to claim 5, wherein, described source/leakage epitaxial region (120) is subject toForeign ion doping, and its doping content is identical with source/drain region (110).
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| CN102856206A (en) | 2013-01-02 |
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