CN102854801A - High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex - Google Patents
High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex Download PDFInfo
- Publication number
- CN102854801A CN102854801A CN2012103587600A CN201210358760A CN102854801A CN 102854801 A CN102854801 A CN 102854801A CN 2012103587600 A CN2012103587600 A CN 2012103587600A CN 201210358760 A CN201210358760 A CN 201210358760A CN 102854801 A CN102854801 A CN 102854801A
- Authority
- CN
- China
- Prior art keywords
- fpga
- ram
- sharing multiplex
- time
- dynamic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention belongs to the field of testing technology of programmable logic element and particularly relates to a high data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex, and aims to solve the problem that the high data volume FPGA simulating test is insufficient in internal memory and improves the sufficiency of the high data volume FPGA simulating test. The high data volume FPGA simulating testing method comprises the step of reducing the internal memory source used for the simulating test within the allowable capacity range of a simulating tool, dividing the RAM (Random Access Memory) data to be tested into a plurality of parts based on the volume of the internal memory source, testing the plurality of divided RAM data through a time sharing multiplex way, and dynamically calculating the internal memory space of a system as current simulating requirement through an internal memory dynamic managing method, and distributing and releasing the internal memory.
Description
Technical field
The invention belongs to the programmable logic device (PLD) technical field of measurement and test, relate to a kind of big data quantity FPGA emulation test method based on time-sharing multiplex, especially a kind of method of testing that is applied to big data quantity FPGA (Field Programmable Gate Array, field programmable gate array) that relates to " time-sharing multiplex " and " emulation ".
Background technology
Along with the application of FPGA in being applied in the products such as Aeronautics and Astronautics, weapon is increasingly extensive, its test job is also further important.But because the restriction of emulation tool for day by day complicated FPGA data processing software, adopts conventional emulation test method to be difficult to the correctness that big data quantity is processed is tested.Big data quantity among the FPGA typically refers to data volume that FPGA processes and takies PC memory and surpass 50% situation.
The development process of programmable logic device (PLD) project comprises: design input, logic synthesis, placement-and-routing's three phases.
Design input: by the describing method of standard, finish by the conversion of system design philosophies to the net table.The principal mode of design comprises VHDL language design, Verilog language design schematic diagram or state machine design etc.
Logic synthesis: logic synthesis is that the logic netlist that is comprised of basic logic unit is translated in the designs such as hardware description language, schematic diagram, state machine input, the net meter file of outputting standard form is realized for placement-and-routing's device of programmable logic device (PLD) manufacturer.
Placement-and-routing: placement-and-routing's process is to convert the net meter file after the logic synthesis to can be loaded into the bit stream file in the chip process by instrument.
For the performance history of FPGA, all there is corresponding test process corresponding with it.Wherein, the corresponding relation that relates to the test process of emulation and FPGA software development process as shown in Figure 1.
Summary of the invention
The objective of the invention is in order to solve the problem of big data quantity FPGA emulation testing low memory, in order to improve the adequacy of big data quantity FPGA emulation testing, provide a kind of method that time-sharing multiplexing technology is carried out the FPGA emulation testing of using.
The technical solution used in the present invention is:
A kind of big data quantity FPGA emulation test method based on time-sharing multiplex may further comprise the steps:
Step S1: in the capacity that the employed memory source of minimizing emulation testing allows to emulation tool encloses;
Step S2: the RAM data according to the large young pathbreaker's needs test of memory source are divided into some parts, and wherein every part amount of capacity must not surpass the memory source size;
Step S3: adopt the time-sharing multiplex mode, respectively several RAM data divisions that mark off are tested;
Step S4: when time-sharing multiplex, adopt the method for dynamic management internal memory, the needed Installed System Memory of the current emulation testing of dynamic calculation space also internally deposits into row distribution and release.
A kind of big data quantity FPGA emulation test method based on time-sharing multiplex as mentioned above, wherein: described time-sharing multiplexing method, the method for taking that the dynamic memory management device is set or the dynamic memory management device being carried out modeling, the internal memory of dynamic management Distribution Calculation machine.
A kind of big data quantity FPGA emulation test method based on time-sharing multiplex as mentioned above, wherein: utilize described dynamic memory management device to calculate the minimum internal memory that FPGA once tests required ram space, then the dynamic memory management device comes the dynamic release calculator memory by the tracking that whether RAM current operation address is reached the maximum address value of RAM, and carries out the distribution of Dram between the high low address of RAM.
A kind of big data quantity FPGA emulation test method based on time-sharing multiplex as mentioned above, wherein: before test, use hardware description language that the behaviour of the outer RAM of sheet is carried out the behavioral scaling simulation modeling, and be connected with FPGA.
A kind of big data quantity FPGA emulation test method based on time-sharing multiplex as mentioned above, wherein: among the described step S2, according to the height of RAM read/write address the RAM data on average are divided into two parts; Input test excitation is stored test to front 1/2 data of FPGA output first, and this part data of then FPGA being read RAM are tested;
Again rear 1/2 data of FPGA output are stored test, this part data of then FPGA being read RAM are tested.
A kind of big data quantity FPGA emulation test method based on time-sharing multiplex as mentioned above, wherein: the result who obtains for test, its form with wave file or data file is kept on the PC, whether judges unanimously by comparison simulation result wave file or data file whether the dynamic memory management device has correctly been realized to the time-sharing multiplex of the high low address space of RAM with to dynamic assignment and the release of PC memory.
The invention has the beneficial effects as follows:
By the mode of time-sharing multiplex, the RAM data are verified, realize at times practical exampleization device, reduce hardware exampleization quantity, improve the hardware model service efficiency, and then reduce the PC Dram and distribute, for realizing that more the emulation testing of big data quantity provides condition.
By dynamic memory management management Memory Allocation, realize distribution and the use of Real Time Monitoring PC memory, and then dynamically realized the management of PC memory, effectively guaranteeing to have realized the more emulation testing of big data quantity on the basis of PC reliability service.
Improve analog device port service efficiency by time-sharing multiplex, reducing PC system Dram distributes, in conjunction with dynamic memory management management Memory Allocation, effectively guarantee the normal operation of PC, further improved simultaneously the memory usage of system, for the emulation testing of Large Volume Data more provides condition.
Description of drawings
Fig. 1 is existing FPGA exploitation and test flow chart;
Fig. 2 is the process flow diagram of a kind of big data quantity FPGA emulation test method based on time-sharing multiplex provided by the invention;
Fig. 3 is that method provided by the invention is to the test process of low address data;
Fig. 4 is that method provided by the invention is to the test process of high address data;
Fig. 5 is that method provided by the invention is to allocation manager and the time-sharing multiplex process of Dram (RAM);
Fig. 6 is the implementation method that method provided by the invention is distributed dynamic memory management.
Embodiment
Below in conjunction with drawings and Examples a kind of big data quantity FPGA emulation test method based on time-sharing multiplex provided by the invention is described further:
As shown in Figure 2, a kind of big data quantity FPGA emulation test method based on time-sharing multiplex may further comprise the steps:
Step S1: in the capacity that the minimizing employed memory source of emulation testing (mem_need) allows to emulation tool encloses;
Step S2: the RAM data according to the large young pathbreaker's needs test of memory source are divided into some parts, and wherein every part amount of capacity must not surpass the memory source size;
Step S3: adopt the time-sharing multiplex mode, respectively several RAM data divisions that mark off are tested;
Step S4: when time-sharing multiplex, adopt the method for dynamic management internal memory, internally deposit into the row distribution and discharge the utilization ratio of raising Installed System Memory by the needed Installed System Memory of the current emulation testing of dynamic calculation space.
For obtaining better effect, before step S1, can use hardware description language (verilog or vhdl) to carry out the behavioral scaling simulation modeling for the behaviour of the outer RAM (for example can adopt SRAM) of sheet, and be connected with FPGA (for example carrying out the FPGA of image Compression).
In described step S2, according to the height of RAM read/write address the RAM data on average are divided into two parts, namely size is former half of definition SRAM size of needing.
As shown in Figure 3, input test excitation is stored test to front 1/2 data (low address) of FPGA output first, and this part data of then FPGA being read RAM are tested;
As shown in Figure 4, rear 1/2 data (high address) of FPGA output are stored test, this part data of then FPGA being read RAM are tested.
As shown in Figure 5, time-sharing multiplexing method can be preferably, and takes to arrange the method for dynamic memory management device (perhaps the dynamic memory management device being carried out modeling), the internal memory of dynamic management Distribution Calculation machine, optimize the memory management of time-sharing multiplex, and then realize the emulation testing of more jumbo data.
As shown in Figure 6, between FPGA and RAM by modeling realizes FPGA is once tested the calculating of the minimum internal memory (mem_min) of required ram space to the dynamic memory management device, the dynamic memory management device of modeling comes the dynamic release calculator memory by the tracking that whether RAM current operation address is reached the maximum address value of RAM, and carries out the distribution of Dram between the high low address of RAM.
At last, the result of test can be kept on the PC with the form of wave file or data file, whether judge unanimously by comparison simulation result wave file or data file method whether the dynamic memory management device has correctly been realized to the time-sharing multiplex of the high low address space of RAM with to dynamic assignment and the release of PC memory, and then can judge that time-sharing multiplex and dynamic memory management optimize the advantage that emulation testing brings to Large Volume Data.
The advantage example that this method of testing is brought is as follows:
Can make in some FPGA design by this method of testing that situation that can't realize becomes possibility owing to causing that PC memory is not enough when needing Large Volume Data emulation, as shown in table 1 below be that data are processed required outer SRAM and stored the exampleization operating position in certain compression of images project:
PC distributed analog device pin and Memory Allocation relatively before and after table 1 adopted this method of testing
By upper table statement as can be known, this method of testing has guaranteed the kilter of system's operation simultaneously on the basis that guarantees the management of Installed System Memory normal allocation, owing to having adopted the thought of time-sharing multiplex, reduced at double the quantity of hardware simulation model exampleization, adopt simultaneously the mode of Dram allocation manager that the service efficiency of Installed System Memory is further improved, effectively guaranteed the task of all kinds of Large Volume Data emulation testings.
Claims (6)
1. big data quantity FPGA emulation test method based on time-sharing multiplex may further comprise the steps:
Step S1: in the capacity that the employed memory source of minimizing emulation testing allows to emulation tool encloses;
Step S2: the RAM data according to the large young pathbreaker's needs test of memory source are divided into some parts, and wherein every part amount of capacity must not surpass the memory source size;
Step S3: adopt the time-sharing multiplex mode, respectively several RAM data divisions that mark off are tested;
Step S4: when time-sharing multiplex, adopt the method for dynamic management internal memory, the needed Installed System Memory of the current emulation testing of dynamic calculation space also internally deposits into row distribution and release.
2. described a kind of big data quantity FPGA emulation test method based on time-sharing multiplex according to claim 1 is characterized by:
Described time-sharing multiplexing method, the method for taking that the dynamic memory management device is set or the dynamic memory management device being carried out modeling, the internal memory of dynamic management Distribution Calculation machine.
3. described a kind of big data quantity FPGA emulation test method based on time-sharing multiplex according to claim 2, it is characterized by: utilize described dynamic memory management device to calculate the minimum internal memory that FPGA once tests required ram space, then the dynamic memory management device comes the dynamic release calculator memory by the tracking that whether RAM current operation address is reached the maximum address value of RAM, and carries out the distribution of Dram between the high low address of RAM.
4. described a kind of big data quantity FPGA emulation test method based on time-sharing multiplex according to claim 3 is characterized by: before test, use hardware description language that the behaviour of the outer RAM of sheet is carried out the behavioral scaling simulation modeling, and be connected with FPGA.
5. described a kind of big data quantity FPGA emulation test method based on time-sharing multiplex according to claim 4 is characterized by: among the described step S2, according to the height of RAM read/write address the RAM data on average are divided into two parts; Input test excitation is stored test to front 1/2 data of FPGA output first, and this part data of then FPGA being read RAM are tested;
Again rear 1/2 data of FPGA output are stored test, this part data of then FPGA being read RAM are tested.
6. described a kind of big data quantity FPGA emulation test method based on time-sharing multiplex according to claim 5, it is characterized by: the result who obtains for test, its form with wave file or data file is kept on the PC, whether judges unanimously by comparison simulation result wave file or data file whether the dynamic memory management device has correctly been realized to the time-sharing multiplex of the high low address space of RAM with to dynamic assignment and the release of PC memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103587600A CN102854801A (en) | 2012-09-25 | 2012-09-25 | High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103587600A CN102854801A (en) | 2012-09-25 | 2012-09-25 | High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102854801A true CN102854801A (en) | 2013-01-02 |
Family
ID=47401469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103587600A Pending CN102854801A (en) | 2012-09-25 | 2012-09-25 | High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102854801A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104238376A (en) * | 2014-09-30 | 2014-12-24 | 东南大学 | Low-temperature and low-air-pressure environment generator set running simulating system based on data |
| CN111369287A (en) * | 2020-03-04 | 2020-07-03 | 腾讯科技（深圳）有限公司 | Information processing method, information processing device, computer storage medium and computer equipment |
| CN112559264A (en) * | 2020-12-08 | 2021-03-26 | 北京京航计算通讯研究所 | Simulation test method for realizing FPGA (field programmable Gate array) universal serial port by verification platform based on UVM (Universal verification Module) |
| CN112835759A (en) * | 2021-02-01 | 2021-05-25 | 百度在线网络技术（北京）有限公司 | Test data processing method and device, electronic equipment and storage medium |
| WO2022088395A1 (en) * | 2020-10-28 | 2022-05-05 | 福州大学 | Method for constructing practical logic verification architecture-level fpga wiring device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620643A (en) * | 2009-07-03 | 2010-01-06 | 中国人民解放军国防科学技术大学 | Design method of architecture simulating system based on FPGA |
-
2012
- 2012-09-25 CN CN2012103587600A patent/CN102854801A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620643A (en) * | 2009-07-03 | 2010-01-06 | 中国人民解放军国防科学技术大学 | Design method of architecture simulating system based on FPGA |
Non-Patent Citations (5)
| Title |
|---|
| 余翔湛等: "动态共享内存缓冲池技术", 《哈尔滨工业大学学报》, vol. 36, no. 3, 31 March 2004 (2004-03-31) * |
| 刘炜等: "FPGA联机测试方法的研究与实现", 《计算机与数字工程》, vol. 37, no. 7, 31 July 2009 (2009-07-31) * |
| 李红宇: "模拟存储管理演示***的设计与实现", 《黑龙江农垦师专学报》, no. 2, 31 December 2002 (2002-12-31) * |
| 杨硕等: "通用FPGA算法测试平台", 《微计算机信息》, vol. 22, no. 72, 31 December 2006 (2006-12-31) * |
| 赖联有等: "三相空间矢量PWM仿真及其基于FPGA的硬件实现", 《电子与封装》, vol. 5, no. 1, 31 January 2005 (2005-01-31) * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104238376A (en) * | 2014-09-30 | 2014-12-24 | 东南大学 | Low-temperature and low-air-pressure environment generator set running simulating system based on data |
| CN111369287A (en) * | 2020-03-04 | 2020-07-03 | 腾讯科技（深圳）有限公司 | Information processing method, information processing device, computer storage medium and computer equipment |
| WO2022088395A1 (en) * | 2020-10-28 | 2022-05-05 | 福州大学 | Method for constructing practical logic verification architecture-level fpga wiring device |
| CN112559264A (en) * | 2020-12-08 | 2021-03-26 | 北京京航计算通讯研究所 | Simulation test method for realizing FPGA (field programmable Gate array) universal serial port by verification platform based on UVM (Universal verification Module) |
| CN112559264B (en) * | 2020-12-08 | 2021-08-06 | 北京京航计算通讯研究所 | Simulation test method for realizing FPGA (field programmable Gate array) universal serial port by verification platform based on UVM (Universal verification Module) |
| CN112835759A (en) * | 2021-02-01 | 2021-05-25 | 百度在线网络技术（北京）有限公司 | Test data processing method and device, electronic equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9147024B1 (en) | Hardware and software cosynthesis performance estimation | |
| CN102035697B (en) | Concurrent connections performance testing system and method for file system | |
| CN102854801A (en) | High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex | |
| US10521544B2 (en) | Traffic shaping in networking system-on-chip verification | |
| CN104205052B (en) | The method and system of measured device is emulated with field programmable gate array | |
| US9081925B1 (en) | Estimating system performance using an integrated circuit | |
| CN105183665A (en) | Data-caching access method and data-caching controller | |
| US10180850B1 (en) | Emulating applications that use hardware acceleration | |
| US9529946B1 (en) | Performance estimation using configurable hardware emulation | |
| CN103136120B (en) | Row buffering operating strategy defining method and device, bank division methods and device | |
| CN104599227A (en) | DDR3 arbitration controller and method applied to high-speed CCD data storage | |
| CN104765701B (en) | Data access method and equipment | |
| US7478027B2 (en) | Systems, methods, and media for simulation of integrated hardware and software designs | |
| CN109446740B (en) | System-on-chip architecture performance simulation platform | |
| CN114780422A (en) | Code verification system and code verification method | |
| CN104050193A (en) | Message generating method and data processing system for realizing method | |
| CN101714075A (en) | Function calling method and device | |
| US10664637B2 (en) | Testbench restoration based on capture and replay | |
| CN108804380A (en) | The cascade Cycle accurate model of vector calculus hardware accelerator multinuclear | |
| CN102523374B (en) | Method for designing real-time parallel electronic image stabilization system | |
| CN108701091A (en) | Chance memory for dynamic workload is finely tuned | |
| US11593547B1 (en) | Prediction and optimization of multi-kernel circuit design performance using a programmable overlay | |
| CN106709116A (en) | Method and device for generating RTL (Register Transfer Logic)-level IP (Intellectual Property) core | |
| CN103902767A (en) | QEMU and SystemC based multi-core simulator | |
| US11520531B1 (en) | Systems and methods for intercycle gap refresh and backpressure management |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130102 |