CN102841853B - Memory management table disposal route, Memory Controller and memorizer memory devices - Google Patents
Memory management table disposal route, Memory Controller and memorizer memory devices Download PDFInfo
- Publication number
- CN102841853B CN102841853B CN201110173868.8A CN201110173868A CN102841853B CN 102841853 B CN102841853 B CN 102841853B CN 201110173868 A CN201110173868 A CN 201110173868A CN 102841853 B CN102841853 B CN 102841853B
- Authority
- CN
- China
- Prior art keywords
- memory
- those
- invalid bit
- management table
- memory management
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides a kind of memory management table disposal route, Memory Controller and memorizer memory devices, wherein method is in order to be stored in the memory buffer of memorizer memory devices by the multiple logins belonging to multiple memory management table, and wherein each login has at least one invalid bit.This method is included in memory buffer and divides corresponding region for each memory management table.This method also comprises for invalid bit metamessage corresponding to each memory management table record.This method also comprises the invalid bit removed according to the invalid bit metamessage of each memory management table corresponding in each login, to produce the valid data string of corresponding each login.This method also comprises and being write in the corresponding region in memory buffer by each valid data string.Base this, the storage area of memory buffer can be utilized effectively.
Description
Technical field
The present invention relates to a kind of memory management table disposal route, and in particular to a kind of by the serial data write buffering memory belonging to memory management table with the memory management table disposal route reading the serial data belonging to this memory management table from memory buffer, and the Memory Controller of use the method and memorizer memory devices.
Background technology
Digital still camera, mobile phone and MP3 are very rapid in growth over the years, impel the demand of consumer to Storage Media also sharply to increase.Due to rewritable non-volatile memory (rewritablenon-volatilememory) have that data are non-volatile, low power consumption, volume are little, mechanical structure and the characteristic such as read or write speed is fast, be suitable for use in most portable electronic product, such as mobile phone, personal digital assistant and notebook computer etc.Such as, the solid state hard disc gazed at is enjoyed to be exactly a kind of storage device using flash memory as Storage Media at present.Therefore, flash memory industry has become a ring quite popular in electronic industry in recent years.
Rewritable non-volatile memory module has multiple physical blocks (physicalblock), and each physical blocks has multiple physical page (physicalpage), when wherein writing data in physical blocks, data must be write in order according to the order of physical page.In addition, the physical page being written into data could again for writing data after must first being erased.Particularly, physical blocks is the least unit of erasing, and physical page is the minimum unit of sequencing (also known as write).
Therefore, for promoting operational paradigm, the physical blocks of rewritable non-volatile memory module can be divided into data field, idle district, system region and replacement district by the Memory Controller of flash memory device.
The physical blocks of data field stores the data that host computer system writes.Specifically, the logic access address that host computer system can access by memory management circuitry is converted to the logical page (LPAGE) of logical blocks, and the logical page (LPAGE) of logical blocks is mapped to the physical page of the physical blocks of data field.That is, in the management of flash memory module, the physical blocks of data field is regarded as the physical blocks (such as, having stored the data that host computer system writes) used.In addition, memory management circuitry can use logical blocks-physical blocks mapping table (logicalblock-physicalblockmappingtable) to record the mapping relations of the physical blocks of logical blocks and data field, the physical page of the corresponding physical blocks mapped in order of the logical page (LPAGE) wherein in logical blocks.
The physical blocks in idle district is the physical blocks of rotating in data field.Specifically, the physical blocks of written data just can again for writing data after must being erased, and the physical blocks in idle district is designed to write go back new data to replace the physical blocks of original mapping logic block.Base this, the physical blocks in idle district is empty or spendable block, i.e. no record data or be labeled as invalid data useless.
The physical blocks of system region is in order to register system data.Such as, system data comprises manufacturer about rewritable non-volatile memory module and model, the physical blocks number of rewritable non-volatile memory module, the physical page number etc. of each physical blocks.
The physical blocks replacing district is in order to replacing damaged physical blocks.Specifically, still have normal physical blocks and the damage of the physical blocks of data field if replace in district, memory management circuitry can extract normal physical blocks to change the physical blocks of damage from replacement district.
Therefore, be the management operations in response to complexity, Memory Controller can utilize many memory management table to record the relevant information of physical blocks when managing rewritable non-volatile memory module.Particularly, when flash memory device operates, these memory management table can be temporarily stored in memory buffer, in order to renewal.Such as, this little memory management table comprises logical blocks-physical blocks mapping table, idle district physical blocks table, replaces district's physical blocks table, system region physical blocks table, bad block table, count table etc. of erasing.Along with management logic gets over complexity, Memory Controller needs the memory management table used also to get over increase, thus needs the storage area taking more memory buffer.But the storage area of memory buffer is limited, base this, how also have the memory-aided storage area of efficient utilization, the target that real those skilled in the art for this reason endeavour.
Summary of the invention
The invention provides a kind of memory management table disposal route, Memory Controller and storer, it can reduce the consumption of the storage area of storer effectively.
Exemplary embodiment of the present invention proposes a kind of memory management table disposal route, for being stored in the memory buffer of storer by the multiple logins (entry) belonging to multiple memory management table, wherein each login of these memory management table has at least one invalid bit.This memory management table disposal route is included in this memory buffer the multiple regions marked off for storing these memory management table, one of them of wherein each region these memory management table corresponding.This memory management table disposal route also comprises the invalid bit metamessage recording corresponding each memory management table, and wherein these invalid bit metamessages comprise the information of the invalid bit of each login about these memory management table.This memory management table disposal route also comprises at least one the invalid bit metadata removed according to these invalid bit metamessages in each login, to produce these multiple valid data strings logged in of these memory management table corresponding.This memory management table disposal route also comprises in a corresponding region among these regions of being write by each valid data string in so far memory buffer.
In one embodiment of this invention, above-mentioned memory management table comprises first memory admin table and second memory admin table, and the step wherein dividing these regions being used for these memory management table in this memory buffer comprises: in this memory buffer, divide a corresponding first area of this first memory admin table and a second area of this second memory admin table corresponding.
In one embodiment of this invention, the step of the invalid bit metamessage of the corresponding each memory management table of above-mentioned record comprises: the first invalid bit metamessage of record this first memory admin table corresponding and the second invalid bit metamessage of record this second memory admin table corresponding, and wherein this first invalid bit metamessage comprises information about at least one the first invalid bit of each login of this first memory admin table and this second invalid bit metamessage comprises the information of at least one the second invalid bit about each login of this second memory admin table.
In one embodiment of this invention, above-mentioned at least one invalid bit metadata removed according to these invalid bit metamessages in each login, comprise with the step of these the valid data strings logged in producing these memory management table corresponding: according to the first invalid bit metamessage of this first memory admin table corresponding, remove the invalid bit metadata belonged in multiple logins of this first memory admin table, to produce these multiple valid data strings logged in of this first memory admin table corresponding; And according to the second invalid bit metamessage of this second memory admin table corresponding, remove the invalid bit metadata belonged in multiple logins of this second memory admin table, to produce these multiple valid data strings logged in of this second memory admin table corresponding.
In one embodiment of this invention, the step in the corresponding region in above-mentioned these regions write by each valid data string in so far memory buffer comprises: these valid data strings logged in of this first memory admin table corresponding are write so far first area and these the valid data strings logged in by this first memory admin table corresponding and write so far second area.
In one embodiment of this invention, above-mentioned memory management table disposal route also comprises: these these valid data strings logged in of these memory management table corresponding are read in these regions from then in memory buffer; And these valid data strings read in these regions in from then on memory buffer are reverted to according to these invalid bit metamessages of these memory management table these that belong to these memory management table and log in.
Exemplary embodiment of the present invention proposes a kind of Memory Controller, in order to manage rewritable non-volatile memory module.This Memory Controller comprises memory management circuitry, host interface, memory interface, memory buffer and temporal data treatment circuit.Host interface is coupled to host computer system.Memory interface is coupled to rewritable non-volatile memory module.Memory management circuitry is coupled to host interface and memory interface.Memory buffer is in order to temporal data.Temporal data treatment circuit is coupled to memory management circuitry, and for being stored in the memory buffer of storer by the multiple logins belonging to multiple memory management table, wherein each login of these memory management table has at least one invalid bit.At this, temporal data treatment circuit divides the multiple regions for storing these memory management table in this memory buffer, one of them of wherein each region these memory management table corresponding.In addition, the invalid bit metamessage of the corresponding each memory management table of temporal data treatment circuit record, wherein these invalid bit metamessages comprise the information of the invalid bit of each login about these memory management table.Moreover, temporal data treatment circuit can remove at least one the invalid bit metadata in each login according to these invalid bit metamessages, to produce these multiple valid data strings logged in of these memory management table corresponding, and each valid data string is write in a corresponding region among these regions in so far memory buffer.
In other words, the Memory Controller that the present invention proposes, in order to manage a rewritable non-volatile memory module, this Memory Controller comprises:
One host interface, in order to be coupled to a host computer system; One memory interface, is coupled to this rewritable non-volatile memory module; One memory management circuitry, is coupled to this host interface and this memory interface; One memory buffer, is coupled to this memory management circuitry and in order to temporal data; and a temporal data treatment circuit, be coupled to this memory buffer and this memory management circuitry, and for receiving the multiple logins belonging to multiple memory management table from this memory management circuitry, wherein each those login of those memory management table have at least one invalid bit, wherein this temporal data treatment circuit divides the multiple regions for storing those memory management table in this memory buffer, one of them of wherein each those regions those memory management table corresponding, a wherein invalid bit metamessage of this temporal data treatment circuit record each those memory management table corresponding, wherein those invalid bit metamessages comprise the information of each those these at least one invalid bit logged in about those memory management table, wherein this temporal data treatment circuit according to those invalid bit metamessages remove each those log at least one invalid bit metadata to produce those multiple valid data strings logged in of those memory management table corresponding, and in a corresponding region among those regions each those valid data string being write in this memory buffer.
In one embodiment of this invention, above-mentioned memory management table comprises first memory admin table and second memory admin table, and wherein above-mentioned temporal data treatment circuit divides the corresponding first area of this first memory admin table and the second area of this second memory admin table corresponding in this memory buffer.
In one embodiment of this invention, first invalid bit metamessage of above-mentioned temporal data treatment circuit record this first memory admin table corresponding and the second invalid bit metamessage of record this second memory admin table corresponding, wherein this first invalid bit metamessage comprises information about at least one the first invalid bit of each login of this first memory admin table and the second invalid bit metamessage comprises the information of at least one the second invalid bit about each login of this second memory admin table.
In one embodiment of this invention, above-mentioned temporal data treatment circuit can according to this first invalid bit metamessage of this first memory admin table corresponding, remove the invalid bit metadata belonged in multiple logins of this first memory admin table, to produce these multiple valid data strings logged in of these first memory admin tables corresponding.In addition, above-mentioned temporal data treatment circuit can according to this second invalid bit metamessage of this second memory admin table corresponding, remove the invalid bit metadata belonged in multiple logins of this second memory admin table, to produce these multiple valid data strings logged in of these second memory admin tables corresponding.
In one embodiment of this invention, these these valid data strings logged in of these first memory admin tables corresponding are write so far first area by above-mentioned temporal data treatment circuit, and these these valid data strings logged in of these first memory admin tables corresponding are write so far second area.
In one embodiment of this invention, above-mentioned temporal data treatment circuit also reads these these valid data strings logged in of these memory management table corresponding in order to these regions in from then on memory buffer, and these valid data strings read in these regions in from then on memory buffer is reverted to according to these invalid bit metamessages of these memory management table these that belong to these memory management table and log in.
The present invention proposes a kind of memorizer memory devices, and this memorizer memory devices comprises connector, rewritable non-volatile memory module and Memory Controller.Connector is coupled to host computer system.Rewritable non-volatile memory module is in order to storage data.Memory Controller is coupled to connector and rewritable non-volatile memory module, and comprises memory management circuitry, host interface, memory interface, memory buffer and temporal data treatment circuit.Host interface is coupled to host computer system.Memory interface is coupled to rewritable non-volatile memory module.Memory management circuitry is coupled to this host interface and memory interface.Memory buffer is in order to temporal data.Temporal data treatment circuit, couple so far memory management circuitry, and for being stored in the memory buffer of memorizer memory devices by the multiple logins belonging to multiple memory management table, wherein each login of these memory management table has at least one invalid bit.At this, temporal data treatment circuit divides and is used for multiple regions of these memory management table in this memory buffer, one of them of wherein each region these memory management table corresponding.In addition, the invalid bit metamessage of the corresponding each memory management table of temporal data treatment circuit record, wherein these invalid bit metamessages comprise the information of the invalid bit of each login about these memory management table.Moreover, temporal data treatment circuit can remove at least one the invalid bit metadata in each login according to these invalid bit metamessages, to produce these multiple valid data strings logged in of these memory management table corresponding, and each valid data string is write in a corresponding region among these regions in so far memory buffer.
The present invention separately proposes a kind of memory management table disposal route, wherein this memory management table has many logins (entry), and respectively this login has at least one invalid bit, this memory management table disposal route comprises: in a storer, divide a presumptive area, for storing this memory management table; Record an invalid bit metamessage of this memory management table, wherein this invalid bit metamessage comprises the information of each those these at least one invalid bit logged in about this memory management table; Confirm receive this memory management table those log at least one of them; Remove those according to this invalid bit metamessage to log at least one of them at least one invalid bit metadata and log at least one of them valid data string to produce those that belong to this memory management table; And this valid data string is write to this presumptive area.
Based on above-mentioned, invalid bit metadata wherein can remove by memory management table disposal route provided by the present invention, Memory Controller and memorizer memory devices before the serial data of the login belonging to memory management table is write to memory buffer, and after read serial data from memory buffer, previous removed invalid bit is filled, the consumption of the storage area of memory buffer can be saved by this, with the service efficiency of effective Promoting Layered Buffer storer.
For above-mentioned feature and advantage of the present invention can also be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the data processing method according to exemplary embodiment of the present invention.
Fig. 2 A is host computer system according to exemplary embodiment of the present invention and memorizer memory devices.
Fig. 2 B is the schematic diagram of computer, input/output device and memorizer memory devices according to exemplary embodiment of the present invention.
Fig. 2 C is the schematic diagram of host computer system according to exemplary embodiment of the present invention and memorizer memory devices.
Fig. 3 is the schematic block diagram of the memorizer memory devices according to the present invention one exemplary embodiment.
Fig. 4 is the schematic block diagram of the Memory Controller according to the present invention one exemplary embodiment.
Fig. 5 and Fig. 6 is the schematic diagram managing the physical blocks of rewritable non-volatile memory module according to the present invention one exemplary embodiment.
Fig. 7 is the memory management table according to exemplary embodiment of the present invention and the schematic diagram in corresponding memory buffer region.
Fig. 8 is the schematic diagram of the serial data of process memory management table according to exemplary embodiment of the present invention.
Fig. 9 is the process flow diagram of serial data to memory buffer that write according to exemplary embodiment of the present invention belongs to the login of memory management table.
Figure 10 is that the reading from memory buffer according to exemplary embodiment of the present invention belongs to the process flow diagram of the serial data of the login of memory management table.
Main element symbol description:
S1, S3, S5, S7: the step of data processing method
1000: host computer system
1100: computer
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: Portable disk
1214: memory card
1216: solid state hard disc
1310: digital still camera
1312:SD card
1314:MMC card
1316: memory stick
1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: connector
104: Memory Controller
106: rewritable non-volatile memory module
202: memory management circuitry
204: host interface
206: memory interface
208: temporal data treatment circuit
210: memory buffer
212: electric power management circuit
214: bug check and correcting circuit
310 (0)-310 (R): physical blocks
502: data field
504: idle district
506: system region
508: replace district
510 (0)-510 (H): logical blocks
600: first memory admin table
601-602: log in
610: second memory admin table
611-612: log in
630: first area
640: second area
803: valid data string
S901, S903, S905, S907, S909: the step of serial data to memory buffer writing memory management table
S1001, S1003, S1005, S1007, S1009, S1011: the step reading the serial data of memory management table from memory buffer
Embodiment
In order to can the service efficiency of Promoting Layered Buffer storer effectively, the present invention proposes the data processing method of the storage area that can reduce needed for storing memory admin table.As shown in Figure 1, in this data processing method, in memory buffer, multiple region can be divided, for different memory management table (S1), one of them of wherein each region one of them memory management table corresponding.In addition, in notebook data disposal route, the invalid bit metamessage of each memory management table corresponding can be recorded (S3), and wherein invalid bit metamessage comprises the information of each at least one invalid bit logged in about memory management table.Moreover, in notebook data disposal route, belong to invalid bit metadata in the login of memory management table and can be removed the valid data string (5) of the login producing correspond to memories admin table according to invalid bit metamessage and in this little valid data string can be written in memory buffer corresponding region (S7).In order to also the present invention can be well understood to, be described with several exemplary embodiment below.
Generally speaking, memorizer memory devices (also known as, memory storage system) comprises rewritable non-volatile memory module and controller (also known as, control circuit).Usual memorizer memory devices uses together with host computer system, data can be write to memorizer memory devices or read data from memorizer memory devices to make host computer system.
Fig. 2 A is host computer system according to exemplary embodiment of the present invention and memorizer memory devices.
Please refer to Fig. 2 A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (randomaccessmemory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2 B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2 B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is through data transmission interface 1110 and couples with other elements of host computer system 1000.Data can be write to memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memorizer memory devices 100.Such as, memorizer memory devices 100 can be the rewritable non-volatile memory storage devices such as Portable disk 1212, memory card 1214 or solid state hard disc (SolidStateDrive, SSD) 1216 as shown in Figure 2 B.
Generally speaking, host computer system 1000 can substantially for coordinating any system with storage data with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but in another exemplary embodiment of the present invention, host computer system 1000 can be the systems such as digital still camera, video camera, communicator, audio player or video player.Such as, when host computer system is digital still camera (video camera) 1310, rewritable non-volatile memory storage device is then its SD card 1312 used, mmc card 1314, memory stick (memorystick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 2 C).Embedded storage device 1320 comprises embedded multi-media card (EmbeddedMMC, eMMC).It is worth mentioning that, embedded multi-media card is directly coupled on the substrate of host computer system.
Fig. 3 is the schematic block diagram of the memorizer memory devices according to the present invention one exemplary embodiment.
Please refer to Fig. 3, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and rewritable non-volatile memory module 106.
In this exemplary embodiment, connector 102 is compatible to advanced annex (SerialAdvancedTechnologyAttachment, the SATA) standard of sequence.But, it must be appreciated, the present invention is not limited thereto, connector 102 can also be meet Institute of Electrical and Electric Engineers (InstituteofElectricalandElectronicEngineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (PeripheralComponentInterconnectExpress, PCIExpress) standard, universal serial bus (UniversalSerialBus, USB) standard, safety digit (SecureDigital, SD) interface standard, memory stick (MemoryStick, MS) interface standard, Multi Media Card (MultiMediaCard, MMC) interface standard, compact flash (CompactFlash, CF) interface standard, integrated driving electrical interface (IntegratedDeviceElectronics, IDE) standard or other standards be applicable to.
Memory Controller 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in rewritable non-volatile memory module 106 data write, read and the running such as to erase.
Rewritable non-volatile memory module 106 is coupled to Memory Controller 104, and have the data that multiple physical blocks writes to store host computer system 1000.In this exemplary embodiment, each physical blocks has several physical page respectively, and the physical page wherein belonging to same physical blocks can be written independently and side by side be erased.Such as, each physical blocks is made up of 128 physical page.But it must be appreciated, the present invention is not limited thereto, each physical blocks can be made up of 64 physical page, 256 physical page or other any physical page.
In more detail, physical blocks is the least unit of erasing.That is, each physical blocks contain minimal amount in the lump by the memory cell of erasing.Physical page is the minimum unit of sequencing.That is physical page is the minimum unit read and write data.But it must be appreciated, in another exemplary embodiment of the present invention, the least unit of write data can also be sector (Sector) or other sizes.Each physical page generally includes data bit element district and redundancy bit district.Data bit element district is in order to store the data of user, and redundancy bit district is in order to the data (such as, bug check and correcting code) of stocking system.
In this exemplary embodiment, rewritable non-volatile memory module 106 is multistage memory cell (MultiLevelCell, MLC) NAND quick-flash memory module.But, the present invention is not limited thereto, rewritable non-volatile memory module 106 also single-order memory cell (SingleLevelCell, SLC) NAND quick-flash memory module, other flash memory module or other there is the memory module of identical characteristics.
Fig. 4 is the schematic block diagram of the Memory Controller according to the present invention one exemplary embodiment.
Please refer to Fig. 4, Memory Controller 104 comprises memory management circuitry 202, host interface 204, memory interface 206, temporal data treatment circuit 208 and memory buffer 210.
Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has multiple steering order, and when memorizer memory devices 100 operates, these steering orders can be performed to carry out data write, read and the running such as to erase.
In this exemplary embodiment, the steering order of memory management circuitry 202 carrys out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessing unit (not shown) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memorizer memory devices 100 operates, the method for writing data that this little steering order can perform according to exemplary embodiment of the present invention by microprocessing unit.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also procedure code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of rewritable non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessing unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has driving code section, and when Memory Controller 104 is enabled, microprocessing unit first can perform this and drive code section the steering order be stored in rewritable non-volatile memory module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessing unit can operate this little steering order to perform the method for writing data of exemplary embodiment of the present invention.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 a hardware pattern can also carry out implementation.
Host interface 204 is coupled to connector 102 and memory management circuitry 202, and in order to receive and to identify the instruction that host computer system 1000 transmits and data.That is, the instruction that transmits of host computer system 1000 and data can through host interface 204 to be sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 can also be compatible to PATA standard, IEEE1394 standard, PCIExpress standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 206 is coupled to memory management circuitry 202, and in order to access rewritable non-volatile memory module 106.That is, the data for writing to rewritable non-volatile memory module 106 can be converted to the receptible form of rewritable non-volatile memory module 106 via memory interface 206.
Temporal data treatment circuit 208 is coupled to memory buffer 210 and memory management circuitry 202.At this, temporal data treatment circuit 208 is in order to be stored to memory buffer 210 and in order to read the data of memory management circuitry 202 for reading from memory buffer 210 by memory management circuitry 202 for keeping in memory buffer 210.
Memory buffer 210 is coupled to memory management circuitry 202, and come from the data and instruction of host computer system 1000 in order to temporary or come from the data of rewritable non-volatile memory module 106.Particularly, the memory management table used during in order to manage rewritable non-volatile memory module 106 (such as, logical blocks-physical blocks mapping table) can be kept in in memory buffer 210 by temporal data treatment circuit 208.
In the present invention one exemplary embodiment, Memory Controller 104 also comprises electric power management circuit 212.Electric power management circuit 212 is coupled to memory management circuitry 202, and in order to the power supply of control store storage device 100.
In the present invention one exemplary embodiment, Memory Controller 104 also comprises bug check and correcting circuit 214.Bug check and correcting circuit 214 are coupled to memory management circuitry 202, and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 214 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (ErrorCheckingandCorrectingCode, ECCCode), and memory management circuitry 202 data of this write instruction corresponding can be write in rewritable non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuitry 202 reads data from rewritable non-volatile memory module 106, and bug check and correcting circuit 214 can according to this bug check and correcting code to read data execution error inspection and correction programs simultaneously.
Fig. 5 and Fig. 6 is the schematic diagram managing the physical blocks of rewritable non-volatile memory module according to the present invention one exemplary embodiment.
Please refer to Fig. 5, rewritable non-volatile memory module 106 has physical blocks 310 (0)-310 (R), and physical blocks 310 (0)-310-(R) logically can be grouped into data field 502, idle district 504, system region 506 and replace district 508 by the memory management circuitry 202 of Memory Controller 104.
Belonging to data field 502 in logic with the physical blocks in idle district 504 is in order to store the data coming from host computer system 1000.Specifically, the physical blocks of data field 502 is regarded as the physical blocks of storage data, and the physical blocks in idle district 504 is the physical blocks in order to replacement data district 502.That is, when receiving the data that write instruction writes with wish from host computer system 1000, memory management circuitry 202 can extract physical blocks from idle district 504, and data is write in extracted physical blocks, with the physical blocks in replacement data district 502.
The physical blocks belonging to system region 506 is in logic in order to register system data.Such as, system data comprises manufacturer about rewritable non-volatile memory module and model, the physical blocks number of rewritable non-volatile memory module, the physical page number etc. of each physical blocks.
Belonging to the physical blocks replacing district 508 is in logic in order to replacing damaged physical blocks.Specifically, still have normal physical blocks and the damage of the physical blocks of data field 502 if replace in district 508, memory management circuitry 202 can extract normal physical blocks to change the physical blocks of damage from replacement district 508.
It is worth mentioning that, in this exemplary embodiment, memory management circuitry 202 manages in units of each physical blocks.But the present invention is not limited thereto, in another exemplary embodiment, physical blocks also can be grouped into multiple solid element by memory management circuitry 202, and manages in units of solid element.Such as, each solid element can be made up of at least one physical blocks in same storer submodule or different memory submodule.
Particularly, data field 502, idle district 504, system region 506 can be different according to different storer specifications with the quantity of the physical blocks in replacement district 508.In addition, it must be appreciated, during the running of memorizer memory devices 100, physical blocks is associated to data field 502, idle district 504, system region 506 also can dynamically change with the grouping relation replacing district 508.Such as, when the physical blocks in idle district 504 is damaged and is substituted the physical blocks replacement in district, then the physical blocks originally replacing district 508 can be associated to idle district 504.
Please refer to Fig. 6, as mentioned above, data field 502 is data that the mode of rotating writes to store host computer system 1000 with the physical blocks in idle district 504.In this exemplary embodiment, memory management circuitry 202 meeting configuration logic block 510 (0)-510 (H) is to map the physical blocks carrying out storage data in the above-mentioned mode of rotating, and the logical page (LPAGE) of logical blocks 510 (0)-510 (H) is mapped to the logic access address that host computer system 1000 accesses, carry out access data in order to host computer system 1000.
Such as, logical blocks 510 (0)-510 (H) initially can be mapped to the physical blocks of data field 502 by memory management circuitry 202.Specifically, when memorizer memory devices 100 is done manufacture, logical blocks 510 (0)-510 (H) maps to the physical blocks 310 (0)-310 (D) of data field 502 respectively.That is, a physical blocks in a logical blocks meeting mapping (enum) data district 502.At this, memory management circuitry 202 can set up logical blocks-physical blocks mapping table, to record the mapping relations between logical blocks and physical blocks.That is, host computer system 1000 can be converted to the logical page (LPAGE) of corresponding logical blocks by memory management circuitry 202 for the logic access address accessed, thus through query logic block-physical blocks mapping table access data in entity address.
In summary, the memory management circuitry 202 of Memory Controller 104 can use many memory management table when managing rewritable non-volatile memory module 106, such as, in order to record the logical blocks-physical blocks mapping table of the mapping relations between logical blocks 510 (0)-510 (H) and the physical blocks of data field 502, in order to record the idle district physical blocks table of the physical blocks in idle district 504, the replacement district physical blocks table of the physical blocks in district 508 is replaced in order to record, in order to the system region physical blocks table of the physical blocks in register system district 506, the managing damage block of physical blocks is damaged in order to record, in order to record the frequency table etc. of erasing of the number of times of erasing of each physical blocks.
In general, before memorizer memory devices 100 shuts down, up-to-date memory management table can be restored to rewritable non-volatile memory module 106 by memory management circuitry 202.And, when memorizer memory devices 100 operates, memory management circuitry 202 can be loaded into this little memory management table from rewritable non-volatile memory module 106 and these memory management table can be kept in in memory buffer 210 by temporal data treatment circuit 208, is beneficial to be updated rapidly.
It should be noted that each memory management table logs in (entry) by multiple and formed, and each login comprises multiple bit composition.Specifically, the microprocessing unit of memory management circuitry 202 be with fixing access size by data temporary storage to memory buffer 210 with from memory buffer 210, read data.Such as, data are for unit accesses with 1 bit group (that is, 8 bits).Therefore, each login can be designed to the size of fixing.But, because the size of various memory management table may be different, therefore, memory management circuitry 202 only can use the part bit in login to store effective data and to be filled up with invalid bit metadata (such as, ' 0 ') by other bits.At this, in each login, the bit of non-storage valid data is called invalid bit.Therefore, in this exemplary embodiment, for same memory management table, each login can comprise at least one invalid bit and each login has identical data aspect.That is the specific fixing bit in all logins of a memory management table is all invalid bit.
Fig. 7 is the memory management table according to exemplary embodiment of the present invention and the schematic diagram in corresponding memory buffer region.
Please refer to Fig. 7, at this, suppose that memory management circuitry 202 uses first memory admin table 600 (such as, logical blocks-physical blocks mapping table) manage rewritable non-volatile memory module 106 with second memory admin table 610 (such as, bad block table) and first memory admin table 600 and second memory admin table 610 can be stored in the system region 506 of rewritable non-volatile memory module 106.It must be appreciated, in another exemplary embodiment of the present invention, first memory admin table 600 and second memory admin table 610 also can be stored in the data field 502 of rewritable non-volatile memory module 106.In addition, although be explain with two memory management table in this exemplary embodiment, the present invention is not limited thereto.
First memory admin table 600 and second memory admin table 610 comprise multiple login respectively, and each login is made up of multiple bit (bit).Memory management circuitry 202 can at each bit identifying recording layer.Such as, first memory admin table 600 comprises login 601 and comprises login 611 and login 612 with login 602 and second memory admin table 610.Particularly, all logins in the middle of first memory admin table 600 all have identical bit number, and comprise invalid bit on identical position.Such as, log in 601, with login 602, all there are 8 bits, and its 0th, 4 and 6 bit is invalid bit (as shown in the hatched example areas in Fig. 7).In addition, log in 611, with login 612, all there are 8 bits, and its 1st, 3,4 and 6 bit is all invalid bit (as shown in the hatched example areas in Fig. 7).It must be appreciated, although in this exemplary embodiment, each memory management table comprises two logins, the present invention is not limited thereto, and in another exemplary embodiment of the present invention, logs in more than each memory management table can comprise.In addition, in exemplary embodiment of the present invention, each size logged in is 8 bits (that is, 1 bit group), but the present invention is not limited thereto.Such as, a size logged in can be 2 bit groups, 4 bit groups or other sizes.
In this exemplary embodiment, temporal data treatment circuit 208 can mark off corresponding first area 630 and second area 640 for first memory admin table 600 and second memory admin table 610 respectively in memory buffer 210, and records the invalid bit metamessage of corresponding first memory admin table 600 and the invalid bit metamessage of second memory admin table 610 respectively.At this, invalid bit metamessage is that in the login in order to record storage admin table, which bit is invalid bit.
Particularly, when memory management circuitry 202 is for being loaded into memory buffer 210 by first memory admin table 600, temporal data treatment circuit 208 can will belong in the first area 630 of login write buffering memory 210 of first memory admin table 600.Similarly, when memory management circuitry 202 is for being loaded into memory buffer 210 by second memory admin table 610, temporal data treatment circuit 208 can will belong in the second area 640 of login write buffering memory 210 of second memory admin table 610.That is, first area 630 only in order to store belong to the login of first memory admin table 600 and second area 640 only in order to store the login belonging to second memory admin table 610.It is worth mentioning that, be in memory buffer 210, divide two regions carry out storing memory admin table respectively in this exemplary embodiment.But, it must be appreciated, the present invention is not limited thereto, in another exemplary embodiment of the present invention, when memory management table increases, more region can be divided out, or, when only there being a memory management table, 1 region also only can be divided to store this memory management table.
It is worth mentioning that, by belonging in the process of login write buffering note body of memory management table, if by invalid bit intactly write buffering memory, unnecessary waste can be caused to the storage area of limited memory buffer 210.In this exemplary embodiment, temporal data treatment circuit 208 first can remove the invalid bit metadata in login, again the login removed after invalid bit metadata (hereinafter referred to as valid data string) is stored in memory buffer 210, thus, the waste of the storage area of memory buffer is avoided.
Specifically, temporal data treatment circuit 208 can identify for the serial data of keeping in memory buffer 210 be belong to which memory management table, and the invalid bit metamessage corresponding to this memory management table removes the invalid bit metadata in this serial data.Afterwards, temporal data treatment circuit 208 can in the valid data string write buffering memory 210 obtained after removing invalid bit metadata.
Otherwise, when reading data from memory buffer 210, temporal data treatment circuit 208 can first identify the serial data read belongs to which memory management table, and read serial data is reverted to original login (that is, rejoining invalid bit metadata in read serial data) by the invalid bit metamessage corresponding to this memory management table.Afterwards, temporal data treatment circuit 208 can send the login after recovery to memory management circuitry 202.
Fig. 8 is the schematic diagram of the serial data of process memory management table according to exemplary embodiment of the present invention.At this, be only described to access the login 601 belonging to first memory admin table 600 in memory buffer 210.But it must be appreciated, this treatment mechanism is also applicable to access in memory buffer 210 and belongs to other logins of first memory admin table 600 or belong to the login of other memory management table.
Please refer to Fig. 8, when for the serial data of the login 601 belonging to first memory admin table 600 is stored to memory buffer 210, memory management circuitry 202 can write through temporal data treatment circuit 208 pairs of memory buffer 210.
In detail, temporal data treatment circuit 208 to remove in login the 0th, 4 according to the invalid bit metamessage of corresponding first memory admin table 600 and produces the valid data string 803 of the login 601 of corresponding first memory admin table 600 with the data (that is, invalid bit metadata) in 6 bits and be stored in the first area 630 of memory buffer 210 by valid data string 803.
In addition, when for reading valid data string 803 from memory buffer 210, memory management circuitry 202 can read through temporal data treatment circuit 208 pairs of memory buffer 210.
In detail, temporal data treatment circuit 208 can read valid data string 803 and in the valid data string 803 read, rejoin corresponding invalid bit metadata, to recover the login 601 belonging to first memory admin table 600 according to the invalid bit metamessage of corresponding first memory admin table 600.Then, temporal data treatment circuit 208 can send the login of recovery to memory management circuitry 202.
Based on above-mentioned, by temporal data treatment circuit 208, the invalid bit metadata in serial data is removed, effectively can reduce the storage area in order to storing memory admin table in memory buffer 210.Such as, in this exemplary embodiment, each of first memory admin table 600 logs on as 8 bits and comprises 3 invalid bits, and therefore, the storage area in order to store first memory admin table 600 in memory buffer 210 can save 37.5%.
Fig. 9 is the process flow diagram of serial data to memory buffer that write according to exemplary embodiment of the present invention belongs to the login of memory management table.
Please refer to Fig. 9, first, in step S901, receive from memory management circuitry 202 and log in and judge that the login received belongs to first memory admin table 600 or second memory admin table 610.
If the login received from memory management circuitry 202 is when belonging to first memory admin table 600, in step S903, temporal data treatment circuit 208 can according to the invalid bit metamessage of corresponding first memory admin table 600 remove this log in invalid data bit to produce valid data string, and, in step S905, valid data string can be stored in the first area 630 of corresponding first memory admin table 600 by temporal data treatment circuit 208.
If the login received from memory management circuitry 202 is when belonging to second memory admin table 610, in step s 907, temporal data treatment circuit 208 can according to the invalid bit metamessage of corresponding second memory admin table 610 remove this log in invalid data bit to produce valid data string, and, in step S909, valid data string can be stored in the second area 640 of corresponding second memory admin table 600 by temporal data treatment circuit 208.
Figure 10 is that the reading from memory buffer according to exemplary embodiment of the present invention belongs to the process flow diagram of the serial data of the login of memory management table.
Please refer to Figure 10, first, in step S1001, temporal data treatment circuit 208 can judge that memory management circuitry 202 is belong to first memory admin table 600 or second memory admin table 610 for the serial data read.
If memory management circuitry 202 is when belonging to first memory admin table 600 for the login of reading, in the step s 1003, temporal data treatment circuit 208 can read serial data from the first area 630 of memory buffer 210, and, in step S1005, read serial data can be reverted to original login according to the invalid bit metamessage of corresponding first memory admin table 600 by temporal data treatment circuit 208.Afterwards, in step S1007, temporal data treatment circuit 208 can transmit recovered login to memory management circuitry 202.
If memory management circuitry 202 is when belonging to second memory admin table 610 for the login of reading, in step S1009, temporal data treatment circuit 208 can read serial data from the second area 640 of memory buffer 210, and, in step S1011, read serial data can be reverted to original login according to the invalid bit metamessage of corresponding second memory admin table 610 by temporal data treatment circuit 208.Afterwards, step S1007 can be performed.
It is worth mentioning that, in this exemplary embodiment, be described for storing memory admin table in memory buffer, but, the present invention is not limited thereto, in another exemplary embodiment of the present invention, can also same way storing memory admin table in other storeies (such as, flash memory etc.).
In sum, by when belonging to the login write buffering memory of memory management table, the memory management table disposal route of exemplary embodiment of the present invention, Memory Controller and memorizer memory devices can identify which memory management table the login for writing storer belongs to, and remove the invalid bit metadata that this serial data comprises according to this, finally write again in the specific region of storer.Base this, the memory management table disposal route of exemplary embodiment of the present invention, Memory Controller and memorizer memory devices can save the storage area needing the storer consumed effectively.
Although the present invention discloses as above with embodiment, the those of ordinary skill in any art, does not depart from the spirit and scope of the present invention, when doing a little change and retouching, and does not depart from the spirit and scope of the present invention.
Claims (19)
1. a memory management table disposal route, for the multiple logins (entry) belonging to multiple memory management table are stored in a memory buffer of a memorizer memory devices, wherein each those login of those memory management table have at least one invalid bit, and this memory management table disposal route comprises:
The multiple regions for storing those memory management table are divided, one of them of wherein each those regions those memory management table corresponding in this memory buffer;
One invalid bit metamessage of record each those memory management table corresponding, wherein those invalid bit metamessages comprise the information of each those these at least one invalid bit logged in about those memory management table;
According to those invalid bit metamessages remove each those log at least one invalid bit metadata to produce those multiple valid data strings logged in of those memory management table corresponding; And
Each those valid data string is write in the corresponding region among those regions in this memory buffer.
2. memory management table disposal route according to claim 1, wherein those memory management table comprise a first memory admin table and a second memory admin table,
In this memory buffer, wherein divide the step in those regions being used for those memory management table comprise: divide in this memory buffer to should first memory admin table a first area with to should a second area of second memory admin table.
3. memory management table disposal route according to claim 2, wherein the step of this invalid bit metamessage of record each those memory management table corresponding comprises:
Record should one first invalid bit metamessage of first memory admin table, wherein this first invalid bit metamessage comprises the information of each those at least one first invalid bit logged in about this first memory admin table; And
Record should one second invalid bit metamessage of second memory admin table, wherein this second invalid bit metamessage comprises the information of each those at least one second invalid bit logged in about this second memory admin table.
4. memory management table disposal route according to claim 3, this at least one invalid bit metadata wherein removed in each those login according to those invalid bit metamessages comprises with the step of those those valid data strings logged in producing those memory management table corresponding:
According to should this first invalid bit metamessage of first memory admin table, remove and belong to multiple invalid bit metadata in multiple logins of this first memory admin table to produce should those multiple valid data strings logged in of first memory admin table; And
According to should this second invalid bit metamessage of second memory admin table, remove and belong to multiple invalid bit metadata in multiple logins of this second memory admin table to produce should those multiple valid data strings logged in of second memory admin table.
5. memory management table disposal route according to claim 4, the step wherein write to by each those valid data string in this corresponding region among those regions in this memory buffer comprises:
By to should first memory admin table those log in those valid data strings write to this first area; And
By to should second memory admin table those log in those valid data strings write to this second area.
6. memory management table disposal route according to claim 1, also comprises:
Those those valid data strings logged in of those memory management table corresponding are read from those regions this memory buffer; And
Those valid data strings read from those regions in this memory buffer are reverted to those logins belonging to those memory management table by those invalid bit metamessages according to those memory management table.
7. a Memory Controller, in order to manage a rewritable non-volatile memory module, this Memory Controller comprises:
One host interface, in order to be coupled to a host computer system;
One memory interface, is coupled to this rewritable non-volatile memory module;
One memory management circuitry, is coupled to this host interface and this memory interface;
One memory buffer, is coupled to this memory management circuitry and in order to temporal data; And
One temporal data treatment circuit, be coupled to this memory buffer and this memory management circuitry, and for receiving the multiple logins belonging to multiple memory management table from this memory management circuitry, wherein each those login of those memory management table have at least one invalid bit
Wherein this temporal data treatment circuit divides the multiple regions for storing those memory management table in this memory buffer, one of them of wherein each those regions those memory management table corresponding,
A wherein invalid bit metamessage of this temporal data treatment circuit record each those memory management table corresponding, wherein those invalid bit metamessages comprise the information of each those these at least one invalid bit logged in about those memory management table,
Wherein this temporal data treatment circuit according to those invalid bit metamessages remove each those log at least one invalid bit metadata to produce those multiple valid data strings logged in of those memory management table corresponding, and each those valid data string to be write in the corresponding region among those regions in this memory buffer.
8. Memory Controller according to claim 7, wherein those memory management table comprise a first memory admin table and a second memory admin table,
Wherein this temporal data treatment circuit divide in this memory buffer to should first memory admin table a first area with to should a second area of second memory admin table.
9. Memory Controller according to claim 8, wherein this temporal data treatment circuit record to should one first invalid bit metamessage of first memory admin table and record to should one second invalid bit metamessage of second memory admin table, wherein this first invalid bit metamessage comprises information about each those at least one first invalid bit logged in of this first memory admin table and this second invalid bit metamessage comprises the information of each those at least one second invalid bit logged in about this second memory admin table.
10. Memory Controller according to claim 9,
Wherein this temporal data treatment circuit is according to should this first invalid bit metamessage of first memory admin table, remove and belong to multiple invalid bit metadata in multiple logins of this first memory admin table to produce should those multiple valid data strings logged in of first memory admin table
Wherein this temporal data treatment circuit is according to should this second invalid bit metamessage of second memory admin table, removes and belongs to multiple invalid bit metadata in multiple logins of this second memory admin table to produce should those multiple valid data strings logged in of second memory admin table.
11. Memory Controllers according to claim 10, wherein this temporal data treatment circuit by should first memory admin table those log in those valid data strings write to this first area and by should second memory admin table those log in those valid data strings write to this second area.
12. Memory Controllers according to claim 7, wherein this temporal data treatment circuit is also in order to read those those valid data strings logged in of those memory management table corresponding from those regions in this memory buffer, and those valid data strings read from those regions in this memory buffer is reverted to according to those invalid bit metamessages of those memory management table those logins belonging to those memory management table.
13. 1 kinds of memorizer memory devices, comprising:
A connector, is coupled to a host computer system;
One rewritable non-volatile memory module, in order to storage data; And
One Memory Controller, be coupled to this connector and this rewritable non-volatile memory module, wherein this Memory Controller comprises:
One host interface, is coupled to this connector;
One memory interface, is coupled to this rewritable non-volatile memory module;
One memory management circuitry, is coupled to this host interface and this memory interface;
One memory buffer, in order to temporal data; And
One temporal data treatment circuit, is coupled to this memory buffer and this memory management circuitry,
Wherein this temporal data treatment circuit in order to receive the multiple logins belonging to multiple memory management table from this memory management circuitry, and wherein each those login of those memory management table have at least one invalid bit,
Wherein this temporal data treatment circuit divides and is used for multiple regions of those memory management table in this memory buffer, one of them of wherein each those region those memory management table corresponding,
A wherein invalid bit metamessage of this temporal data treatment circuit record each those memory management table corresponding, wherein those invalid bit metamessages comprise the information of each those these at least one invalid bit logged in about those memory management table,
Wherein this temporal data treatment circuit according to those invalid bit metamessages remove each those log at least one invalid bit metadata to produce those multiple valid data strings logged in of those memory management table corresponding and each those valid data string to be write in the corresponding region among those regions in this memory buffer.
14. memorizer memory devices according to claim 13, wherein those memory management table comprise a first memory admin table and a second memory admin table,
Wherein this temporal data treatment circuit divide in this memory buffer to should first memory admin table a first area with to should a second area of second memory admin table.
15. memorizer memory devices according to claim 14, wherein this temporal data treatment circuit record to should one first invalid bit metamessage of first memory admin table and record to should one second invalid bit metamessage of second memory admin table, wherein this first invalid bit metamessage comprises information about each those at least one first invalid bit logged in of this first memory admin table and this second invalid bit metamessage comprises the information of each those at least one second invalid bit logged in about this second memory admin table.
16. memorizer memory devices according to claim 15,
Wherein this temporal data treatment circuit is according to should this first invalid bit metamessage of first memory admin table, remove and belong to multiple invalid bit metadata in multiple logins of this first memory admin table to produce should those multiple valid data strings logged in of first memory admin table
Wherein this temporal data treatment circuit is according to should this second invalid bit metamessage of second memory admin table, removes and belongs to multiple invalid bit metadata in multiple logins of this second memory admin table to produce should those multiple valid data strings logged in of second memory admin table.
17. memorizer memory devices according to claim 16, wherein this temporal data treatment circuit by should first memory admin table those log in those valid data strings write to this first area and by should second memory admin table those log in those valid data strings write to this second area.
18. memorizer memory devices according to claim 13, wherein this temporal data treatment circuit is also in order to read those those valid data strings logged in of those memory management table corresponding from those regions in this memory buffer,
Wherein those valid data strings read from those regions in this memory buffer are reverted to those logins belonging to those memory management table by this temporal data treatment circuit according to those invalid bit metamessages of those memory management table.
19. 1 kinds of memory management table disposal routes, wherein this memory management table has many logins (entry), and respectively this login has at least one invalid bit, and this memory management table disposal route comprises:
A presumptive area is divided, for storing this memory management table in a storer;
Record an invalid bit metamessage of this memory management table, wherein this invalid bit metamessage comprises the information of each those these at least one invalid bit logged in about this memory management table;
Confirm receive this memory management table those log at least one of them;
Remove those according to this invalid bit metamessage to log at least one of them at least one invalid bit metadata and log at least one of them valid data string to produce those that belong to this memory management table; And
This valid data string is write to this presumptive area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110173868.8A CN102841853B (en) | 2011-06-24 | 2011-06-24 | Memory management table disposal route, Memory Controller and memorizer memory devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110173868.8A CN102841853B (en) | 2011-06-24 | 2011-06-24 | Memory management table disposal route, Memory Controller and memorizer memory devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102841853A CN102841853A (en) | 2012-12-26 |
| CN102841853B true CN102841853B (en) | 2016-03-02 |
Family
ID=47369241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110173868.8A Active CN102841853B (en) | 2011-06-24 | 2011-06-24 | Memory management table disposal route, Memory Controller and memorizer memory devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102841853B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104182293B (en) * | 2013-05-22 | 2017-06-30 | 群联电子股份有限公司 | Method for writing data, memory storage apparatus and Memory Controller |
| CN104461935B (en) * | 2014-11-27 | 2018-03-13 | 华为技术有限公司 | A kind of method, apparatus and system for carrying out data storage |
| CN106776376B (en) * | 2015-11-24 | 2019-08-06 | 群联电子股份有限公司 | Buffer storage supervisory method, memorizer control circuit unit and storage device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200941487A (en) * | 2008-03-28 | 2009-10-01 | Phison Electronics Corp | Method and controller for promoting management efficiency of non-volatile memory storage device |
| TW201115335A (en) * | 2009-10-28 | 2011-05-01 | Phison Electronics Corp | Falsh memory storage system and flash memory controller and data processing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4722839B2 (en) * | 2004-05-19 | 2011-07-13 | パナソニック株式会社 | MEMORY CONTROL CIRCUIT, NONVOLATILE MEMORY DEVICE, AND MEMORY CONTROL METHOD |
-
2011
- 2011-06-24 CN CN201110173868.8A patent/CN102841853B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200941487A (en) * | 2008-03-28 | 2009-10-01 | Phison Electronics Corp | Method and controller for promoting management efficiency of non-volatile memory storage device |
| TW201115335A (en) * | 2009-10-28 | 2011-05-01 | Phison Electronics Corp | Falsh memory storage system and flash memory controller and data processing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102841853A (en) | 2012-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI423026B (en) | Data writing method, memory controller and memory storage apparatus | |
| US9037814B2 (en) | Flash memory management method and flash memory controller and storage system using the same | |
| CN102193869B (en) | Memory management and write-in method, memory controller and storage system | |
| CN104699413A (en) | Data management method, memorizer saving device and memorizer control circuit unit | |
| CN102890655B (en) | Memory storage device, memory controller and valid data recognition method thereof | |
| TW201305818A (en) | Data writing method, memory controller and memory storage apparatus | |
| CN103514096A (en) | Data storage method, memory controller and memory storage device | |
| CN102567221B (en) | Data management method, memory controller and memory storage device | |
| US8943264B2 (en) | Data storing method, and memory controller and memory storage apparatus using the same | |
| US8943289B2 (en) | Data moving method for flash memory module, and memory controller and memory storage apparatus using the same | |
| CN103136111A (en) | Data writing method, memorizer controller and memorizer storage device | |
| CN102866861B (en) | Flash memory system, flash controller and method for writing data | |
| CN104252317B (en) | Method for writing data, Memory Controller and memory storage apparatus | |
| CN102999437B (en) | Data-moving method, Memory Controller and memorizer memory devices | |
| CN102841853B (en) | Memory management table disposal route, Memory Controller and memorizer memory devices | |
| US8417909B2 (en) | Block management and data writing method, and flash memory storage system and controller using the same | |
| CN103714008A (en) | Method for memorizing data, memory controller and memorizing device of memory | |
| CN102800357A (en) | Program code loading and accessing methods, memory controller and storage device of memory | |
| TWI464585B (en) | Data storing method, and memory controller and memory storage apparatus using the same | |
| CN102467459B (en) | Data write method, memory controller and memory device | |
| CN104166558B (en) | Firmware code loading method, Memory Controller and memory storage apparatus | |
| CN102467460B (en) | Data management method, memory controller and memory storage device | |
| CN102543184A (en) | Memory storage device, memory controller thereof and data writing method | |
| TWI436209B (en) | Memory management table proceesing method, memory controller and memory storage apparatus | |
| CN102043724B (en) | For the block management method of flash memory, controller and storage system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |