CN102833063B - The implementation method of client traffic Clock Extraction in a kind of OTN network - Google Patents
The implementation method of client traffic Clock Extraction in a kind of OTN network Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
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- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1652—Optical Transport Network [OTN]
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Abstract
The present invention relates to the implementation method of client traffic Clock Extraction in a kind of OTN network, Statisti-cal control is adopted to add plug-in digital frequency synthesizer, the first step, carries out synchronous smoothing processing to the client traffic that OTN network solution frame goes out, makes client traffic data more even under OTN system clock; Second step, statistics and smoother rear data volume and client traffic send data volume, clock adjustment information is controlled in conjunction with FIFO buffer memory redundancy by weighting algorithm, 3rd step, clock adjustment information is converted into the precise frequency adjustment information that plug-in digital frequency synthesizer needs, precisely controls plug-in digital frequency synthesizer and produce business tranmitting data register.Implementation method of the present invention, realizes difficulty little, and it is low to implement cost; Clock Extraction process controls mainly through adding up, and does not rely on buffer memory operating state, safe and reliable; Run into abnormal can filtration in time in statistic processes, can not cause iteration effect during equipment cascading, the clock quality of extraction is better.
Description
Technical field
The present invention relates to optical transport network (OTN, Optical Transport Network) communication technical field, is the implementation method that in a kind of OTN network, client traffic clock (referring to the tranmitting data register of client traffic) extracts specifically.The implementation method that the tranmitting data register espespecially carrying GE, STM16 and OTU1 client traffic in OTN network extracts.
Background technology
In recent years, the business that communication network carries there occurs huge change, and OTN has been main optical transport network technology.At present, domestic and international mainstream carrier pays special attention to development and the application of OTN technology, and the WDM transmission interface of most operator has realized OTN function.OTN concept covers photosphere and electric layer two-tier network, and one of its key technical feature is presented as: multiple client signal encapsulation and transparent transmission.Mapping and the transparent transmission of multiple client signal can be supported, as SDH, ATM, Ethernet etc. based on ITU-T OTN frame structure G.709.For realizing the transparent transmission of OTN carrying client business, the tranmitting data register (be called for short client traffic clock) of client traffic must be extracted when customer side sends business, its clock frequency to carry corresponding client traffic with OTN before business receive clock consistent.
For the extraction of client traffic clock, realize mainly through two schemes at present: FIFO buffer memory control of redundancy adds that high accuracy number phase-locked loop and FIFO buffer memory control of redundancy add plug-in digital frequency synthesizer.
FIFO buffer memory control of redundancy adds that high accuracy number phase-locked loop scheme implementation gets up difficulty greatly, and clock tracing adjustment time delay is long, and high accuracy number phase-locked loop technique is too complicated, realizes high cost.FIFO buffer memory control of redundancy adds in plug-in digital frequency synthesizer scheme and only leans on FIFO buffer status to adjust clock, and it is subject to the restriction of judgement cycle and plug-in digital frequency synthesizer adjustment step-length.As judged, the cycle is short, and buffer memory redundancy error is large, and clock adjustment is frequent, and clock jitter can be caused excessive; Adjustment step-length arranges too small or excessive, and in tracing process, buffer memory is frequent empty or full, and now buffer memory redundancy angle value is unavailable, cannot extract efficient clock adjustment information; When equipment cascading is too much, buffer memory redundancy can cause iteration effect, causes clock jitter excessive.
Summary of the invention
For the defect existed in prior art, the object of the present invention is to provide the implementation method of client traffic Clock Extraction in a kind of OTN network, mainly be positioned the Clock Extraction of OTN device client side business transmitting terminal, for realizing client traffic transparent transmission in OTN network, the method can recover high performance client traffic clock from OTN frame, meets the requirement of various client traffic to shake.
For reaching above object, the technical scheme that the present invention takes is:
The implementation method of client traffic Clock Extraction in a kind of OTN network, it is characterized in that: adopt Statisti-cal control to add plug-in digital frequency synthesizer, the first step, carries out synchronous smoothing processing to the client traffic that OTN network solution frame goes out, makes client traffic data more even under OTN system clock; Second step, Clock Extraction control treatment: statistics and smoother rear data volume and client traffic send data volume, clock adjustment information is controlled in conjunction with FIFO buffer memory redundancy by weighting algorithm, 3rd step, Clock Extraction adaptation processing: the clock adjustment information provided by Clock Extraction control treatment, be translated into the precise frequency adjustment information that plug-in digital frequency synthesizer needs, and precisely control plug-in digital frequency synthesizer generation business tranmitting data register by serial control interface.
On the basis of technique scheme, the described smoothing processing to client traffic, comprises the following steps:
Step 1: set a smooth time window, sets according to the OTN frame period of OTN line interface usually,
Step 2: the nominal data amount calculating client traffic in a smooth time window,
Step 3: according to tolerance frequency deviation and the OTN interface tolerance frequency deviation of client traffic, calculate and smoothly go out at a smooth time window data volume that client traffic may occur, described data volume comprises a higher value, a median and a smaller value, and this data volume is integer
Step 4: the buffer status detecting synchronous random access memory, calculate the data volume that this smooth time window will read, carry out detecting the readable space of RAM at the upper limit, lower limit still in central area a smooth time window original position, as in the upper limit, the data volume that this smooth time window will read is the higher value that step 3 calculates; As at lower limit, the data volume that this smooth time window will read is the smaller value that step 3 calculates; As in central area or abnormal conditions, the data volume that this smooth time window will read is the median that step 3 calculates;
Step 5: the data volume that will read according to the smooth time window calculated, produces more uniform breach, data is read from synchronous random access memory uniformly and goes, can obtain client traffic smoothed data.
On the basis of technique scheme, second step comprises following concrete steps:
Step 1: calculate clock adjustment cycle T, N number of smooth time window is a clock adjustment cycle T, and N value is configurable, N value is larger, and the data volume of statistics is more accurate, but can not be infinitely great, if N is too large, the tracking time of Clock Extraction can be very long, and need larger buffer memory;
Step 2: the nominal data amount calculating client traffic in a clock adjustment cycle T;
Step 3: the smoothed data amount in statistical computation clock adjustment cycle T, namely FIFO receives data volume, FIFO receives data volume should within nominal value × (1+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)), otherwise FIFO receives data volume should be set to nominal value, wherein, 20ppm is OTN circuit tolerance frequency deviation; Redundancy frequency deviation is arranged voluntarily, is used for absorbing shake and ensureing that circuit can stand larger frequency deviation, as the shake of entry data amount is too large, also needs to carry out statistical average;
Step 4: the FIFO sense data amount in statistical computation clock adjustment cycle T, namely FIFO sends data volume;
Step 5: the FIFO calculated in a clock adjustment cycle T receives the difference of data volume and FIFO transmission data volume, difference should within nominal value × (+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)) scope, difference is not within this scope, represent that line speed or tranmitting data register frequency are made mistakes, now report and alarm, and difference is set to zero;
Step 6: clock adjustment windowed time, if the existing clock adjustment of each cycle is adjudicated again, can cause error to judgement, for avoiding this situation, employing current period adjusts, and next cycle adjudicates the processing mode hocketed, and in previous cycle when ensureing judgement, clock is stable;
Step 7: Clock Extraction controls, Clock Extraction controls the difference being received by FIFO and send, and the weighting algorithm of the readable spatial information of FIFO calculates clock adjustment direction and adjustment amount of bytes.
On the basis of technique scheme, the readable spatial information of FIFO is used for producing clock vernier control, is used for ensureing that FIFO is operated in safety zone.
On the basis of technique scheme, the concrete steps producing clock vernier control are:
The readable space of position judgment FIFO is adjudicated, when readable space is greater than 256, to a positive justification refinement information in the T0 cycle; A negative justification refinement information is given when readable space is less than 256; When readable space is 256, as the last T0 cycle has positive justification refinement information to produce, then produce a negative refinement information, as the last T0 cycle has negative justification refinement information to produce, then produce a positive justification refinement information, otherwise, do not produce any inching information.
On the basis of technique scheme, the generation of clock adjustment direction and adjustment amount of bytes comprises following steps:
Adjudicate position FIFO in the T0 cycle and receive the difference B of data volume and FIFO transmission data volume outside nominal value × (+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)) scope, clock does not adjust, and adjustment amount of bytes is 0; If difference B is within this scope, clock adjustment is as follows:
When difference B is 0, if there is positive justification refinement information, clock adjustment direction is positive justification, and adjustment amount is 1; If there is negative justification refinement information, clock adjustment direction is negative justification, and adjustment amount is 1; If without inching information, then do not adjusted, adjustment amount is 0;
When difference B absolute value is greater than 1, if receive amount of bytes to be greater than transmission amount of bytes, clock adjustment direction is positive justification, and adjustment amount is: receive amount of bytes-transmission amount of bytes+positive justification refinement information-negative justification refinement information; If receive amount of bytes to be less than transmission amount of bytes, clock adjustment direction is negative justification, and adjustment amount is: send amount of bytes-reception amount of bytes-positive justification refinement information+negative justification refinement information;
When difference B equals 1, if there is positive justification refinement information, clock adjustment direction is positive justification, and adjustment amount is 2; If there is negative justification refinement information, clock does not adjust, and adjustment amount is 0; If without inching information, clock adjustment direction is positive justification, and adjustment amount is 1;
When difference B equals-1, if there is negative justification refinement information, clock adjustment direction is negative justification, and adjustment amount is 2; If there is positive justification refinement information, clock does not adjust, and adjustment amount is 0; If without inching information, clock adjustment direction is negative justification.
On the basis of technique scheme, the 3rd step comprises following concrete steps:
Step 1: the frequency converted to by the adjustment amount that Clock Extraction controls required for plug-in digital frequency synthesizer adjusts the adjustment step-length of control word or frequency deviation side-play amount; The adjustment amount least unit that Clock Extraction controls is byte, and the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount is very little, needs progressively to drop near 0 by the adjustment amount that Clock Extraction controls after repeatedly adjusting;
Step 2: produce the precise frequency adjustment information that plug-in digital frequency synthesizer needs: frequency adjustment control word or frequency deviation side-play amount that first a client traffic nominal is set, this frequency adjustment control word or frequency deviation side-play amount are configured to by serial line interface the client traffic clock that plug-in digital frequency synthesizer can produce a benchmark; Then, when there being positive justification information, the frequency adjustment control word exported or frequency deviation side-play amount are adjustment control word or the frequency deviation side-play amount+adjustment step-length of last configuration, when there being negative justification information, the frequency adjustment control word of output or frequency deviation side-play amount are adjustment control word or the frequency deviation side-play amount-adjustment step-length of last configuration; When without adjustment information, do not upgrade frequency adjustment control word or the frequency deviation side-play amount of output;
Step 3: the frequency calculated adjustment control word or frequency deviation side-play amount are configured to plug-in digital frequency synthesizer chip by the serial line interface being suitable for plug-in digital frequency synthesizer, plug-in digital frequency synthesizer chip and the exportable tranmitting data register of client traffic accurately.
On the basis of technique scheme, when the adjustment amount that Clock Extraction controls is larger, the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount arranges greatly a bit; When the adjustment amount that Clock Extraction controls is less, the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount arranges a little bit smaller.
On the basis of technique scheme, frequency adjustment control word or frequency deviation side-play amount maximum and a minimum value are set, when clock Adjustable calculation, as calculate frequency adjustment control word or frequency deviation side-play amount exceed maximum or minimum value time, output frequency adjustment control word or frequency deviation side-play amount be setting maximum or minimum value;
According to client traffic tolerance frequency deviation, described maximum and minimum value add that the redundancy frequency offset calculation of 15ppm obtains.
The implementation method of client traffic Clock Extraction in OTN network of the present invention, carrying client service rate extracts business clock to adopt statistical method to predict, and is aided with buffer memory redundancy and carries out fine setting clock and ensure that buffer memory is operated in safety zone.It is little that this method realizes difficulty, and it is low to implement cost; Clock Extraction process controls mainly through adding up, and does not rely on buffer memory operating state, safe and reliable; Run into abnormal can filtration in time in statistic processes, can not cause iteration effect during equipment cascading, the clock quality of extraction is better.
Accompanying drawing explanation
The present invention has following accompanying drawing:
Fig. 1 is that client traffic is mapped to OTN network structure;
Fig. 2 is that client traffic moves towards figure in OTN network;
Fig. 3 is Clock Extraction system design functions figure provided by the invention;
Fig. 4 is clock judgement periodogram;
Fig. 5 is clock fine setting flow chart;
Fig. 6 is clock adjustment flow chart.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The implementation method of client traffic Clock Extraction in OTN network of the present invention, be applicable to the clock recovery of the client traffic of transparent transmission in OTN network, can effectively map and the shake that produces in de-mapping process by filtering client traffic, produce clocking information accurately, recover high performance client traffic tranmitting data register by plug-in digital frequency synthesizer.Can support mapping and the transparent transmission of multiple client signal based on ITU-T OTN frame structure G.709, the present invention mainly supports the client traffic of GE, STM16 and OTU1 low speed.Fig. 1 is that client traffic is mapped to OTN network structure.Client traffic forms high-order OTN frame transparent transmission on OTN network after various mapping path, and from OTN network, separate frame goes out various client traffic simultaneously.
Fig. 2 is that client traffic moves towards figure in OTN network.Client traffic forms high-order OTN frame transparent transmission on OTN network after website A is by various mapping path, after one or more levels website C, arrive website B, and website B separates frame and goes out various client traffic from OTN network.The client traffic itself that slave site B solution frame goes out is not with any timing information, and be ensure business transparent transmission, must recover the tranmitting data register of website B client traffic, the speed that business is received according to slave site A sends.Fig. 3 is system design functions figure provided by the invention.
In OTN network of the present invention, the implementation method scheme of client traffic Clock Extraction is: adopt Statisti-cal control to add plug-in digital frequency synthesizer, the first step, under OTN system clock, synchronous smoothing processing is carried out to the client traffic that OTN network solution frame goes out, makes client traffic data more even; Second step, Clock Extraction control treatment: statistics and smoother rear data volume and client traffic send data volume, clock adjustment information is controlled in conjunction with FIFO buffer memory redundancy by weighting algorithm, 3rd step, Clock Extraction adaptation processing: the clock adjustment information provided by Clock Extraction control treatment, be translated into the precise frequency adjustment information that plug-in digital frequency synthesizer needs, and precisely control plug-in digital frequency synthesizer generation business tranmitting data register by serial control interface.
On the basis of technique scheme, the described smoothing processing to client traffic, comprises the following steps:
Step 1: set a smooth time window, sets according to the OTN frame period of OTN line interface usually, if line side is OTU1, then determines smooth time window according to the time of the next OTU1 frame of the system clock domain of OTU1; If line side is ODU2, then determine smooth time window according to the time of the next ODU2 frame of the system clock domain of ODU2;
Step 2: the nominal data amount calculating client traffic in a smooth time window, as an OTU1 time in frame period, the nominal data amount of GE is the nominal data amount of 6121.4, STM16 is 7616; An ODU2 time in frame period, the nominal data amount of GE is the nominal data amount of 1523.9, STM16 is 1896;
Step 3: according to tolerance frequency deviation and the OTN interface tolerance frequency deviation of client traffic, calculate and smoothly go out at a smooth time window data volume (requiring as integer) that client traffic may occur, described data volume comprises a higher value, a median and a smaller value, as an OTU1 time in frame period, GE data volume after smoothing processing may be 6120,6121 or the data volume of 6122, STM16 may be 7615,7616 or 7617;
Step 4: the buffer status detecting synchronous random access memory, calculate the data volume that this smooth time window will read, carry out detecting the readable space of RAM at the upper limit, lower limit still in central area a smooth time window original position, as in the upper limit, the data volume that this smooth time window will read is the higher value that step 3 calculates; As at lower limit, the data volume that this smooth time window will read is the smaller value that step 3 calculates; As in central area or abnormal conditions, the data volume that this smooth time window will read is the median that step 3 calculates;
Step 5: the data volume that will read according to the smooth time window calculated, produces more uniform breach, data is read from synchronous random access memory uniformly and goes, can obtain client traffic smoothed data,
Client traffic maps upper to OTN network through one or more levels, client traffic can introduce shake in mapping and de-mapping process, and under being in the clock zone of OTN after client traffic solution frame, have data burst phenomenon, this can cause client traffic Clock Extraction difficulty to strengthen, and clock performance index is also bad.For head it off needs to separate the smoothing process of customer data that goes out of frame to OTN, smoothing processing is made up of a synchronization caching RAM and control logic.
Described in second step statistics and smoother rear data volume and client traffic send data volume, clock adjustment information is controlled in conjunction with FIFO buffer memory redundancy by weighting algorithm, i.e. Clock Extraction control treatment process, Clock Extraction control treatment is by an an asynchronous buffer FIFO and Clock Extraction control treatment logical constitution.
On the basis of technique scheme, second step comprises following concrete steps:
Step 1: calculate clock adjustment cycle T, N number of smooth time window is a clock adjustment cycle T, and N value is configurable, N value is larger, and the data volume of statistics is more accurate, but can not be infinitely great, if N is too large, the tracking time of Clock Extraction can be very long, and need larger buffer memory;
Step 2: the nominal data amount calculating client traffic in a clock adjustment cycle T;
Step 3: the smoothed data amount in statistical computation clock adjustment cycle T, namely FIFO receives data volume, FIFO receives data volume should within nominal value × (1+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)), otherwise FIFO receives data volume should be set to nominal value, wherein, 20ppm is OTN circuit tolerance frequency deviation; Redundancy frequency deviation can be arranged voluntarily, is used for absorbing shake and ensureing that circuit can stand larger frequency deviation, as the shake of entry data amount is too large, also needs to carry out statistical average;
Step 4: the FIFO sense data amount in statistical computation clock adjustment cycle T, namely FIFO sends data volume;
Step 5: the FIFO calculated in a clock adjustment cycle T receives the difference of data volume and FIFO transmission data volume, difference should within nominal value × (+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)) scope, difference is not within this scope, represent that line speed or tranmitting data register frequency are made mistakes, now report and alarm, and difference is set to zero;
Step 6: clock adjustment windowed time, if the existing clock adjustment of each cycle is adjudicated again, can cause error to judgement, for avoiding this situation, employing current period adjusts, and next cycle adjudicates the processing mode hocketed, and in previous cycle when ensureing judgement, clock is stable; Fig. 4 is clock judgement periodogram, and the T0 cycle adjudicates, the statistics in T1 cycle, and the T0 cycle also can be added up, but does not adopt;
Step 7: Clock Extraction controls, Clock Extraction controls the difference being received by FIFO and send, and the weighting algorithm of the readable spatial information of FIFO calculates clock adjustment direction and adjustment amount of bytes.
On the basis of technique scheme, the readable spatial information of FIFO is used for producing clock vernier control, is used for ensureing that FIFO is operated in safety zone.Fig. 5 is clock fine setting flow chart.The concrete steps producing clock vernier control are: adjudicate the readable space of position judgment FIFO in the T0 cycle, when readable space is greater than 256, to a positive justification refinement information; A negative justification refinement information is given when readable space is less than 256; When readable space is 256, as the last T0 cycle has positive justification refinement information to produce, then produce a negative refinement information (callback mechanism), as the last T0 cycle has negative justification refinement information to produce, then produce a positive justification refinement information (callback mechanism), otherwise, do not produce any inching information.
On the basis of technique scheme, the generation of clock adjustment direction and adjustment amount of bytes as shown in Figure 6.The generation following steps of clock adjustment direction and adjustment amount of bytes:
Adjudicate position FIFO in the T0 cycle and receive the difference B (see step 5) of data volume and FIFO transmission data volume outside nominal value × (+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)) scope, clock does not adjust, and adjustment amount of bytes is 0; If difference B is within this scope, clock adjustment is as follows:
When difference B is 0, if there is positive justification refinement information, clock adjustment direction is positive justification, and adjustment amount is 1; If there is negative justification refinement information, clock adjustment direction is negative justification, and adjustment amount is 1; If without inching information, then do not adjusted, adjustment amount is 0;
When difference B absolute value is greater than 1, if receive amount of bytes to be greater than transmission amount of bytes, clock adjustment direction is positive justification, and adjustment amount is: receive amount of bytes-transmission amount of bytes+positive justification refinement information-negative justification refinement information; If receive amount of bytes to be less than transmission amount of bytes, clock adjustment direction is negative justification, and adjustment amount is: send amount of bytes-reception amount of bytes-positive justification refinement information+negative justification refinement information;
When difference B equals 1, if there is positive justification refinement information, clock adjustment direction is positive justification, and adjustment amount is 2; If there is negative justification refinement information, clock does not adjust, and adjustment amount is 0; If without inching information, clock adjustment direction is positive justification, and adjustment amount is 1;
When difference B equals-1, if there is negative justification refinement information, clock adjustment direction is negative justification, and adjustment amount is 2; If there is positive justification refinement information, clock does not adjust, and adjustment amount is 0; If without inching information, clock adjustment direction is negative justification.
On the basis of technique scheme, the 3rd step comprises following concrete steps:
Step 1: the frequency converted to by the adjustment amount that Clock Extraction controls required for plug-in digital frequency synthesizer adjusts the adjustment step-length of control word or frequency deviation side-play amount; The adjustment amount least unit that Clock Extraction controls is byte, and the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount very little (conference of adjustment step-length causes clock to have very large shake), need progressively the adjustment amount that Clock Extraction controls to be dropped near 0 after repeatedly adjusting; For accelerating the tracking time of Clock Extraction, when the adjustment amount that Clock Extraction controls is larger, the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount arranges greatly a bit; When the adjustment amount that Clock Extraction controls is less, the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount arranges a little bit smaller;
Step 2: produce the precise frequency adjustment information that plug-in digital frequency synthesizer needs: frequency adjustment control word or frequency deviation side-play amount that first a client traffic nominal is set, this frequency adjustment control word or frequency deviation side-play amount are configured to by serial line interface the client traffic clock that plug-in digital frequency synthesizer can produce a benchmark; Then, when there being positive justification information, the frequency adjustment control word exported or frequency deviation side-play amount are adjustment control word or the frequency deviation side-play amount+adjustment step-length of last configuration, when there being negative justification information, the frequency adjustment control word of output or frequency deviation side-play amount are adjustment control word or the frequency deviation side-play amount-adjustment step-length of last configuration; When without adjustment information, do not upgrade frequency adjustment control word or the frequency deviation side-play amount of output;
For ensureing to export the reliable of client traffic clock, the frequency adjustment control word of output or frequency deviation side-play amount will ensure within normal scope; Frequency adjustment control word or frequency deviation side-play amount maximum and a minimum value are set, when clock Adjustable calculation, as when the frequency adjustment control word that calculates or frequency deviation side-play amount exceed maximum or minimum value (according to client traffic tolerance frequency deviation, maximum and minimum value add that the redundancy frequency offset calculation of 15ppm obtains), the frequency adjustment control word of output or frequency deviation side-play amount are maximum or the minimum value of setting;
Step 3: the frequency calculated adjustment control word or frequency deviation side-play amount are configured to plug-in digital frequency synthesizer chip by the serial line interface being suitable for plug-in digital frequency synthesizer, plug-in digital frequency synthesizer chip and the exportable tranmitting data register of client traffic accurately.
In sum, a kind of clock extraction method provided by the invention effectively can extract client traffic tranmitting data register in OTN system, to realize the transparent transmission of OTN carrying client business.Above-described embodiment is just described the implementation method that client traffic tranmitting data register in OTN system extracts, and other similar business clocks extract also can adopt the method, and the present invention is not limited.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment, replacement, improvement etc. done, all should be included within protection scope of the present invention.
The content be not described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (5)
1. the implementation method of client traffic Clock Extraction in an OTN network, it is characterized in that: adopt Statisti-cal control to add plug-in digital frequency synthesizer, the first step, carries out synchronous smoothing processing to the client traffic that OTN network solution frame goes out, makes client traffic data more even under OTN system clock; Second step, Clock Extraction control treatment: statistics and smoother rear data volume and client traffic send data volume, clock adjustment information is controlled in conjunction with FIFO buffer memory redundancy by weighting algorithm, 3rd step, Clock Extraction adaptation processing: the clock adjustment information provided by Clock Extraction control treatment, be translated into the precise frequency adjustment information that plug-in digital frequency synthesizer needs, and precisely control plug-in digital frequency synthesizer generation business tranmitting data register by serial control interface;
The described smoothing processing to client traffic, comprises the following steps:
Step 11: set a smooth time window, sets according to the OTN frame period of OTN line interface usually,
Step 12: the nominal data amount calculating client traffic in a smooth time window,
Step 13: according to tolerance frequency deviation and the OTN interface tolerance frequency deviation of client traffic, calculate and smoothly go out at a smooth time window data volume that client traffic may occur, described data volume comprises a higher value, a median and a smaller value, and this data volume is integer
Step 14: the buffer status detecting synchronous random access memory, calculate the data volume that this smooth time window will read, carry out detecting the readable space of RAM at the upper limit, lower limit still in central area a smooth time window original position, as in the upper limit, the data volume that this smooth time window will read is the higher value that step 13 calculates; As at lower limit, the data volume that this smooth time window will read is the smaller value that step 13 calculates; As in central area or abnormal conditions, the data volume that this smooth time window will read is the median that step 13 calculates;
Step 15: the data volume that will read according to the smooth time window calculated, produces more uniform breach, data is read from synchronous random access memory uniformly and goes, can obtain client traffic smoothed data;
Second step comprises following concrete steps:
Step 21: calculate clock adjustment cycle T, N number of smooth time window is a clock adjustment cycle T, and N value is configurable, N value is larger, and the data volume of statistics is more accurate, but can not be infinitely great, if N is too large, the tracking time of Clock Extraction can be very long, and need larger buffer memory;
Step 22: the nominal data amount calculating client traffic in a clock adjustment cycle T;
Step 23: the smoothed data amount in statistical computation clock adjustment cycle T, namely FIFO receives data volume, FIFO receives data volume should within nominal value × (1+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)), otherwise FIFO receives data volume should be set to nominal value, wherein, 20ppm is OTN circuit tolerance frequency deviation; Redundancy frequency deviation is arranged voluntarily, is used for absorbing shake and ensureing that circuit can stand larger frequency deviation, as the shake of entry data amount is too large, also needs to carry out statistical average;
Step 24: the FIFO sense data amount in statistical computation clock adjustment cycle T, namely FIFO sends data volume;
Step 25: the FIFO calculated in a clock adjustment cycle T receives the difference of data volume and FIFO transmission data volume, difference should within nominal value × (+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)) scope, difference is not within this scope, represent that line speed or tranmitting data register frequency are made mistakes, now report and alarm, and difference is set to zero;
Step 26: clock adjustment windowed time, if each cycle, existing clock adjustment was adjudicated again, error can be caused to judgement, for avoiding this situation, employing current period adjusts, next cycle adjudicates the processing mode hocketed, and in previous cycle when ensureing judgement, clock is stable;
Step 27: Clock Extraction controls, Clock Extraction controls the difference being received by FIFO and send, and the weighting algorithm of the readable spatial information of FIFO calculates clock adjustment direction and adjustment amount of bytes; The readable spatial information of FIFO is used for producing clock vernier control, and the method producing clock control is: adjudicate the readable space of position judgment FIFO in the T0 cycle, when readable space is greater than 256, to a positive justification refinement information; A negative justification refinement information is given when readable space is less than 256; When readable space is 256, as the last T0 cycle has positive justification refinement information to produce, then produce a negative refinement information, as the last T0 cycle has negative justification refinement information to produce, then produce a positive justification refinement information, otherwise, do not produce any inching information;
3rd step comprises following concrete steps:
Step 31: the frequency converted to by the adjustment amount that Clock Extraction controls required for plug-in digital frequency synthesizer adjusts the adjustment step-length of control word or frequency deviation side-play amount; The adjustment amount least unit that Clock Extraction controls is byte, and the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount is very little, needs progressively to drop near 0 by the adjustment amount that Clock Extraction controls after repeatedly adjusting;
Step 32: produce the precise frequency adjustment information that plug-in digital frequency synthesizer needs: frequency adjustment control word or frequency deviation side-play amount that first a client traffic nominal is set, this frequency adjustment control word or frequency deviation side-play amount are configured to by serial line interface the client traffic clock that plug-in digital frequency synthesizer can produce a benchmark; Then, when there being positive justification information, the frequency adjustment control word exported or frequency deviation side-play amount are adjustment control word or the frequency deviation side-play amount+adjustment step-length of last configuration, when there being negative justification information, the frequency adjustment control word of output or frequency deviation side-play amount are adjustment control word or the frequency deviation side-play amount-adjustment step-length of last configuration; When without adjustment information, do not upgrade frequency adjustment control word or the frequency deviation side-play amount of output;
Step 33: the frequency calculated adjustment control word or frequency deviation side-play amount are configured to plug-in digital frequency synthesizer chip by the serial line interface being suitable for plug-in digital frequency synthesizer, plug-in digital frequency synthesizer chip and the exportable tranmitting data register of client traffic accurately.
2. the implementation method of client traffic Clock Extraction in OTN network as claimed in claim 1, is characterized in that: the readable spatial information of FIFO is used for producing clock vernier control, is used for ensureing that FIFO is operated in safety zone.
3. the implementation method of client traffic Clock Extraction in OTN network as claimed in claim 1, it is characterized in that, the generation of clock adjustment direction and adjustment amount of bytes comprises following steps:
Adjudicate position FIFO in the T0 cycle and receive the difference B of data volume and FIFO transmission data volume outside nominal value × (+/-(client traffic tolerance maximum frequency deviation+20ppm+ redundancy frequency deviation)) scope, clock does not adjust, and adjustment amount of bytes is 0; If difference B is within this scope, clock adjustment is as follows:
When difference B is 0, if there is positive justification refinement information, clock adjustment direction is positive justification, and adjustment amount is 1; If there is negative justification refinement information, clock adjustment direction is negative justification, and adjustment amount is 1; If without inching information, then do not adjusted, adjustment amount is 0;
When difference B absolute value is greater than 1, if receive amount of bytes to be greater than transmission amount of bytes, clock adjustment direction is positive justification, and adjustment amount is: receive amount of bytes-transmission amount of bytes+positive justification refinement information-negative justification refinement information; If receive amount of bytes to be less than transmission amount of bytes, clock adjustment direction is negative justification, and adjustment amount is: send amount of bytes-reception amount of bytes-positive justification refinement information+negative justification refinement information;
When difference B equals 1, if there is positive justification refinement information, clock adjustment direction is positive justification, and adjustment amount is 2; If there is negative justification refinement information, clock does not adjust, and adjustment amount is 0; If without inching information, clock adjustment direction is positive justification, and adjustment amount is 1;
When difference B equals-1, if there is negative justification refinement information, clock adjustment direction is negative justification, and adjustment amount is 2; If there is positive justification refinement information, clock does not adjust, and adjustment amount is 0; If without inching information, clock adjustment direction is negative justification.
4. the implementation method of client traffic Clock Extraction in OTN network as claimed in claim 1, is characterized in that: when the adjustment amount that Clock Extraction controls is larger, the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount arrange large a bit; When the adjustment amount that Clock Extraction controls is less, the adjustment step-length of frequency adjustment control word or frequency deviation side-play amount arranges a little bit smaller.
5. the implementation method of client traffic Clock Extraction in OTN network as claimed in claim 1, it is characterized in that: frequency adjustment control word or frequency deviation side-play amount maximum and a minimum value are set, when clock Adjustable calculation, as calculate frequency adjustment control word or frequency deviation side-play amount exceed maximum or minimum value time, output frequency adjustment control word or frequency deviation side-play amount be setting maximum or minimum value;
According to client traffic tolerance frequency deviation, described maximum and minimum value add that the redundancy frequency offset calculation of 15ppm obtains.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210303087.0A CN102833063B (en) | 2012-08-24 | 2012-08-24 | The implementation method of client traffic Clock Extraction in a kind of OTN network |
| PCT/CN2013/079967 WO2014029253A1 (en) | 2012-08-24 | 2013-07-24 | Method for extracting client service clock from otn network |
| MYPI2014703211A MY167451A (en) | 2012-08-24 | 2013-07-24 | Method for extracting client service clock from otn network |
| CL2015000112A CL2015000112A1 (en) | 2012-08-24 | 2015-01-14 | Method for extracting a customer service clock from an otn network, which comprises the steps of 1) using the otn system clock to synchronize smoothly a customer service unlocked by an otn network, 2) perform statistical calculation and compare the volume of data smoothed with the volume of data transmitted by the customer service, and 3) convert the clock setting information, provided by the clock extraction control, into frequency adjustment information |
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| CN201210303087.0A CN102833063B (en) | 2012-08-24 | 2012-08-24 | The implementation method of client traffic Clock Extraction in a kind of OTN network |
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| CN102833063B (en) * | 2012-08-24 | 2015-08-19 | 烽火通信科技股份有限公司 | The implementation method of client traffic Clock Extraction in a kind of OTN network |
| US11487871B2 (en) * | 2015-01-31 | 2022-11-01 | San Diego Gas & Electric Company | Methods and systems for detecting and defending against invalid time signals |
| CN104702365A (en) * | 2015-03-09 | 2015-06-10 | 烽火通信科技股份有限公司 | Delta sigma principle-based clock adjustment system and method |
| CN105490767B (en) * | 2015-11-16 | 2017-09-26 | 中国电子科技集团公司第十研究所 | The method that parallel intermittent data circulation is changed to serial continuous data stream output |
| CN110417504B (en) * | 2019-09-11 | 2021-08-24 | 天津光电通信技术有限公司 | Method for outputting signal solved in OTN from SERDES |
| CN110519667B (en) * | 2019-09-11 | 2021-08-24 | 天津光电通信技术有限公司 | Method for realizing optical signal line crossing |
| CN110808808A (en) * | 2019-11-13 | 2020-02-18 | 天津光电通信技术有限公司 | Method for extracting signal clock from OTN |
| CN113573174A (en) * | 2020-04-28 | 2021-10-29 | 华为技术有限公司 | Service processing method and device |
| CN112821981B (en) * | 2021-01-19 | 2023-03-24 | 柳州达迪通信技术股份有限公司 | Service recovery clock extraction method, system and storage medium based on optical transport network |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101277162A (en) * | 2007-03-28 | 2008-10-01 | 华为技术有限公司 | Method and apparatus for removing jitter in demapping, method and apparatus for obtaining clock, phase discriminator |
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| CN1330152C (en) * | 2003-08-01 | 2007-08-01 | 华为技术有限公司 | Apparatus and method for clock recovery for time division multiplexing business |
| WO2007072921A1 (en) * | 2005-12-22 | 2007-06-28 | Nippon Telegraph And Telephone Corporation | Optical transmission system and method |
| CN101252403B (en) * | 2008-01-22 | 2011-12-07 | 中兴通讯股份有限公司 | Realizing method of traffic transmission in light transmitted network |
| US8437641B2 (en) * | 2008-10-21 | 2013-05-07 | Bay Microsystems, Inc. | Clock regeneration for optical communications |
| US8588245B2 (en) * | 2009-02-17 | 2013-11-19 | Telefonaktiebolaget L M Ericsson (Publ) | Methods and systems for frame generation in communication networks |
| CN102510321B (en) * | 2011-11-02 | 2016-02-10 | 烽火通信科技股份有限公司 | Based on the clock recovery method of Direct Digital Synthesizer |
| CN102833063B (en) * | 2012-08-24 | 2015-08-19 | 烽火通信科技股份有限公司 | The implementation method of client traffic Clock Extraction in a kind of OTN network |
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| CN101277162A (en) * | 2007-03-28 | 2008-10-01 | 华为技术有限公司 | Method and apparatus for removing jitter in demapping, method and apparatus for obtaining clock, phase discriminator |
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| MY167451A (en) | 2018-08-28 |
| WO2014029253A1 (en) | 2014-02-27 |
| CL2015000112A1 (en) | 2015-05-04 |
| CN102833063A (en) | 2012-12-19 |
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