CN102832945B - Sigma-delta modulator - Google Patents
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- CN102832945B CN102832945B CN201210195640.3A CN201210195640A CN102832945B CN 102832945 B CN102832945 B CN 102832945B CN 201210195640 A CN201210195640 A CN 201210195640A CN 102832945 B CN102832945 B CN 102832945B
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Abstract
A sigma-delta modulator includes a front portion and a hybrid portion to form a loop filter. The front portion includes integrator(s) and feed-forward path(s), and is arranged to provide a front signal by combining signals of the integrator(s) and feed-forward path(s). The hybrid portion is coupled to the front portion, and arranged to provide a filtered signal by combining an integration of the front signal and a weighting of the front signal. The filtered signal is quantized, converted from digital to analog, and fed back to the loop filter. According to the sigma-delta modulator, hardware complexity, power consumption and layout area is reduced.
Description
[technical field]
The invention relates to a kind of sigma-delta modulator (sigma-delta modulator), and relate to especially and a kind ofly in resistance-type feed-forward loop filter, the forward path being directed to loop filter output to be replaced, reducing hardware complexity, reduce layout area and reduce the sigma-delta modulator of power consumption.
[background technology]
Sigma-delta modulator can be used in analog-to-digital conversion, has become one of key components in signal/message/image-processing circuit and communicating circuit.
Sigma-delta modulator includes primary Ioops filter, a quantizer and a digital to analog converter.The analog feedback signal that the signal meeting of one analog input and digital to analog converter export does linear combination, and feeds back to loop filter.Accordingly, loop filter produces a filtering signal, and it can be quantified as the quantized signal of a numeral by a quantizer (quantizer).So, analog input signal just can be converted into corresponding digital signal.Quantized signal also can be converted back the analog signal of a correspondence by digital to analog converter, using as aforesaid analog feedback signal, and feed back to loop filter.Via feedback architecture, quantizing noise (error) will be treated to the frequency band of high frequency, with by loop filter filtering.
Resistance-type feedforward topology can in order to realize the loop filter of high-performance continuous time (continuous-time).The loop filter of resistance-type feedforward topology comprises an integration link and multiple forward path realized with resistance.Integration link comprises the integrator of multiple serial connection, for integrated signal; Each integrator is directed to once the port of high order by Single port, that is each integrator, by Single port Received signal strength, by the signal integration received, and exports the port of time high order to.Each forward path then bypass in integration link, by the signal weighting of a low order port, and by its feed forward, with the signal plus with a higher-order port.As loop filter needs a forward path to make one first signal of a low order port be able to and the secondary signal output signal of last integrator (namely in integration link) of the highest order port does linear combination, an extra adder circuit will be needed, as an operational amplifier, to combine the first signal and secondary signal.This extra adder circuit can make the more power of loop filter consumption, and occupies larger layout area.
For example, in four (4-th order) loop filters, if there is a forward path to be directed to the port of the highest order, this loop filter just needs could realize with five operational amplifiers; These five operational amplifiers wherein four in order to realize four integrators (i.e. four filtering of order one to four), another is then in order to realize extra adder circuit.That is the continuous-time sigma-delta modulator realized with resistance-type feedforward topology must finally add extra adder (realizing with operational amplifier) at loop filter, therefore can consume larger current and larger chip area.
[summary of the invention]
In view of this, the embodiment of the present invention provides a kind of sigma-delta modulator, to solve the problem.
One embodiment of the invention provide a sigma-delta modulator, comprise a front portion and mix part with one.Front portion comprises at least one leading portion integrator and at least one forward path.Leading portion integrator provides a first integral signal according to the integration of an internal signal.Forward path bypass in leading portion integrator, in order to weighting internal signal to provide a feed-forward signal.Front portion provides a summation signals according to first integral signal, and provides a front signal according to the linear combination of summation signals and feed-forward signal.Mixing part couples front portion, weighting front signal to provide a weighted signal, integration front signal to provide a second integral signal, and by weighted signal and second integral signal combination to provide a filtering signal.
In one embodiment, mixing part comprises the weight path of a back segment integrator and a resistance-type, respectively in order to integration front signal and weighting front signal.Because mixing part incorporates the function of integration and linear combination (weighting be added), the hardware complexity of loop filter, power consumption and layout area can be reduced.So, No. four filters just can realize with four amplifiers, do not need to set up amplifier to realize extra adder circuit.
In one embodiment, front portion is provided with a leading portion input port to receive an input signal, and a leading portion output port to export front signal, and provides internal signal according to input signal.Forward path has a feedforward input port to receive internal signal, and has a feed forward output mouth to export feed-forward signal.Leading portion integrator has an integration input port to receive internal signal, and has an integration output port to export first integral signal.Feedforward input port is coupled to integration input port, and feed forward output mouth is then coupled between integration output port and leading portion output port; That is forward path crosses over leading portion integrator, with bypass in leading portion integrator.
In one embodiment, front portion also comprises one second leading portion integrator, is coupled between integration output port and leading portion output port.Accordingly, front portion can provide summation signals according to the integration of first integral signal.
In one embodiment, the second leading portion integrator is coupled between integration output port and feed forward output mouth, in order to provide a third integral signal according to the integration of first integral signal.That is forward path crosses over two or more leading portion integrators.Front portion also provides summation signals according to third integral signal.In one embodiment, front portion also comprises one second forward path, is coupled between feedforward input port and integration output port.That is the number of the leading portion integrator of the second forward path cross-over connection is less than aforesaid forward path, in order to weighting internal signal to provide one second feed-forward signal.Accordingly, front portion can provide summation signals according to the linear combination of first integral signal and the second feed-forward signal.
In one embodiment, the second leading portion integrator is coupled between feed forward output mouth and leading portion output port, in order to the combination of integration feed-forward signal and summation signals to provide a third integral signal.That is forward path bypass is in the first leading portion integrator but non-cross-over connection second leading portion integrator.Accordingly, front portion response third integral signal (combination of such as summation signals and feed-forward signal) is to provide front signal.
In one embodiment, sigma-delta modulator also comprises a quantizer and a digital to analog converter.Quantizer is coupled to mixing part, in order to quantification filtering signal to provide a quantized signal.Digital to analog converter couples quantizer, in order to change quantized signal to provide a feedback signal.Accordingly, front portion responsive feedback signal is to provide internal signal.
In one embodiment, front portion also provides one the 3rd internal signal according to an auxiliary signal, and the combination of integration one second internal signal and the 3rd internal signal is to provide a third integral signal.Front portion also comprises a secondary path, and weighting third integral signal is to provide auxiliary signal.In one embodiment, the combination of leading portion integrator integration internal signal and auxiliary signal is to provide first integral signal, and front portion weighting first integral signal is to provide the 3rd internal signal.Second internal signal is obtained by internal signal weighting; For example, feed-forward signal can be used as the second internal signal.Secondary path can introduce the zero point of non-zero in the transfer function of quantizing noise (transfer function), to strengthen the filtering of (in-band) noise in frequency band.
One embodiment of the invention provide a sigma-delta modulator, have primary Ioops filter, and it comprises a path of integration, at least one forward path and mixes part with one.Path of integration comprises multiple internal port orderly and preset number (one or more) leading portion integrator, and each leading portion integrator is led once by an internal port internal port of high order.Forward path is directed to the internal port of another higher-order by an internal port, and bypass is in this preset number leading portion integrator.Mixing part comprises an input port, an output port, a back segment integrator and a weight path; Input port couples one of them of internal port, and back segment integrator is directed to output port by input port, and weight path to be led output port by input port, and bypass is in back segment integrator.
In one embodiment, sigma-delta modulator also comprises one second forward path, is directed to the higher internal port of another order by an internal port.For example, suppose that forward path is by one first internal port guiding one second internal port, the second forward path can by the first internal port guiding one the 3rd internal port, and its order is greater than the first internal port.
In one embodiment, sigma-delta modulator also comprises a secondary path, is directed to the lower internal port of an order by an internal port.In one embodiment, suppose that secondary path is directed to one first internal port, then the signal being directed to the first internal port via secondary path more can be combined by path of integration with the signal being directed to the first internal port via path of integration.
In one embodiment, sigma-delta modulator also comprises a quantizer and a digital to analog converter.Quantizer is coupled to output port to quantize the signal of output port.Digital to analog converter in quantizer to internal port between carry out digital-to-analogue conversion.
In one embodiment, suppose that forward path is directed to one first internal port, then the signal being directed to the first internal port via forward path and the signal being directed to the first internal port via path of integration also can by path of integration in addition linear combinations.
Sigma-delta modulator of the present invention can make hardware complexity, power consumption, layout area effectively be reduced.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating accompanying drawing, being described in detail below.
[accompanying drawing explanation]
Fig. 1 is a kind of structural representation of sigma-delta modulator;
Fig. 2 is the structural representation of a kind of embodiment of the loop filter of Fig. 1;
Fig. 3 is the structural representation of the sigma-delta modulator of one embodiment of the invention;
Fig. 4 is the structural representation of an embodiment of loop filter in Fig. 3 of the present invention;
Fig. 5 is the structural representation of the sigma-delta modulator of another embodiment of the present invention;
Fig. 6 is the structural representation of an embodiment of loop filter in Fig. 5 of the present invention.
[embodiment]
Please refer to Fig. 1, the embodiment of what it was illustrated is a kind of sigma-delta modulator 10.Sigma-delta modulator (sigma-delta modulator, SDM) 10 comprise primary Ioops filter 12, quantizer 14, dynamic element matching (dynamic element matching, DEM) circuit 16 and a digital to analog converter (digital-to-analog converter, DAC) 18.Sigma-delta modulator 10 also comprises multiple weighting circuit 22a to 22j, and each weighting circuit is weighted signal according to a coefficient of correspondence.When signal u (t) of an analog input will be converted to the digital signal v (n) of a correspondence by sigma-delta modulator 10, signal u (t) of simulation receives from Single port i0, be weighted with a coefficient B 1, and be added with another analog signal uf (t); The result be added can be fed back in loop filter 12, and accordingly, loop filter 12 can provide filtering signal x (t).Quantizer 14 can quantize filtering signal x (t) of loop filter 12, to produce the quantized signal v (n) of numeral.The quantized signal v (n) of numeral is converted back a corresponding analog signal uf0 (t) by dynamic element matching circuit 16 and digital to analog converter 18 together, then with a coefficient D1 weighting, and feed back to loop filter 12, become signal uf (t).
In sigma-delta modulator 10, loop filter 12 is the feedforward topology on four rank, and comprises three forward path and an integration link.The weighting circuit 22f to 22h that three feed forward circuits are respectively A0 to A2 by coefficient respectively formed.The weighting circuit 22b to 22e that integration chain route coefficient is respectively B2 to B5 is respectively C1/s, C2/s with transfer function, the integrator 20a to 20d of C3/s and C4/s formed.Integrator 20a to 20d is connected in series, and the weighting circuit 22b to 22e that coefficient is respectively B2 to B5 is then arranged at therebetween.Integrator 20a is directed to port o1 by port i1, and the signal being received from port i1 is carried out integration, provide according to this (output) one signal (integrated signal) x1 (t) to port o1.Similarly, integrator 20b, 20c and 20d in order to integration are directed to port o2, o3 and o4 by port i2, i3 and i4 respectively.Port o1 and i3 to i5 has the order (progression) of integration; The order of port o1 is minimum, because only have an integrator 20a between port i1 and o1.Compared with port o1, port i3 has the order of time high (high one-level), because be coupled with two integrator 20a and 20b between port i1 and i3.Relative to port i3, port i4 has secondary high order.The order of port i5 is the highest, because all integrators of loop filter 12 are all coupled between port i1 and i5.
Three forward path that coefficient is respectively A0, the weighting circuit 22f to 22h of A1 and A2 realizes loop filter 12 respectively.Each forward path is directed to the another port of higher-order in integration link by the port of a lower order, and therefore, the signal of lower order port can be combined into the signal being directed to higher-order port via integration link.For example, the forward path being A2 due to coefficient is directed to port i3 by port o1, therefore, the signal being directed to port i3 via integration link with regard to can and signal x1 (t) of port o1 carry out linear combination.Similarly, coefficient is that the forward path of A0 is directed to the highest port i5 of order by port o1, makes signal x1 (t) energy of port o1 and the output signal linearity combination of tail end integrator 20d.Along integration chain routed port o1 to i5, signal x1 (t) can by integrator 20b to 20d integration three times, and combine with signal x1 (t) itself, because signal x1 (t) itself also can via the forward path fl transmission of coefficient A0 to port i5.
Please refer to Fig. 2, a kind of embodiment of what it was illustrated the is loop filter 12 realized in Fig. 1.Integrator 20a to 20d is realized C1 to C4 with electric capacity by differential amplifier OP1 to OP4 respectively.Port i0 to i5, o1 to o4 difference corresponding node in Fig. 1 is to i0p/i0n to i5p/i5n, o1p/o1n to o4p/o4n.Resistance is to Rb1 to Rb5, Ra0 to Ra2, and Rr is relevant to coefficient B 1 to B5, A0 to A2 and G1 in Fig. 1 respectively.It should be noted that, differential amplifier OP5 and a pair resistance Rbs of an additional is also comprised in Fig. 2, so, being directed to output node via differential amplifier OP4 could mutual additive combination to the differential wave of o1p/o1n to the differential wave of o4n/o4p and guiding node.That is, except realizing each amplifier of each integrator in integration link, loop filter structure in Fig. 1 also needs to set up an extra amplifier, for carrying out additive combination to the signal being directed to port i5 via integration link with the signal being directed to port i5 via coefficient A0 forward path.This amplifier set up can consume extra power, and occupies extra layout area.
In order to overcome the shortcoming of setting up amplifier, the invention provides the loop filter of a resistance-type feedforward topology, it can adopt a weight path between the port of the port of the highest order and contiguous secondary low order, therefore, just can be substituted by the forward path of lower order port extremely the highest order port.Please refer to Fig. 3, what it was illustrated is according to the sigma-delta modulator 30 of one embodiment of the invention.Sigma-delta modulator 30 can be used as an analog to digital converter, and comprises primary Ioops filter 32, quantizer 34, dynamic element matching circuit 36 and a D/A converter 38.When one analog signal u (t) is converted to the digital signal v (n) of a correspondence by sigma-delta modulator 30, analog input signal u (t) transferring to port i0 can be the weighting circuit 48a weighting of b1 by coefficient, and combine with analog feedback signal uf (t), to form signal x0 (t).Loop filter 32 has two-port i1 and o4, and via port i1, loop filter 32 Received signal strength x0 (t) as an input signal, and produces filtering signal x (t) with response signal x0 (t).Filtering signal x (t) is exported by port o4, and transfers to quantizer 34.Quantizer 34 couples loop filter 32, in order to quantification filtering signal x (t) to produce the quantized signal v (n) of a numeral, so, input signal u (t) of simulation just can be converted to quantized signal v (n) by sigma-delta modulator 30.Digital to analog converter 38 couples quantizer 34 via element matching circuit 36, and with element matching circuit 36 Collaboration, quantized signal v (n) is converted to the feedback signal uf0 (t) of simulation.The weighting circuit 48b that feedback signal uf0 (t) is then d1 by coefficient is weighted to feedback signal uf (t).
Loop filter 32, such as four rank loop filters, include a front portion 50 and mix part 52 with one.Front portion 50 comprises integrator 40a to 40c and weighting circuit 42a to 42c, 46a to 46b and 54.The transfer function of integrator 40a, 40b and 40c is respectively c1/s, c2/s and c3/s, and wherein c1 to c3 is coefficient.Weighting circuit 42a to 42c, 46a to 46b and 54 coefficient be then respectively b2 to b4, a1 to a2 and g1.Integrator 40a to 40c and weighting circuit 42a to 42c is coupled to port i1, o1, i2, o2 alternately, between i3, o3 and i4, forms the path of integration of a serial connection.Because integrator 40b to 40c is respectively coupled between port o1, i3 and i4, port o1, i3 and i4 to can be considered in path of integration internal port orderly; The order of port o1 is minimum, and the order of port i4 is the highest.Each integrator 40a to 40c is in order to be directed to the another port of time high order by an internal port.For example, integrator 40b is directed to port i3 by port i2, and wherein, port i2 also can be considered an internal port, and its order can be considered it is identical with the order of port o1, because do not have integrator between port o1 and i2.Similarly, the order of port o2 and i3 is identical.Integrator 40a to 40c by respectively to signal x0 (t) received by port i1, i2 and i3, z1 (t) and z2 (t) in addition integration, with signal x1 (t), x2 (t) and x3 (t) after producing integration respectively to port o1, o2 and o3.
In loop filter 32, weighting circuit 46a and the 46b that coefficient is respectively a1 and a2 forms two forward path.Each forward path in order to be directed to another higher internal port of order from an internal port, and carries out bypass to integrator 40a to 40c; Therefore, a lower order port signal can with the signal combination of higher-order port.Coefficient is that the forward path of a1 is directed to port i4 by port o1, and signal x1 (t) that port o1 is exported can combine with signal x3 (t); Wherein, signal x3 (t) is then the signal being directed to port i4 via path of integration.Similarly, coefficient is that the forward path of a2 is directed to another port i3 by port o1, makes signal x1 (t) of lower order port o1 can do linear combination with signal x2 (t) of higher-order port o2.
On the other hand, coefficient is that the weighting circuit 54 of g1 forms a secondary path, and this secondary path is directed to the port i2 of lower order by port o3.So, signal x3 (t) by coefficient g1 weighting, and will combine in port i2 and signal b2 × x1 (t).That is, the integrator 40c of front portion 50 by signal a2 × x1 (t) exported by weighting circuit 46b and 42b respectively with b3 × x2's (t) with carry out integration, to produce integrated signal x3 (t); Coefficient is that the secondary path of g1 is by being weighted to produce an auxiliary signal aux (t) to signal x3 (t), the integrator 40b of front portion 50 is then by carrying out integration to produce signal x2 (t) to signal z1 (t), wherein, signal z1 (t) is auxiliary signal aux (t) and the linear combination of signal x1 (t), i.e. z1 (t)=(b2 × x1 (t)-g1 × aux (t)), signal x1 (t) is then the signal of integrator 40a integration gained.
In loop filter 32, mixing part 52 is coupled to port i4, and comprises an an integrator 40d and two weighting circuit 42d and 56.The transfer function of integrator 40d is c4/s, c4 is coefficient, and weighting circuit 42d and 56 then has coefficient b5 and a3 respectively.Integrator 40d is directed to port o4 by port i4, carries out integration, to produce signal x4 (t) after integration in order to signal z3 (t) by exporting front portion 50.Coefficient is that the weighting circuit 56 of a3 forms a weight path, is directed to port o4 by port i4, in order to be weighted to produce signal z3 ' (t) after a weighting to signal z3 (t); Signal x (t) is namely the linear combination of signal x4 (t) and z3 ' (t).The equation EQ1 of Fig. 3 represents Laplce (Laplace) transfer function of loop filter 32, such as X (s)/X0 (s); Wherein, X (s) and X0 (s) are respectively and change the Laplce of time-domain signal x (t) with x0 (t).In equation EQ1, front portion 50 provides three transfer functions with three limits (pole) and two zero points; Mixing part 52 provides has a single limit and the transfer function at single zero point.
Because signal z1 (t)=(b2 × x1 (t)-g1 × x3 (t)) comprises signal x1 (t), when integrator 40b carries out integration to provide signal x2 (t) to port i3 to signal z1 (t), signal x2 (t) of integration just comprises the integration of signal x1 (t); That is be forward path and the integrator 40b of a2 via coefficient, signal x1 (t) itself and its integrated signal are able to combine at port i3.Moreover, due to be about to be integrated device 40c integration signal z2 (t) in comprise integration after the weighting of signal x1 (t), signal x1 (t) can be integrated device 40b and 40c integration twice along path of integration, and signal x1 (t) itself that the result of this twice integration also can be transmitted for a1 forward path with coefficient combines.In mixing part 52, signal x1 (t) can experience the third time integration of integrator 40d.That is via integrator 40b to 40d, signal x1 (t) is integrated three times, form a part for signal x4 (t).
In the feedforward topological structure shown in Fig. 1, coefficient is that the forward path of A0 makes signal x1 (t) be able to combine with the triple integral result of signal x1 (t), but also needs the amplifier OP5 of an additional to realize this combination.Relatively, the forward path that the loop filter shown in Fig. 3 32 is take coefficient as the weight path substitution index of a3 is A0.Via the path that weighting circuit 46a and 56 is formed, signal x1 (t) also can be fed forward to port o4, and signal x1 (t) can be combined with the triple integral result of signal x1 (t) equally.Therefore, compared to loop filter 12, loop filter 32 still can provide enough functions.But because mixing part 52 can realize with single amplifier, therefore the hardware complexity of loop filter 32, power consumption and layout area all can be less than loop filter 12.
Please refer to Fig. 4, what it was illustrated is in order to realize the circuit layer level framework of loop filter 32 in one embodiment of the invention.In the diagram, Fig. 3 loop filter 32 can with four amplifier (as differential operational amplifier) op1 to op4, resistance to R1 to R4, Rf1 to Rf2, Rr1 and Rs and electric capacity to C1 to C4(as variable capacitance) be achieved.Differential node is to i0p and i0n, i1p and i1n, i2p and i2n, i3p and i3n, i4p and i4n, o1p and o1n, o2p and o2n, o3p and o3n and o4p and o4n corresponding ports i0, i1, i2, i3, i4, o1, o2, o3 and o4 respectively.Integrator 40a to 40d(Fig. 3) C1 to C4 is realized with electric capacity with amplifier op1 to op4 respectively.For example, node i 1p, i1n, o1p and o1n are coupled to the positive input terminal of amplifier op1, negative input end, positive output end and negative output terminal respectively; Electric capacity to C1 between one of them positive input terminal being coupled to amplifier op1 and negative output terminal, between the negative input end that electric capacity is then coupled to amplifier op1 to another in C1 and positive output end.
Resistance is respectively coupled to positive input terminal and the negative input end of amplifier op1 to R1.Resistance is coupled between the positive output end of amplifier op1/op2/op3/op3 and the negative input end of amplifier op2/op3/op4/op2 to one of them of R2/R3/R4/Rr1, between the negative output terminal that resistance another resistance to R2/R3/R4/Rr1 is then coupled to amplifier op 1/op2/op3/op3 and the positive input terminal of amplifier op2/op3/op4/op2.Resistance is coupled between the positive output end of amplifier op1 and the positive input terminal of amplifier op4/op3 to one of them of Rf1/Rf2, and resistance is then coupled between the negative output terminal of amplifier op1 and the negative input end of amplifier op4/op3 another resistance in Rf1/Rf2.Resistance to one of them and the electric capacity of Rs to C4 between one of them positive output end being serially connected with amplifier op4 and negative input end, between the negative output terminal that resistance is then serially connected with amplifier op4 to another resistance in Rs and electric capacity to another electric capacity in C4 and positive input terminal.
The numerical value (Fig. 3) of coefficient c1 to c4 can be determined by the capacitance of electric capacity C1 to C4.Resistance then distinguishes the numerical value of coefficient of correspondence b1, b2, b3, b4, a1, a2, a3 and g1 to the resistance value of R1, R2, R3, R4, Rf1, Rf2, Rs and Rr1; Wherein, coefficient b5 summable coefficients c4 combines, and makes coefficient product c4 × b5 can be controlled by the capacitance of electric capacity C4.As shown in Figure 4, mixing part 52 provides the several functions of integration and linear combination (weighting be added), and it can utilize single amplifier op4, resistance is achieved to C4 to Rs and electric capacity.
Known with Fig. 2 by comparison diagram 4, by the feed forward circuit (Fig. 1) of substitution index A0, just can be reduced to four (Fig. 4) by five (Fig. 2) in order to the amplifier number realizing homogeneous transfer function.The addition that originally will realize respectively with two amplifier OP5 and OP4 in fig. 2 and integrating function can be integrated, to be realized by the single amplifier op4 of mixing part 52, as shown in Figure 4.
Please refer to Fig. 5, what it was illustrated is according to the loop filter 32A of one embodiment of the invention; Sigma-delta modulator 30(Fig. 3) loop filter 32 replaceable be loop filter 32A.Loop filter 32A comprises N number of integrator G [1] to G [N], N number of weighting circuit 42, weighting circuit 56 and one or more weighting circuit 46, mixes part 52A to form a front portion 50A with one.In addition, loop filter 32A can comprise one or more weighting circuit 54 in former-section circuit 50A, also can not arrange any weighting circuit 54.
The transfer function of integrator G [1] to G [N] is for being respectively c [1]/s to c [N]/s.For k=1 to N, transfer function is that the integrator G [k] of c [k]/s is coupled between port i [k] and oa [k], receives a signal, carries out integration to this signal, and exported to port oa [k] by integral result by port i [k].The coefficient of each weighting circuit 42 is respectively b [2] to b [N]; For k=1 to (N-1), coefficient is that the weighting circuit 42 of b [k+1] is coupled between port oa [k] and port ob [k], and the signal of port oa [k] by coefficient b [k+1] weighting, and can be transmitted to port ob [k].To k=1 to (N-1), port ob [k] is coupled to the port i [k+1] of next integrator, integrator G [1] to G [N-1] is connected in series alternately with the weighting circuit 42 of coefficient b [2] to b [N], forms the path of integration in front portion 50A.
Each weighting circuit 46 provides a coefficient a [j], and form a forward path being led port ob [kjH] by port oa [kjL], make the signal of port oa [kjL] can by coefficient a [j] weighting, and export port ob [kjH] to, wherein, index kjH and kjL selects in (N-1) by 1, and index kjH is greater than kjL.For example, front portion 50A can comprise the weighting circuit 46 that a coefficient is a [1], is directed to port ob [N-1] by port oa [1].In one embodiment, the forward path that (N-2) individual coefficient is a [1] to a [N-2] can be set; For j=1 to (N-2), coefficient a [j] is directed to port ob [N-j] by port oa [1], and carries out bypass to each integrator G [1] to G [N-1].The feed forward circuit being a [j] due to coefficient is connected across port oa [kjL] and ob [kjH], integrator between port oa [kjL] to ob [kjH] is bypassed, the signal being directed to port ob [kjH] from port oa [kjL] via path of integration just can and the signal of port oa [kjL] itself combine.That is, forward path experiences less integration signal (signal as port oa [kjL]) can directly and the signal (signal as port ob [kjH]) path of integration experiencing more repeatedly integration mutually combine.
If be provided with weighting circuit 54, each weighting circuit 54 is in order to provide a coefficient g [i], and form one to be directed to port ob [kiL] secondary path by port oa [kiH], make the signal of port oa [kiH] by coefficient g [i] weighting, and port ob [kiL] can be transmitted to; Wherein, index kiH and kiL selects in (N-1) by 1, and index kiH is greater than kiL.For example, it is that the weighting circuit 54(of g1 is not shown that front portion 50A can comprise a coefficient), be directed to port ob [1] by port oa [3].In front portion 50A, the signal plus that each port ob [k] makes the signal of path of integration be able to forward path or secondary path, for k=1 to (N-1).Secondary path can the transfer function limit (i.e. the zero point of quantizing noise) of subsidiary control loop filter 32A, some limit can be placed in and be greater than in the frequency of zero.
In mixing part 52A, the weighting circuit 42 of transfer function to be integrator G [N] and the coefficient of c [N]/s be b [N+1] to be led port ob [N] by port i [N].Coefficient is that the weighting circuit 56 of as0 forms a weight path, to be led port ob [N], to carry out bypass for integrator G [N] by port i [N].N is less than for k, if wish, the secondary signal that one first signal of port oa [k] and last integrator G [N] integration go out combines mutually, the first signal from port oa [k] is directed to port ob [N-1] by the forward path that only extends front portion 50A, make this first signal can through via mixing part 52A in weighting circuit 56 and be directed to port ob [N], so that the secondary signal that sum-product intergrator G [N] exports combines mutually.
Utilize integrator G [1] to G [N] and each forward path, loop filter 32A can provide N the rank transfer function with N number of limit.Front portion 50A can provide (N-1) secondary transfer function, and is multiplied with the transfer function of mixing part 52A.Be similar to the mixing part 52 in Fig. 3, because mixing part 52A can realize with single amplifier, therefore loop filter 32A only needs N number of amplifier just can realize, but not (N+1) is individual.Please refer to Fig. 6, what it was illustrated is the embodiment that the present invention realizes loop filter 32A.In front portion 50A, the path of integration available amplifier op [1] to op [N-1] in Fig. 5, electric capacity realize R [2] to R [N] with resistance C [1] to C [N-1]; Coefficient is that the forward path of a [j] can be realized Rf [j] by resistance, and coefficient is that the secondary path of g [i] can be realized Rr [i] by resistance.Mixing part 52A available capacity realizes a Rs and amplifier op [N] C [N], resistance.For k=1 to N, the corresponding differential node of the port i [k] in Fig. 5, oa [k] and ob [k] difference is to i [k] p and i [k] n, oa [k] p and oa [k] n and ob [k] p and ob [k] n.For k=2 to N, node i [k] p and i [k] n is couple nodes ob [k-1] n and ob [k-1] p respectively.
For k=1 to (N-1), the positive input terminal of amplifier G [k], negative input end, positive output end and negative output terminal be couple nodes i [k] p, i [k] n, oa [k] p and oa [k] n respectively; Electric capacity is coupled between node i [k] p and oa [k] n to one of them of C [k], and electric capacity is then coupled between node i [k] n and oa [k] p to another in C [k]; Resistance is coupled between node oa [k] p and ob [k] p to one of them of R [k+1], and resistance is then coupled between node oa [k] n and ob [k] n another in R [k+1].In mixing part 52A, electric capacity is coupled between node i [N] p and ob [N] n to one of them and the resistance of C [N] to one of them of Rs, and electric capacity is then coupled between node i [N] n and ob [N] p another in Rs another in C [N] and resistance.
In each forward path, resistance is coupled between node oa [kjL] p and ob [kjH] n to one of them of Rf [j], and resistance is then coupled between node oa [kjL] n and ob [kjH] p another in Rf [j].For example, for realizing the coefficient a [1] of Fig. 5, a resistance Rf [1] is coupled between node oa [1] p and ob [N-1] n, and another resistance Rf [1] is then coupled between node oa [1] n and ob [N-1] p.In each secondary path, resistance is coupled between node oa [kiH] n and ob [kiL] n to one of them of Rr [i], and another is then coupled between node oa [kiL] p and ob [kiH] p.
Though the sigma-delta modulator 30 in Fig. 3 have employed one continuous time loop filter 32, sigma-delta modulator 30 also can be a kind of hybrid sigma-delta modulator mixing continuous time and discrete time process.Digital to analog converter 38(is shown in Fig. 3, Fig. 4 and Fig. 6) dynamic element matching circuit 36(Fig. 3 can be worked in coordination with), using by digital signal v (n) converted back into analog signal uf0 (t) as feedback.Though the sigma-delta modulator 30 in Fig. 3 have employed single digital to analog converter 38 so that an analog signal is fed back to loop filter, sigma-delta modulator 30 also can comprise the digital to analog converter of multiple feedback.For example, with reference to figure 3, a digital to analog converter set up, with one arrange in pairs or groups set up dynamic element matching circuit (words if necessary; Both all non-figure go out), can be arranged between quantizer 34 and port i2 or i3, so that signal v (n) is converted to analog signal, and feed back to the port i2 of integrator 40b or the port i3 of integrator 40c.
In summary, the invention provides a kind of loop filter of resistance-type feedforward topology of improvement, can be applicable in the sigma-delta modulator of continuous time.In the loop filter of resistance-type feedforward topology, N number of integrator G [1] is sequentially connected in series to G [N], and last integrator G [N] is equipped with a weight path, to form a multi-functional mixing part, can carry out integration and linear combination; One first signal that a certain integrator G [k] exports if expect mutually combines with the secondary signal that integrator G [N] exports and is added (k is less than N), then the first signal can be fed forward to weight path, makes the first signal be able to combine with secondary signal.Because integrator G [1] to G [N-1] can realize with single amplifier respectively with the integrator G [N] mixing part, therefore altogether only need N number of amplifier, instead of (N+1) is individual.So, the hardware complexity of loop filter and sigma-delta modulator, power consumption, layout area just can effectively reduce.In one embodiment, sigma-delta modulator of the present invention can be applicable to a fundamental frequency demodulator, with a radio-frequency tuner (RF tuner) Collaboration.Radio-frequency tuner receives a radiofrequency signal and is fallen and transfers the I signal of homophase and the Q signal of orthorhombic phase to.In fundamental frequency demodulator, I signal and Q signal just can give digitlization with two sigma-delta modulators of the present invention respectively.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; any person skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, the scope that therefore protection scope of the present invention ought define depending on claims of the present invention is as the criterion.
Claims (15)
1. a sigma-delta modulator, is characterized in that, comprises: a front portion and a mixing part;
Wherein this front portion comprises:
One leading portion integrator, produces a first integral signal in order to carry out integration to an internal signal; And
One forward path, also produce a feed-forward signal according to this in order to this internal signal of weighting, wherein this front portion is in order to produce a summation signals according to this first integral signal, and combines to produce a front signal to this summation signals and this feed-forward signal; And
This mixing part couples this front portion, and in order to this front signal of weighting to produce a weighted signal, this front signal of integration to produce a second integral signal, and combines this weighted signal and this second integral signal to produce a filtering signal.
2. sigma-delta modulator as claimed in claim 1, is characterized in that:
This front portion also comprises a leading portion input port and a leading portion output port, and respectively in order to receive an input signal and to export this front signal, and this front portion is also for producing this internal signal according to this input signal;
This forward path comprises a feedforward input port and a feed forward output mouth, respectively in order to receive this internal signal and to export this feed-forward signal;
This leading portion integrator comprises an integration input port and an integration output port, respectively in order to receive this internal signal and to export this first integral signal;
Wherein, this feedforward input port couples this integration input port, and this feed forward output mouth is coupled between this integration output port and this leading portion output port.
3. sigma-delta modulator as claimed in claim 2, it is characterized in that, this front portion also comprises one second leading portion integrator, is coupled between this integration output port and this leading portion output port;
Wherein this front portion is used for according to the integration to this first integral signal and produces this summation signals.
4. sigma-delta modulator as claimed in claim 3, it is characterized in that, this second leading portion integrator is coupled between this integration output port and this feed forward output mouth, in order to carry out integration to this first integral signal to produce a third integral signal;
Wherein, this front portion also provides this summation signals according to this third integral signal.
5. sigma-delta modulator as claimed in claim 4, it is characterized in that, this front portion also comprises one second forward path, is coupled between this feedforward input port and this integration output port, also produces one second feed-forward signal according to this in order to this internal signal of weighting;
Wherein, this front portion also provides this summation signals according to the combination of this first integral signal and this second feed-forward signal.
6. sigma-delta modulator as claimed in claim 3, it is characterized in that, this the second leading portion integrator is coupled between this feed forward output mouth and this leading portion output port, in order to the combination of this feed-forward signal of integration and this summation signals, and produces a third integral signal according to this;
Wherein this front portion also provides this front signal according to this third integral signal; And this front portion also according to the combination of this summation signals and this feed-forward signal integration and produce this front signal.
7. sigma-delta modulator as claimed in claim 1, is characterized in that, also comprise:
One quantizer, is coupled to this mixing part, in order to quantize this filtering signal and to provide a quantized signal according to this; And
One digital to analog converter, is coupled in this quantizer, in order to change this quantized signal to provide a feedback signal;
Wherein this front portion more provides this internal signal according to this feedback signal.
8. sigma-delta modulator as claimed in claim 1, is characterized in that:
This front portion also for the combination of integration one second internal signal and one the 3rd internal signal to produce one the 4th integrated signal;
Wherein this front portion also comprises a secondary path, and in order to weighting the 4th integrated signal to provide an auxiliary signal, and this front portion also produces the 3rd internal signal according to this auxiliary signal;
Wherein the combination of this this internal signal of leading portion integrator integration and this auxiliary signal is to produce this first integral signal, and this first integral signal of this front portion weighting is to provide the 3rd internal signal; And this second internal signal i.e. this feed-forward signal.
9. sigma-delta modulator as claimed in claim 1, is characterized in that, this mixing part comprises:
One back segment integrator, in order to this front signal of integration; And
One weight path, in order to this front signal of weighting.
10. a sigma-delta modulator, is characterized in that, comprises:
One path of integration, comprise multiple internal port orderly and a preset number leading portion integrator, each leading portion integrator is in order to be directed to the internal port of another high order in described internal port via in described internal port;
One first forward path, in order to be directed to the internal port of another the higher order in described internal port via in described internal port, and bypass is in this preset number leading portion integrator; And
One mixing part, comprises an input port, an output port, a back segment integrator and a weight path; This input port couples one in described internal port, and this back segment integrator is in order to be directed to this output port via this input port, and this weight path is in order to be directed to this output port by this input port, and this back segment integrator of bypass.
11. sigma-delta modulators as claimed in claim 10, is characterized in that, also comprise:
One second forward path, in order to be directed to the internal port of another higher order in described internal port by described internal port.
12., as the sigma-delta modulator of claim 10, is characterized in that, also comprise:
One secondary path, in order to be directed to the lower internal port of an order by described internal port.
13. sigma-delta modulators as claimed in claim 12, it is characterized in that, this secondary path leads one first internal port in described internal port, and the signal that this path of integration is also directed to this first internal port for the signal and being directed to this first internal port via this secondary path by via this path of integration combines.
14. sigma-delta modulators as claimed in claim 10, is characterized in that, also comprise:
One quantizer, couples this output port, in order to quantize the signal of this output port; And
One digital to analog converter, carries out digital-to-analogue conversion by from this quantizer to the signal of the internal port of in described internal port.
15. sigma-delta modulators as claimed in claim 10, it is characterized in that, this first forward path is directed to one second internal port in described internal port, and the signal that this path of integration is also directed to this second internal port for the signal and being directed to this second internal port via this forward path by via this path of integration combines.
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| US61/549,922 | 2011-10-21 | ||
| US13/450,866 | 2012-04-19 | ||
| US13/450,866 US8552894B2 (en) | 2011-06-15 | 2012-04-19 | Sigma-delta modulator having a feed-forward path and a hybrid portion |
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| US9030342B2 (en) * | 2013-07-18 | 2015-05-12 | Analog Devices Global | Digital tuning engine for highly programmable delta-sigma analog-to-digital converters |
| US9537497B2 (en) * | 2015-05-14 | 2017-01-03 | Mediatek Inc. | Continuous time delta sigma modulator, analog to digital converter and associated compensation method |
| US10327659B2 (en) * | 2016-11-13 | 2019-06-25 | Analog Devices, Inc. | Quantization noise cancellation in a feedback loop |
| US10361711B1 (en) * | 2018-12-13 | 2019-07-23 | Analog Devices Global Unlimited Company | Stub filters to improve blocker tolerance in continuous-time residue generation analog-to-digital converters |
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| CN101069352A (en) * | 2004-11-16 | 2007-11-07 | 皇家飞利浦电子股份有限公司 | Continuous-time sigma-delta analog-to-digital converter with non-invasive filter(s) for immunity preservation against interferers. |
| CN101375507A (en) * | 2006-01-25 | 2009-02-25 | Nxp股份有限公司 | Continuous-time sigma-delta analog-to-digital converter with capacitor and/or resistance digital self-calibration means for RC spread compensation |
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| CN101069352A (en) * | 2004-11-16 | 2007-11-07 | 皇家飞利浦电子股份有限公司 | Continuous-time sigma-delta analog-to-digital converter with non-invasive filter(s) for immunity preservation against interferers. |
| CN101375507A (en) * | 2006-01-25 | 2009-02-25 | Nxp股份有限公司 | Continuous-time sigma-delta analog-to-digital converter with capacitor and/or resistance digital self-calibration means for RC spread compensation |
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