CN102832223B - Wafer thinning method - Google Patents
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- CN102832223B CN102832223B CN201210328714.6A CN201210328714A CN102832223B CN 102832223 B CN102832223 B CN 102832223B CN 201210328714 A CN201210328714 A CN 201210328714A CN 102832223 B CN102832223 B CN 102832223B
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Abstract
The invention provides a wafer thinning method, which is characterized in that selective corrosive liquid is utilized for etching an crystal edge oxidization layer of a device wafer, wherein the etching rate of the selective corrosive liquid on the oxidization layer is larger than the etching rate on the device wafer, so that the height difference of the device wafer and a crystal edge oxidization layer surface of the device wafer by respectively utilizing SPINETCH-D (mixed solution of phosphoric, nitric acid, sulfuric acid and hydrofluoric acid) and HNA (mixed solution of hydrofluoric acid, nitric acid and acetic acid) to perform two etching process on the back surface of the device wafer and the crystal edge oxidization layer of the device wafer can be overcome. Meanwhile, by utilizing the chemical process, the problem by utilizing the physical process (i.e. cutting process) that the utilization rate of the produced device wafer is low and the quality and the reliability of the device wafer are low can be avoided, and the quality of a finally formed image sensor can be improved.
Description
Technical field
The present invention relates to field of IC technique, the wafer thining method particularly in a kind of backside-illuminated sensor manufacture process.
Background technology
Imageing sensor grows up on photoelectric technology basis, so-called imageing sensor, can experience optical image information exactly and convert thereof into the transducer of usable output signal.Imageing sensor can improve the visual range of human eye, people are made to see the microcosmos that naked eyes cannot be seen and macrocosm, see that people temporarily cannot arrive place's occurrence, see the various physics, the chemical change process that exceed naked eyes visual range, the generation evolution of life, physiology, pathology, etc.Visual picture transducer plays very important effect in the culture of people, physical culture, production, life and scientific research.Can say, modern humans's activity cannot leave imageing sensor.
According to the difference of the position of reception light, imageing sensor can be divided into positive illuminated (image) transducer of tradition and back-illuminated type (image) transducer, wherein, backside-illuminated sensor is compared with the positive illuminated sensor of tradition, maximum optimization part is exactly by the structural change of element internal, direction turned by element by photosensitive layer, luminous energy is allowed to enter from back side direct projection, avoid in the positive illuminated sensor structure of tradition, light can be subject to the impact of circuit between lenticule and photodiode and transistor.In addition, the both sides or below of imageing sensor (chip) are separated into photosensitive irrelevant cabling and photodiode, so not only can increase photoelectric cell exposure area (aperture opening ratio increase), and reduce the loss of light through wiring layer, thus significantly improve the usefulness of light, greatly improve the photosensitive effect under low-light conditions.
For backside-illuminated sensor, effectively photo-sensitive cell can be arrived in order to make the light inciding its back side, in the manufacture process of backside-illuminated sensor, carrying out slimming process for wafer (i.e. the base material of bearing function element) is a necessary processing step, and the quality of slimming process directly will affect the reliability of the backside-illuminated sensor finally formed.
Please refer to Fig. 1 a ~ 1e, it is the device profile schematic diagram in existing wafer thining method.Concrete,
As shown in Figure 1a, provide device wafers 10, first is performed to device wafers 10 and shears technique;
As shown in Figure 1 b, forming oxide layer 11 on device wafers 10 surface through shearing technique, at this, forming oxide layer 11 in the front of described device wafers 10 and crystal edge;
As illustrated in figure 1 c, cmp (CMP) technique is performed to the oxide layer of device wafers 10, device wafers 10 and carrying wafer 12 are fitted, wherein portion of oxide layer 11 is between described device wafers 10 and carrying wafer 12, then the back side of device wafers 10 is ground (Grinding), realize mechanical reduction;
As shown in Figure 1 d, utilize SPINETCH-D(and phosphoric acid respectively, nitric acid, the mixed liquor of sulfuric acid and hydrofluoric acid) and HNA(and hydrofluoric acid, the mixed liquor of nitric acid and acetic acid) twice etching technics is performed to the crystal edge oxide layer 11 of described device wafers 10 and device wafers 10, thus thinning device wafers 10, at this, because SPINETCH-D and HNA is very large for the etch rate difference of device wafers 10 and oxide layer 11, thus, to device wafers 10 and (crystal edge of device wafers 10) oxide layer 11 surface be caused to have difference in height after etching technics, the existence of this difference in height will cause the less reliable of subsequent technique,
For this reason, please continue to refer to Fig. 1 e, second is performed to device wafers 10 and shears technique 13, to remove the crystal edge oxide layer 11 causing the device wafers 10 of difference in height, meanwhile, in order to ensure the effective removal to this part oxide layer 11, inevitably remove part device wafers 10.
At this, can the difference in height problem on abatement device wafer 10 and oxide layer 11 surface although shear technique 13 by second, it brings following several defect:
1., owing to eliminating part of devices wafer 10, namely waste the utilization of the device wafers 10 to this part, thus reduce the utilance for device wafers 10, add production cost;
2. shear technique by a large amount of surface particles of generation and stress, thus, will quality and the reliability of device wafers 10 be reduced.
Summary of the invention
The object of the present invention is to provide a kind of wafer thining method, to solve in the process of the difference in height on abatement device wafer and oxide layer surface in prior art, reduce the utilance for device wafers and reduce the quality of device wafers and the problem of reliability.
For solving the problems of the technologies described above, the invention provides a kind of wafer thining method, comprising:
Device wafers is provided, and crystal edge shearing technique is performed to described device wafers;
Oxide layer is formed in device wafers front and crystal edge;
Device wafers and carrying wafer are fitted, wherein the frontside oxide layer of device wafers is between described device wafers and carrying wafer;
The crystal edge oxide layer of SPINETCH-D and HNA to the device wafers back side and device wafers is utilized to perform twice etching technics respectively;
Utilize selective etching liquid to perform etching technics to the crystal edge oxide layer of described device wafers, wherein, the etch rate of described selective etching liquid to oxide layer is greater than the etch rate to device wafers.
Optionally, in described wafer thining method, after device wafers front and crystal edge form oxide layer, before device wafers and carrying wafer are fitted, also comprise:
CMP is performed to device wafers oxide layer.
Optionally, in described wafer thining method, after wafer fit with carrying by device wafers, utilize SPINETCH-D and HNA to before the crystal edge oxide layer execution twice etching technics of the device wafers back side and device wafers respectively, also comprise:
Grinding technics is performed to the device wafers back side.
Optionally, in described wafer thining method, described selective etching liquid is hydrofluoric acid solution.
Optionally, in described wafer thining method, described hydrofluoric acid solution to be mass percent concentration be 49% hydrofluoric acid solution.
Optionally, in described wafer thining method, the technological temperature utilizing selective etching liquid to perform etching technics to the crystal edge oxide layer of described device wafers is 45 DEG C.
Optionally, in described wafer thining method, the process time utilizing selective etching liquid to perform etching technics to the crystal edge oxide layer of described device wafers is 20 seconds ~ 60 seconds.
Optionally, in described wafer thining method, utilize selective etching liquid to perform in etching technics the crystal edge oxide layer of described device wafers, the thickness of the oxide layer of removal is 1.5um ~ 2um.
Optionally, in described wafer thining method, utilize the crystal edge oxide layer of SPINETCH-D and HNA to the device wafers back side and device wafers to perform in twice etching technics respectively, the thickness of the device wafers of removal is 15um ~ 30um.
Optionally, in described wafer thining method, the total process time utilizing SPINETCH-D and HNA to perform twice etching technics to the crystal edge oxide layer of the device wafers back side and device wafers is respectively 1.5 minutes ~ 7.5 minutes.
Optionally, in described wafer thining method, described selective etching liquid is BOE solution.
Optionally, in described wafer thining method, utilize the crystal edge oxide layer of selective etching liquid to multichip devices wafer to perform etching technics simultaneously.
Optionally, in described wafer thining method, utilizing after selective etching liquid performs etching technics to the crystal edge oxide layer of described device wafers, also utilize NH
4oH and H
2o
2mixed liquor cleans device wafers.
In wafer thining method provided by the invention, selective etching liquid is utilized to perform etching technics to the crystal edge oxide layer of described device wafers, wherein, the etch rate of described selective etching liquid to oxide layer is greater than the etch rate to device wafers, thus, compensate for and utilize the crystal edge oxide layer of SPINETCH-D and HNA to the described device wafers back side and device wafers to perform in twice etching technics respectively, the difference in height on the crystal edge oxide layer surface of device wafers and device wafers.Meanwhile, is chemical technology due to what utilize, thus the utilance avoiding the device wafers that physical technology (namely shearing technique) produces is low and the quality of device wafers and the low problem of reliability, improves the quality of the imageing sensor finally formed.
Accompanying drawing explanation
Fig. 1 a ~ 1e is the device profile schematic diagram in existing wafer thining method;
Fig. 2 is the schematic flow sheet of the wafer thining method of the embodiment of the present invention;
Fig. 3 a ~ 3e is the device profile schematic diagram in the wafer thining method of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the wafer thining method that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, utilize chemical technology to make up and utilize the crystal edge oxide layer of SPINETCH-D and HNA to the described device wafers back side and device wafers to perform in twice etching technics respectively, the difference in height on the crystal edge oxide layer surface of device wafers and device wafers, thus avoid the quality of the low and device wafers of the utilance of the device wafers utilizing physical technology (namely shearing technique) to produce in prior art and the low problem of reliability, improve the quality of the imageing sensor finally formed.
Preferably, the present invention have selected etching (corrosion) technique often used in semiconductor technology, thus, both (substantially not increasing in other words) process costs can not be increased, additional process steps can be avoided again for the injury of device wafers (because etching technics is the technique often used in semiconductor technology, its technique is very ripe, therefore, it is possible to control the use for this technique well).
Simultaneously, it should be noted that, usually with shearing technique (for the thinning process of whole wafer together in existing technique, that second shears technique) oxide layer that will be positioned at device wafers crystal edge (i.e. side surface position) removes, thus eliminates device wafers (back side) surface and the surperficial problem with difference in height of (crystal edge of device wafers) oxide layer.And in wafer thining method provided by the invention, make use of one chemical technology, it fundamentally takes means (mode) unlike the prior art, thus fundamentally avoid in the process of the difference in height on abatement device wafer and oxide layer surface in prior art, reduce the utilance for device wafers and reduce the quality of device wafers and the problem of reliability.
In addition, in term of the present invention, the wafer that " device wafers " refers to be formed with device or the wafer referring to for the formation of device, namely it is a kind of wafer, and it forms device; And " carrying wafer " refers to the wafer carrying device wafers, especially, carry device wafers and carry out reduction process to make device wafers.
Concrete, please refer to Fig. 2, it is the schematic flow sheet of the wafer thining method of the embodiment of the present invention.As shown in Figure 2, described wafer thining method comprises the steps:
S20: device wafers is provided, and crystal edge shearing technique is performed to described device wafers;
S21: form oxide layer in device wafers front and crystal edge;
S22: device wafers and carrying wafer are fitted, wherein the frontside oxide layer of device wafers is between described device wafers and carrying wafer;
S23: utilize the crystal edge oxide layer of SPINETCH-D and HNA to the device wafers back side and device wafers to perform twice etching technics respectively;
S24: utilize selective etching liquid to perform etching technics to the crystal edge oxide layer of described device wafers, wherein, the etch rate of described selective etching liquid to oxide layer is greater than the etch rate to device wafers.
In order to further illustrate the wafer thining method of the present embodiment, subsequent, be explained in conjunction with the device profile map formed in wafer reduction process process.Concrete, please refer to Fig. 3 a ~ 3e, it is the device profile schematic diagram in the wafer thining method of the embodiment of the present invention.
As shown in Fig. 3 a-1, provide device wafers 30, described device wafers 30 is silicon materials wafer; As shown in Fig. 3 a-2, crystal edge is performed to described device wafers 30 and shears technique (namely crystal edge/the crystal round fringes of device wafers 30 is performed and shear technique).
Then, as shown in Figure 3 b, oxide layer 31(is formed concrete on device wafers 30 surface through shearing technique, oxide layer 31 is formed in the front of described device wafers 30 and crystal edge, namely the frontside oxide layer 31 of device wafers 30 and the crystal edge oxide layer 31 of device wafers 30 is formed), preferably, described oxide layer 31 can be silicon oxide layer, and it is formed by chemical vapor deposition (CVD) technique.Concrete, the device wafers 30 shearing technique through crystal edge can be inserted chemical vapor deposition process chamber room, wherein, facing up of described device wafers 30, thus, by the surface in device wafers 30 being formed an oxide layer 31 after chemical vapor deposition method, this oxide layer 31 covers front and the crystal edge of described device wafers 30.The device that described device wafers 30 has been formed can be protected by described oxide layer 31, prevent subsequent technique for the injury of established device, thus improve the quality of products.Preferably, the thickness of described oxide layer 31 is 1.5um ~ 2um.Then, CMP(cmp is carried out to the oxide layer 31 of described device wafers 30) technique, make its planarization.
After CMP is performed to described device wafers 30 surface oxide layer (namely comprising frontside oxide layer and the crystal edge oxide layer of device wafers 30), described device wafers 30 and carrying wafer 32 are fitted, wherein, portion of oxide layer 31 is (concrete between described device wafers 30 and carrying wafer 32, the frontside oxide layer 31 of described device wafers 30 is between described device wafers 30 and carrying wafer 32), namely described device wafers 30 is bonded with described carrying wafer 32 by described oxide layer 31, thus, described oxide layer 31 can protect the device that described device wafers 30 is formed with, prevent adhesion technique from damaging the device in device wafers 30.At this, described carrying wafer 32 is also formed with oxide layer, i.e. oxide layer 33, when fitting, described oxide layer 33 is between device wafers 30 and carrying wafer 32.
Then, as shown in Figure 3 c, grinding (Grinding) technique is performed to described device wafers 30, concrete, perform grinding (Grinding) technique to the back side of described device wafers 30, namely one of described device wafers 30 is formed with oxide layer 31, on the surface at this, another surface relative to the surface being formed with oxide layer 31 performs grinding (Grinding) technique, and described grinding (Grinding) technique stops at the thickness position that device wafers 30 also remains 20um ~ 40um.Can rapid thinning described device wafers 30 by this grinding (Grinding) technique.
Then, as shown in Figure 3 d, utilize the mixed liquor of SPINETCH-D(and phosphoric acid, nitric acid, sulfuric acid and hydrofluoric acid respectively) and the mixed liquor of HNA(and hydrofluoric acid, nitric acid and acetic acid) to perform twice etching technics to described device wafers 30 and oxide layer 31 (concrete, twice etching technics is performed to the back side of described device wafers 30 and the crystal edge oxide layer 31 of device wafers 30), thus thinning device wafers 30.That is, at this, perform twice etching technics, be respectively: utilize SPINETCH-D to perform etching technics to described device wafers 30 and oxide layer 31; And utilize HNA to perform etching technics to described device wafers 30 and oxide layer 31.The requirement of device wafers 30 reduction process can be met by this twice etching technics, namely reach and need thinning size, meanwhile, make device wafers 30 surface smoothness etc. higher.
Common, the thickness of the device wafers 30 removed by this twice etching technics is 15um ~ 30um.Preferably, this twice etching technics is generally silica to oxide layer 31() rate of etch be to device wafers 30(silicon) rate of etch 1/80 ~ 1/100; Wherein, for device wafers 30(silicon) rate of etch between 4um ~ 10um per minute; The total etch period of this twice etching technics is 1.5 minutes ~ 7.5 minutes, such as, can be 3 minutes, 4 minutes, 5.5 minutes etc. according to different reduced thickness demands.In the process, also can remove some oxide layers 31 to a certain extent, the thickness of usual removed oxide layer 31 is 0.15um ~ 0.38um.
Then, as shown in Figure 3 e, utilize the crystal edge oxide layer 31 of selective etching liquid to described device wafers 30 to perform etching technics, wherein, described selective etching liquid to the etch rate of oxide layer 31 much larger than the etch rate to device wafers 30.Concrete, by the crystal edge oxide layer 31(of described device wafers 30 and device wafers 30) immerse and be equipped with in the container of selective etching liquid, to carry out selective etching technique.In the process, certain corrosiveness can be produced to device wafers 30, but due to the characteristic of selective etching liquid, mainly the crystal edge oxide layer 31 of device wafers 30 be corroded.
In the present embodiment, the crystal edge oxide layer 31 of hydrofluoric acid solution to described device wafers is utilized to perform etching technics.In other embodiments of the invention, the crystal edge oxide layer 31 of other corrosive liquids to described device wafers also can be utilized to perform etching technics, such as BOE solution.In this step etching technics, portion of oxide layer 33 can be removed simultaneously, namely remove the portion of oxide layer 33 that carrying wafer 32 is formed.
Preferably, utilize mass percent concentration be 49% hydrofluoric acid solution perform this etching technics, because the percent concentration hydrofluoric acid solution that is 49% is easy to obtain and use and etching rate is high in the industry, thus, just can reduce process costs.Further, utilize mass percent concentration be 49% hydrofluoric acid solution to perform the technological temperature of etching technics be 45 DEG C, the process time is 20 seconds ~ 60 seconds.Due to the technological temperatures of 45 DEG C to be percent concentration be 49% a technological temperature often using in semiconductor processing of hydrofluoric acid solution, thus, the frequent adjustment of technological temperature can be avoided, simplified manufacturing technique.Mass percent concentration be the hydrofluoric acid solution of 49% under the technological temperature of 45 DEG C, for oxide layer 31(silica) rate of etch be about 2um ~ 5um, therefore, preferably, the process time of this step etching technics is 20 seconds ~ 60 seconds.
Certainly, in other embodiments of the invention, also can with the hydrofluoric acid solution of other concentration, such as mass percent concentration is the hydrofluoric acid solution of 30%, 35%, 40%, 45%, 50%, 55% or 60%; Meanwhile, also can perform etching technics under other technological temperatures, such as technological temperature is 35 DEG C, 40 DEG C, 50 DEG C, 55 DEG C or 60 DEG C etc.
Etching technics is performed by the above-mentioned crystal edge oxide layer 31 of hydrofluoric acid to device wafers that utilize, the oxide layer 31 exposed can be removed (oxide layer 31 by device wafers 30 crystal edge place is removed), thus, just abatement device wafer 30 and oxide layer 31 surface the problem of difference in height can be had.Because the crystal edge oxide layer 31 of device wafers 30 is removed, obvious, also would not there is the device wafers 30(back side) there is the problem of surface height difference with crystal edge oxide layer.
At this, the thickness of the oxide layer 31 removed is about 1.5um ~ 2um(and is about 1.12um ~ 1.85um more accurately), when the thickness of the oxide layer 31 of required removal very thin and for the rate of etch of oxide layer 31 much larger than rate of etch for device wafers 30, can ensure not only to eliminate oxide layer 31, but also not injure device wafers 30, thus improve the reliability of wafer reduction process.
Further, in concrete technical process, can hydrofluoric acid solution be all formed with oxide layer 31 on multichip devices wafer 30 and oxide layer 31(and every sheet device wafers 30) perform etching technics simultaneously, thus, can process efficiency be improved, reduce manufacturing cost.Concrete, be all formed with oxide layer 31 by every for multichip devices wafer 30(sheet device wafers 30) be placed in a hydrofluoric acid solution groove, normally 50 simultaneously.
In addition, after the crystal edge oxide layer 31 utilizing selective etching liquid to described device wafers performs etching technics, also NH can be utilized
4oH and H
2o
2mixed liquor cleans device wafers 30, namely makes described device wafers 30 (fill NH in groove through SC1 groove again
4oH and H
2o
2mixed liquor).By utilizing NH
4oH and H
2o
2mixed liquor cleans device wafers 30, the particle that after can controlling and remove hf etching technique, described device wafers 30 surface is left, thus improves the quality of device wafers 30 further.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (13)
1. a wafer thining method, is characterized in that, comprising:
Device wafers is provided, and crystal edge shearing technique is performed to described device wafers;
Oxide layer is formed in device wafers front and crystal edge;
Device wafers and carrying wafer are fitted, wherein the frontside oxide layer of device wafers is between described device wafers and carrying wafer;
Perform twice etching technics, thinning described device wafers, described device wafers and described crystal edge oxide layer surface form a difference in height, wherein, described twice etching technics comprises: utilize the crystal edge oxide layer of the mixed liquor of phosphoric acid, nitric acid, sulfuric acid and hydrofluoric acid to the device wafers back side and device wafers to perform etching technics; And utilize the crystal edge oxide layer of the mixed liquor of hydrofluoric acid, nitric acid and acetic acid to the device wafers back side and device wafers to perform etching technics;
Selective etching liquid is utilized to perform etching technics to the crystal edge oxide layer of described device wafers, eliminate the difference in height on described device wafers and described crystal edge oxide layer surface, wherein, the etch rate of described selective etching liquid to oxide layer is greater than the etch rate to device wafers.
2. wafer thining method as claimed in claim 1, is characterized in that, after device wafers front and crystal edge form oxide layer, before device wafers and carrying wafer being fitted, also comprises:
CMP is performed to device wafers oxide layer.
3. wafer thining method as claimed in claim 1, is characterized in that, after device wafers being fitted with carrying wafer, before performing twice etching technics, also comprises:
Grinding technics is performed to the device wafers back side.
4. wafer thining method as claimed in claim 1, it is characterized in that, described selective etching liquid is hydrofluoric acid solution.
5. wafer thining method as claimed in claim 4, is characterized in that, described hydrofluoric acid solution to be mass percent concentration be 49% hydrofluoric acid solution.
6. wafer thining method as claimed in claim 5, is characterized in that, the technological temperature utilizing selective etching liquid to perform etching technics to the crystal edge oxide layer of described device wafers is 45 DEG C.
7. wafer thining method as claimed in claim 6, is characterized in that, the process time utilizing selective etching liquid to perform etching technics to the crystal edge oxide layer of described device wafers is 20 seconds ~ 60 seconds.
8. the wafer thining method as described in any one in claim 1 to 7, is characterized in that, utilize selective etching liquid to perform in etching technics the crystal edge oxide layer of described device wafers, the thickness of the oxide layer of removal is 1.5um ~ 2um.
9. the wafer thining method as described in any one in claim 1 to 7, is characterized in that, perform in twice etching technics, the thickness of the device wafers of removal is 15um ~ 30um.
10. wafer thining method as claimed in claim 9, is characterized in that, the total process time performing twice etching technics is 1.5 minutes ~ 7.5 minutes.
11. wafer thining methods as claimed in claim 1, it is characterized in that, described selective etching liquid is BOE solution.
12. wafer thining methods as described in any one in claim 1 to 7, is characterized in that, utilize the crystal edge oxide layer of selective etching liquid to multichip devices wafer to perform etching technics simultaneously.
13. wafer thining methods as described in any one in claim 1 to 7, is characterized in that, utilizing after selective etching liquid performs etching technics to the crystal edge oxide layer of described device wafers, also utilize NH
4oH and H
2o
2mixed liquor cleans device wafers.
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| CN101789371A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Cleaning method of semiconductor component |
| CN102534620A (en) * | 2010-12-08 | 2012-07-04 | 无锡华润上华科技有限公司 | Wet-process silicon etching solution for P-type wafer |
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