CN102832197B - Metal interconnect structure and forming method thereof - Google Patents
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- CN102832197B CN102832197B CN201110161470.2A CN201110161470A CN102832197B CN 102832197 B CN102832197 B CN 102832197B CN 201110161470 A CN201110161470 A CN 201110161470A CN 102832197 B CN102832197 B CN 102832197B
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Abstract
A kind of metal interconnect structure and forming method thereof, wherein the formation method of metal interconnect structure comprises: provide Semiconductor substrate, form dielectric layer on a semiconductor substrate; In described dielectric layer, form discrete metal interconnecting layer, described metal interconnecting layer surface flushes with dielectric layer surface; Metal interconnecting layer forms metal capping layers; Dielectric layer and metal capping layers form molecular sieve; Pass into reacting gas through molecular sieve to dielectric layer, remove part dielectric layer, between the metal interconnecting layer that at least one pair of is adjacent, form airspace.The technical program by forming molecular sieve on dielectric layer and metal capping layers, and pass into reacting gas through molecular sieve to dielectric layer, remove part dielectric layer, form airspace, parasitic capacitance can be reduced like this, and manufacture craft is simple, thus improve the voltage breakdown of semiconductor device and the dielectric breakdown characteristic with time correlation.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of metal interconnect structure and forming method thereof.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed, larger data storage amount and more function faster, and semiconductor chip is to more high integration future development.And the integrated level of semiconductor chip is higher, the characteristic size (CD, CriticalDimension) of semiconductor device is less.
Along with the reduction gradually of characteristic size CD, RC postpones the impact of the device speed of service more and more obvious, how to reduce RC and postpones to be one of hot issue of studying of those skilled in the art.And to solve one of method that RC postpones be exactly parasitic capacitance between reduction plain conductor.
In prior art, develop the method for multiple reduction parasitic capacitance, such as, filling porous low-K dielectric material etc. between plain conductor.But porous material is frangible, adopt the reliability of the semiconductor device of porous low-K dielectric material poor.There have been developed one in prior art and form air gap between plain conductor, to reduce dielectric constant, and then reduce the method for parasitic capacitance.The organic film of self-organizing (polymer) is such as adopted to form air gap etc., but described method and existing manufacture of semiconductor compatibility is poor, manufacture process is comparatively complicated.
On the other hand, along with semiconductor technology enters copper wiring, although copper has higher electric conductivity than other metal materials (such as aluminium etc.), but along with the continuous reduction of integrated circuit wiring width, the electromigration made in metal interconnect structure (EM) problem becomes increasingly conspicuous by higher wiring density, meanwhile, the adhesive force between existing copper metal interconnecting layer and dielectric cap is also very poor.For the problems referred to above, propose a kind of cobalt tungsten phosphorus (CoWP) material in prior art and carry out alternative existing dielectric cap, but because the dielectric layer in metal interconnect structure uses low-K dielectric material usually, so often there is voltage breakdown (VBD) and dielectric breakdown (TDDB) phenomenon with time correlation.
In the patent announcement number Chinese patent for CN1618601A, disclose a kind of copper barrier layer of electroplated CoWP composite structures, but this technical scheme does not still solve the problem.
Summary of the invention
The problem that the embodiment of the present invention solves is to provide a kind of metal interconnect structure and forming method thereof, and its technique is simple, and can reduce parasitic capacitance in metal interconnect structure and improve VBD and the TDDB characteristic of semiconductor device.
For solving the problem, the embodiment of the present invention provides a kind of formation method of metal interconnect structure, comprises the steps: to provide Semiconductor substrate, forms dielectric layer on a semiconductor substrate; In described dielectric layer, form discrete metal interconnecting layer, described metal interconnecting layer surface flushes with described dielectric layer surface; Described metal interconnecting layer forms metal capping layers; Described dielectric layer and metal capping layers form molecular sieve; Pass into reacting gas through described molecular sieve to described dielectric layer, remove part dielectric layer, between the metal interconnecting layer that at least one pair of is adjacent, form airspace.
Alternatively, described dielectric layer comprises first medium layer, the second dielectric layer be positioned on described first medium layer, removes part dielectric layer for removing the described second dielectric layer of part or removing whole described second dielectric layer.
Alternatively, the step described metal interconnecting layer forming metal capping layers comprises: the residual particles of cleaning described metal interconnecting layer surface; Described metal interconnecting layer forms metal seed layer; Described metal seed layer forms metal capping layers.
Alternatively, the material of described metal seed layer is palladium, and the method forming described metal seed layer is physical vapour deposition (PVD).
Alternatively, the material of described metal capping layers is cobalt tungsten phosphorus, and the method forming described metal capping layers is electroless deposition.
Alternatively, have regularly arranged micropore in described molecular sieve, the size of described micropore is within the scope of 1.5nm-10nm.
Alternatively, described molecular sieve is silicate or the alumino-silicate of crystalline state.
Alternatively, be oxygen or carbon dioxide through described molecular sieve to the reacting gas that described dielectric layer passes into.
Alternatively, the material of described dielectric layer is one or more the dielectric material in carbon containing, nitrogen, hydrogen.
Alternatively, the material of described metal interconnecting layer is copper.
Alternatively, passing into reacting gas through described molecular sieve to described dielectric layer, removing part dielectric layer, form airspace between the metal interconnecting layer that at least one pair of is adjacent after, also comprise step: on described molecular sieve, form interlayer dielectric layer.
The embodiment of the present invention also provides a kind of metal interconnect structure, comprises Semiconductor substrate; Be positioned at the dielectric layer in Semiconductor substrate; Part is positioned at the discrete metal interconnecting layer of described dielectric layer, has airspace between at least one pair of adjacent metal interconnecting layer; Be positioned at the metal capping layers on described metal interconnecting layer; Be positioned at the molecular sieve on described metal capping layers.
Alternatively, described dielectric layer comprise first medium layer, the second dielectric layer be positioned on described first medium layer.
Optionally, the material of described metal capping layers is cobalt tungsten phosphorus, and the method forming described metal capping layers is electroless deposition.
Alternatively, described molecular sieve is silicate or the alumino-silicate of crystalline state.
Alternatively, the material of described second dielectric layer is one or more the dielectric material in carbon containing, nitrogen, hydrogen.
Alternatively, the material of described metal interconnecting layer is copper.
Alternatively, also comprise: be positioned at the interlayer dielectric layer on molecular sieve.
Compared with prior art, the technical program has the following advantages:
By forming molecular sieve on dielectric layer and metal capping layers, and passing into reacting gas (oxygen or carbon dioxide) through molecular sieve to dielectric layer, removing part dielectric layer, form airspace, its manufacture craft is simple.
Further, utilize molecular sieve between part metals interconnection layer, form space interval and not only can reduce parasitic capacitance, also improve VBD and the TDDB characteristic of semiconductor device, thus improve the reliability of semiconductor device.
In metal interconnect structure, use CoWP material to replace dielectric material to form metal capping layers, improve the problems of electromigration in metal interconnecting layer.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the embodiment of a kind of metal interconnection structure formation method of the present invention;
Fig. 2 to Fig. 7 is the cross-sectional view that the present invention forms the specific embodiment of metal interconnect structure.
Embodiment
Inventor finds in existing metal interconnect structure, and along with the continuous reduction of integrated circuit wiring width, the electromigration made in metal interconnect structure (EM) problem becomes increasingly conspicuous by higher wiring density; Simultaneously, adhesive force between existing metal interconnecting layer and dielectric cap is also very poor, propose a kind of cobalt tungsten phosphorus (CoWP) material in prior art and carry out alternative existing dielectric cap, but because the dielectric layer in metal interconnect structure uses low-K dielectric material usually, so often there is voltage breakdown (VBD) and dielectric breakdown (TDDB) phenomenon with time correlation.
For the problems referred to above, inventor, through research, provides a kind of metal interconnect structure and forming method thereof, between metal interconnecting layer, airspace is formed by molecular sieve, manufacture craft is simple, and can reduce parasitic capacitance phenomenon, improves VBD and the TDDB characteristic of semiconductor device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
First, with reference to the schematic flow sheet of the embodiment of a kind of metal interconnection structure formation method of the present invention shown in figure 1.Particularly, as shown in Figure 1, comprise the steps:
Step S1: provide Semiconductor substrate, forms dielectric layer on a semiconductor substrate;
Step S2: form discrete metal interconnecting layer in described dielectric layer, described metal interconnecting layer surface flushes with dielectric layer surface;
Step S3: form metal capping layers on metal interconnecting layer;
Step S4: form molecular sieve on dielectric layer and metal capping layers;
Step S5: pass into reacting gas to dielectric layer through molecular sieve, removes part dielectric layer, forms airspace;
Step S6: form interlayer dielectric layer on described molecular sieve.
Technical scheme of the present invention is further described below in conjunction with accompanying drawing and specific embodiment.
Referring to figs. 2 to the process structure schematic diagram of the specific embodiment of the formation metal interconnect structure shown in Fig. 7, and be described in conjunction with the schematic flow sheet of the embodiment shown in above-mentioned Fig. 1.
Please refer to Fig. 2, perform step S1, provide Semiconductor substrate 20, described Semiconductor substrate 20 can be monocrystalline silicon or SiGe; Also can be silicon-on-insulator (Silicononinsulator, SOI).
Then, described Semiconductor substrate 20 forms dielectric layer 21.In the present embodiment, described dielectric layer 21 comprises first medium layer 211 and second dielectric layer 212.Particularly, wherein, described first medium layer 211 is for the stop-layer in the step of the described second dielectric layer 212 of follow-up removal, and in the present embodiment, the material of described first medium layer 211 can be silicon nitride (Si
3n
4), the carborundum (NitrogenDopedSiliconCarbon, NDC) etc. of NBLoK (compound be made up of Si, C, H, N), nitrating.
Described first medium layer 211 forms second dielectric layer 212, described second dielectric layer 212 can be partially removed or all remove in subsequent step, the material that usual selection is easily removed, in the present embodiment, described second dielectric layer 212 is one or more the dielectric material in carbon containing, nitrogen, hydrogen.Particularly, such as described second dielectric layer 212 is amorphous carbon, diamond-like-carbon (Diamond-likecarbon, DLC) etc., but is not limited to above-mentioned material.
Further, after described second dielectric layer 212 is removed, its formation airspace, position place.Therefore, the thickness of described second dielectric layer 212 can be set according to the design requirement of airspace.
Please refer to Fig. 3, perform step S2, in described dielectric layer 21, form discrete metal interconnecting layer 22a, 22b and 22c, described metal interconnecting layer flushes with dielectric layer 21 (being specially second dielectric layer 212) surface.The structure of conductive plunger that metal interconnecting layer can be metal line or conductive plunger or comprise metal line and be connected with metal line.In the present embodiment, as shown in Figure 3, the conductive plunger that described metal interconnecting layer 22a with 22c only comprises metal line, metal interconnecting layer 22b comprises metal line and be connected with metal line.
Particularly, the technical process forming metal interconnecting layer is as follows: first, described second dielectric layer 212 applies the first photoresist layer (not shown), through photoetching process, the first photoresist layer defines via hole image; With the first photoresist layer for mask, along via hole image etching first medium layer 211 and second dielectric layer 212 to exposing substrate 20, form through hole; After removing the first photoresist layer, described second dielectric layer 212 forms the second photoresist layer (not shown), through exposure imaging, the second photoresist layer defines groove figure; With the second photoresist layer for mask, along groove figure etching second dielectric layer 212, form the groove be communicated with through hole.
Further, filled conductive material in groove and through hole, in the present embodiment, described electric conducting material is copper; Then, the electric conducting material of described second dielectric layer 212 excess surface is removed by the mode of chemico-mechanical polishing (CMP), to exposing described second dielectric layer 212, thus form metal interconnecting layer 22a, 22b, 22c, wherein trench portions correspondence forms metal line, throughhole portions correspondence forms conductive plunger.The surface of described metal interconnecting layer 22a, 22b, 22c flushes with second dielectric layer 212 surface.
It should be noted that, in practical application, the method forming metal interconnecting layer is not limited thereto, such as, except above-mentioned technique, in second dielectric layer 212, first can also form groove, then in first medium layer 211 with second dielectric layer 212, form the through hole be communicated with groove.
Please refer to Fig. 4, perform step S3, metal interconnecting layer 22a, 22b and 22c are formed metal capping layers 23.In the present embodiment, the material of described metal capping layers 23 is cobalt tungsten phosphorus (CoWP).
Particularly, the technique forming described metal capping layers 23 comprises the steps:
First, the residual particles on clean metal interconnection layer 22a, 22b, 22c surface.Owing to removing unnecessary electric conducting material by chemico-mechanical polishing (CMP) in previous technique, residual abrasive grains may be had at process of lapping and be attached to metal interconnecting layer 22a, 22b, 22c surface, therefore the residual particles on clean metal interconnection layer 22a, 22b, 22c surface is needed, such as, residual particles can be cleaned by alkaline reagent.
Then, described metal interconnecting layer 22a, 22b, 22c form metal seed layer (not shown).In the present embodiment, the material of described metal seed layer is palladium (Pd), and the method forming described metal seed layer is physical vapour deposition (PVD).The effect of described metal seed layer is that subsequent metal cap layer can be attached on metal interconnecting layer 22a, 22b, 22c better.
Then, described metal seed layer forms metal capping layers 23.In the present embodiment, the material of described metal capping layers 23 is cobalt tungsten phosphorus (CoWP), and the method forming described metal capping layers is electroless deposition.
Please refer to Fig. 5, perform step S4, dielectric layer 21 and metal capping layers 23 form molecular sieve 24.In the present embodiment, described molecular sieve is silicate or the alumino-silicate of crystalline state.Have regularly arranged micropore in described molecular sieve 24, in the present embodiment, the size of described micropore is within the scope of 1.5nm-10nm.
Particularly, the step forming molecular sieve 24 comprises: first, spin coating reaction material on the surface of described second dielectric layer 212 and metal capping layers 23, described reaction material comprises: silicon-containing compound (waterglass, Ludox etc.), aluminum contained compound (hydrated alumina, aluminium salt etc.), alkali (NaOH, potassium hydroxide etc.) and water; Heating is carried out to the reaction material of described spin coating and separates out molecular sieve crystal, be i.e. the silicate of crystalline state or alumino-silicate; Finally wash away other reactants.It should be noted that, in actual applications, the method forming molecular sieve 24 is not limited thereto.Further, more composition materials about molecular sieve and structure can references: " synthesis and characterization of Novel Mesoporous molecular sieve-MCM41 " of chemistry circular (the 3rd phase in 1999).
Please refer to Fig. 6, perform step S5, pass into reacting gas through molecular sieve 24 to dielectric layer 21, remove part dielectric layer 21, form airspace.Alternatively, the reacting gas wherein passed into is oxygen or carbon dioxide.
In the present embodiment, the material of described second dielectric layer 212 comprises one or more the dielectric material in carbon, nitrogen, hydrogen, correspondingly, these materials above-mentioned and oxygen reaction can form gas (such as carbon dioxide, nitrogen dioxide, steam etc.), easy removal, thus in the formation airspace, space 25 that described second dielectric layer 102 occupies originally.
Particularly, pass into high-octane oxygen gas plasma through described molecular sieve 24 to dielectric layer 21, described high-octane oxygen gas plasma, by the micropore in molecular sieve 24, arrives face, second dielectric layer 212 place, and react with second dielectric layer 212, remove part second dielectric layer 212.
Simultaneously, oxygen gas plasma and metal interconnecting layer 22a, 22b and 22c do not react, the second dielectric layer 212 position formation air gap 25 of such script between metal interconnecting layer, such as, between metal interconnecting layer 22a and 22b, between metal interconnecting layer 22b and 22c.Because the dielectric constant (K) of air is approximately 1, be less than the dielectric constant (be generally greater than 1 and be less than 3.9) of existing second dielectric layer 212, described air gap 25 can reduce the parasitic capacitance between metal interconnecting layer 22a, 22b and 22c, reduces RC and postpones.
It should be noted that, in the above-described embodiments, second dielectric layer 212 is partially removed, but the present invention is not restricted to this, when passing into reacting gas through described molecular sieve 24 to dielectric layer 21, described second dielectric layer 212 can be entirely removed, until expose first medium layer 211 surface.The height of the airspace of such formation is higher, can play the effect and then reduction RC delay that reduce parasitic capacitance better.
Please refer to Fig. 7, perform step S6, described molecular sieve 24 forms interlayer dielectric layer 26.
Correspondingly, the embodiment of the present invention additionally provides a kind of metal interconnect structure, and please continue to refer to Fig. 7, the metal interconnect structure described in the present embodiment comprises: Semiconductor substrate 20; Be positioned at the dielectric layer 21 in Semiconductor substrate 20, described dielectric layer 21 comprises first medium layer 211 and second dielectric layer 212, and the material of wherein said second dielectric layer 212 is one or more the dielectric material in carbon containing, nitrogen, hydrogen; Part is positioned at metal interconnecting layer 22a, 22b and 22c of described dielectric layer 21, and alternatively, the material of described metal interconnecting layer 22a, 22b and 22c is copper; And to have between at least one pair of adjacent metal interconnecting layer shown in airspace 25, Fig. 7 be all formed between metal interconnecting layer 22a, 22b and 22c to have airspace 25; Be positioned at the metal capping layers 23 on metal interconnecting layer 22a, 22b and 22c, the material of described metal capping layers 23 is cobalt tungsten phosphorus, and the method forming described metal capping layers is electroless deposition; Be positioned at the molecular sieve 24 on dielectric layer 21 and metal capping layers 23, described molecular sieve 24 is silicate or the alumino-silicate of crystalline state; Be positioned at the interlayer dielectric layer 26 on molecular sieve 24.
In sum, the technical program provides a kind of metal interconnect structure and forming method thereof, by forming molecular sieve on dielectric layer and metal capping layers, and pass into reacting gas (oxygen or carbon dioxide) through molecular sieve to dielectric layer, remove part dielectric layer, form airspace, parasitic capacitance phenomenon can be reduced like this, manufacture craft is simple, and improves the problem of the puncture voltage (VBD) that produces in semiconductor device and the dielectric breakdown (TDDB) with time correlation.On the other hand, in metal interconnect structure, use cobalt tungsten phosphorus (CoWP) material to replace dielectric material to form metal capping layers, improve the problems of electromigration in metal interconnecting layer.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (16)
1. a formation method for metal interconnect structure, is characterized in that, comprise the steps:
Semiconductor substrate is provided, forms dielectric layer on a semiconductor substrate;
In described dielectric layer, form discrete metal interconnecting layer, described metal interconnecting layer surface flushes with dielectric layer surface;
Described metal interconnecting layer forms metal capping layers, and the material of described metal capping layers is cobalt tungsten phosphorus;
Described dielectric layer and metal capping layers form molecular sieve, has regularly arranged micropore in described molecular sieve, the size of described micropore is within the scope of 1.5nm-10nm;
Pass into oxygen gas plasma through described molecular sieve to described dielectric layer, remove part dielectric layer, between the metal interconnecting layer that at least one pair of is adjacent, form airspace.
2. the formation method of metal interconnect structure according to claim 1, it is characterized in that, described dielectric layer comprises first medium layer, the second dielectric layer be positioned on described first medium layer, removes part dielectric layer for removing the described second dielectric layer of part or removing whole described second dielectric layer.
3. the formation method of metal interconnect structure according to claim 1, is characterized in that, the step that described metal interconnecting layer is formed metal capping layers comprises:
Clean the residual particles on described metal interconnecting layer surface;
Described metal interconnecting layer forms metal seed layer;
Described metal seed layer forms metal capping layers.
4. the formation method of metal interconnect structure according to claim 3, is characterized in that, the material of described metal seed layer is palladium, and the method forming described metal seed layer is physical vapour deposition (PVD).
5. the formation method of the metal interconnect structure according to claim 1 or 3, is characterized in that, the method forming described metal capping layers is electroless deposition.
6. the formation method of metal interconnect structure according to claim 1, is characterized in that, described molecular sieve is silicate or the alumino-silicate of crystalline state.
7. the formation method of metal interconnect structure according to claim 2, is characterized in that, the material of described second dielectric layer is one or more the dielectric material in carbon containing, nitrogen, hydrogen.
8. the formation method of metal interconnect structure according to claim 1, is characterized in that, the material of described metal interconnecting layer is copper.
9. the formation method of metal interconnect structure according to claim 1, it is characterized in that, reacting gas is being passed into described dielectric layer through described molecular sieve, remove part dielectric layer, form airspace between the metal interconnecting layer that at least one pair of is adjacent after, also comprise step: on described molecular sieve, form interlayer dielectric layer.
10. a metal interconnect structure, is characterized in that, comprising: Semiconductor substrate; Be positioned at the dielectric layer in Semiconductor substrate; Part is positioned at the discrete metal interconnecting layer of described dielectric layer, has airspace between at least one pair of adjacent metal interconnecting layer; Be positioned at the metal capping layers on described metal interconnecting layer, the material of described metal capping layers is cobalt tungsten phosphorus; Be positioned at the molecular sieve on described metal capping layers, have regularly arranged micropore in described molecular sieve, the size of described micropore is within the scope of 1.5nm-10nm.
The formation method of 11. metal interconnect structures according to claim 10, it is characterized in that, described dielectric layer comprises first medium layer, the second dielectric layer be positioned on described first medium layer, removes part dielectric layer for removing the described second dielectric layer of part or removing whole described second dielectric layer.
12. metal interconnect structures according to claim 10, is characterized in that, the method forming described metal capping layers is electroless deposition.
13. metal interconnect structures according to claim 10, is characterized in that, described molecular sieve is silicate or the alumino-silicate of crystalline state.
14. metal interconnect structures according to claim 11, is characterized in that, the material of described second dielectric layer is one or more the dielectric material in carbon containing, nitrogen, hydrogen.
15. metal interconnect structures according to claim 10, is characterized in that, the material of described metal interconnecting layer is copper.
16. metal interconnect structures according to claim 10, is characterized in that, also comprise: be positioned at the interlayer dielectric layer on described molecular sieve.
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| EP0685885A1 (en) * | 1994-05-27 | 1995-12-06 | Texas Instruments Incorporated | Improvements in or relating to the fabrication of semiconductor devices |
| CN1790702A (en) * | 2004-12-01 | 2006-06-21 | 国际商业机器公司 | Improved HDP-based ILD capping layer |
| CN101032015A (en) * | 2004-06-14 | 2007-09-05 | 恩索恩公司 | Capping of metal interconnects in integrated circuit electronic devices |
| CN101465318A (en) * | 2007-12-21 | 2009-06-24 | 东部高科股份有限公司 | Method for manufacturing a semiconductor device |
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| US6924222B2 (en) * | 2002-11-21 | 2005-08-02 | Intel Corporation | Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide |
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| EP0685885A1 (en) * | 1994-05-27 | 1995-12-06 | Texas Instruments Incorporated | Improvements in or relating to the fabrication of semiconductor devices |
| CN101032015A (en) * | 2004-06-14 | 2007-09-05 | 恩索恩公司 | Capping of metal interconnects in integrated circuit electronic devices |
| CN1790702A (en) * | 2004-12-01 | 2006-06-21 | 国际商业机器公司 | Improved HDP-based ILD capping layer |
| CN101465318A (en) * | 2007-12-21 | 2009-06-24 | 东部高科股份有限公司 | Method for manufacturing a semiconductor device |
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