CN102832178A - Sealing ring structure used for integrated circuit chip - Google Patents
Sealing ring structure used for integrated circuit chip Download PDFInfo
- Publication number
- CN102832178A CN102832178A CN2012103481894A CN201210348189A CN102832178A CN 102832178 A CN102832178 A CN 102832178A CN 2012103481894 A CN2012103481894 A CN 2012103481894A CN 201210348189 A CN201210348189 A CN 201210348189A CN 102832178 A CN102832178 A CN 102832178A
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- sealing ring
- ring structure
- integrated circuit
- chip
- seal ring
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a sealing ring structure used for an integrated circuit chip. The sealing ring structure is characterized in that at least one side edge of the sealing ring is of a double-side structure, and the inner side of at least one double-side structure is provided with at least one opening. The sealing ring structure provided by the invention can prevent hydrosphere from penetrating, can reduce influence on an integrated circuit from the noises transferred by the sealing ring, can reduce noise coupling, and can prevent an electromagnetic signal from interfering the operation of a sensitive circuit and the like; and the structure is simple, the processing is convenient, and the sealing ring structure has strong practicability and can be widely popularized and applied.
Description
Technical field
The present invention relates to a kind of seal ring structure, specifically, relate to a kind of seal ring structure that is used for IC chip.
Background technology
Integrated circuit all is on silicon chip or other semiconductor material substrate, to make usually, carries out packaging and testing then.When encapsulation, must cut (saw) to integrated circuit earlier.The mechanical force of cutting possibly cause edge to form micro-fractures, especially near edge.Formed slight crack may advance towards the central circuit zone of integrated circuit and cause circuit region wherein to damage.In order to protect the circuit region of IC Center, generally can on the IC chip between circuit region with and Cutting Road between, configuration sealing ring (seal ring).Sealing ring can prevent that any slight crack (slight crack that for example, is caused because of the stress (stress) of cutting during integrated circuit) from invading the circuit region of IC interior.In addition, sealing ring also can avoid moisture to infiltrate, or avoids other chemical substance to get into and the circuit region of damage IC interior.
Traditional sealing ring is by the substrate that mixes, the circulus that metal connecting line and through hole and dielectric material are formed.Though this sealing ring can prevent slight crack and moisture that chip cutting produces and infiltrate; But it may conduct noise to other circuit in the different circuit regions or conduct the integrated circuit of external disturbance electromagnetic riveting machine signal to chip internal, and then has influence on the running of whole integrated circuit.As far as radio frequency chip, because it has low noise amplifier (LNA), the The noise of being come pressure sealing ring to propagate more easily.
In order to suppress propagation of noise, used the sealing ring of some intermittent interruption to solve this problem at present; Though it helps to reduce propagation of noise, there is certain risk in reliability.Especially under some rigorous environment conditions, the inside that aqueous vapor can get into IC chip via the interruptions of sealing ring makes the chip accelerated ageing.
Summary of the invention
To the problems referred to above that prior art exists, the purpose of this invention is to provide and a kind ofly both can prevent penetrating of aqueous vapor, can reduce the noise that comes the pressure sealing ring transmission the seal ring structure that is used for IC chip again to the integrated circuit influence.
For realizing the foregoing invention purpose, the technical scheme that the present invention adopts is following:
A kind of seal ring structure that is used for IC chip; It is characterized in that: at least one side of said sealing ring is a bilateral structure, and the inner side edge at least one bilateral structure (side adjacent with the integrated circuit on the chip) is provided with at least 1 opening.
As a kind of preferred version, the adjacent dual-side of said sealing ring is bilateral structure, and is equipped with 2 openings on the inner side edge in each bilateral structure.
As another kind of preferred version, the relative dual-side of said sealing ring is bilateral structure, and is equipped with 2 openings on the inner side edge in each bilateral structure.
As further preferred version, said sealing ring is a twin nuclei, and outer shroud wherein is a closed loop, and interior ring wherein adopts said structure.
As further preferred version, the section that is disconnected because of opening at least one inner side edge is connected with ground pads through metal wire.
Compared with prior art, the present invention is made as bilateral structure through at least one side with sealing ring, and with chip on adjacent at least one inner side edge of integrated circuit on be provided with at least 1 opening; Realized both can preventing penetrating of aqueous vapor, can reduce again and come the influence of noise that pressure sealing ring transmits, can reduce coupling noise integrated circuit; Prevent that electromagnetic riveting machine signal from disturbing sensitive circuit running etc., and simple in structure, easy to process; Have extremely strong practicality, but wide popularization and application.
Description of drawings
Fig. 1 is a kind of sketch map that is used for the seal ring structure of IC chip that embodiment 1 provides;
Fig. 2 is a kind of sketch map that is used for the seal ring structure of IC chip that embodiment 2 provides;
Fig. 3 is a kind of sketch map that is used for the seal ring structure of IC chip that embodiment 3 provides;
Fig. 4 is a kind of sketch map that is used for the seal ring structure of IC chip that embodiment 4 provides;
Fig. 5 is a kind of sketch map that is used for the seal ring structure of IC chip that embodiment 5 provides.
Among the figure: 1, sealing ring; 2, integrated circuit; 3, bilateral limit; 31, inner side edge; 32, opening; 4, metal wire; 5, outer shroud.
Embodiment
Below in conjunction with embodiment and accompanying drawing to the present invention do further in detail, intactly explanation.
Embodiment 1
As shown in Figure 1: a kind of seal ring structure that is used for IC chip that present embodiment provides; It is characterized in that: said sealing ring 1 has four sides; One of them side 3 is a bilateral structure, and said inner side edge 31 (side adjacent with integrated circuit on the chip 2) in bilateral is provided with 2 openings 32.
Said opening 32 can be used to the interference of masking noise; In addition, adopt the sealing ring 1 of outer closure can prevent the crackle that chip is not caused by stress rupture and diced chip, and can avoid the infiltration of aqueous vapor.
As shown in Figure 2; Present embodiment only is with the difference of embodiment 1: the section that is disconnected because of opening on the inner side edge 31 is connected with the ground pads (not shown) through metal wire 4; Promptly; Carry out ground connection and connect (ground connection), with masking noise electric current or signal better.
Embodiment 3
As shown in Figure 3, the difference of present embodiment and embodiment 1 only is: the adjacent dual-side of sealing ring all adopts bilateral structure, and is equipped with 2 openings 32 on the inner side edge in each bilateral structure 31.
As shown in Figure 4, the difference of present embodiment and embodiment 1 only is: the relative dual-side of sealing ring all adopts bilateral structure, and is equipped with 2 openings 32 on the inner side edge in each bilateral structure 31.
As shown in Figure 5, the difference of present embodiment and embodiment 1 only is: said sealing ring is a twin nuclei, and outer shroud 5 wherein is a closed loop, and interior ring structure wherein is said identical with embodiment 1.The outer shroud that this embodiment increases can prevent more effectively that chip cutting from cracking or aqueous vapor is infiltrated inner.
Bilateral structure quantity described in the present invention, open amount and outer shroud quantity all can correspondingly make up and increase according to required shield effectiveness.Therefore; Be necessary in this explanation to be: above embodiment only is used for technical scheme of the present invention is done explanation in further detail; Can not be interpreted as the restriction to protection range of the present invention, some nonessential improvement that those skilled in the art's foregoing according to the present invention is made and adjustment all belong to protection scope of the present invention.
Claims (5)
1. seal ring structure that is used for IC chip, it is characterized in that: at least one side of said sealing ring is a bilateral structure, and the inner side edge at least one bilateral structure is provided with at least 1 opening.
2. seal ring structure according to claim 1 is characterized in that: the adjacent dual-side of said sealing ring is bilateral structure, and is equipped with 2 openings on the inner side edge in each bilateral structure.
3. seal ring structure according to claim 1 is characterized in that: the relative dual-side of said sealing ring is bilateral structure, and is equipped with 2 openings on the inner side edge in each bilateral structure.
4. according to each described seal ring structure in the claim 1 to 3, it is characterized in that: said sealing ring is a twin nuclei, and outer shroud wherein is a closed loop, and interior ring wherein is each described seal ring structure in the claim 1 to 3.
5. according to each described seal ring structure in the claim 1 to 3, it is characterized in that: the section that is disconnected because of opening at least one inner side edge is connected with ground pads through metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103481894A CN102832178A (en) | 2012-09-18 | 2012-09-18 | Sealing ring structure used for integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103481894A CN102832178A (en) | 2012-09-18 | 2012-09-18 | Sealing ring structure used for integrated circuit chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102832178A true CN102832178A (en) | 2012-12-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103481894A Pending CN102832178A (en) | 2012-09-18 | 2012-09-18 | Sealing ring structure used for integrated circuit chip |
Country Status (1)
| Country | Link |
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| CN (1) | CN102832178A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133911A (en) * | 2017-12-21 | 2018-06-08 | 王孝裕 | A kind of seal ring structure for being used to protect IC chip |
| WO2020255573A1 (en) * | 2019-06-18 | 2020-12-24 | 株式会社Ｊｖｃケンウッド | Semiconductor wafer and manufacturing method for semiconductor chip |
| CN114642377A (en) * | 2022-02-16 | 2022-06-21 | 美智纵横科技有限责任公司 | Interaction device and self-moving cleaning equipment with same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060055007A1 (en) * | 2004-09-13 | 2006-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structure for integrated circuit chips |
| CN101447479A (en) * | 2007-11-26 | 2009-06-03 | 台湾积体电路制造股份有限公司 | Structures for preventing cross-talk between through-silicon vias and integrated circuits |
| CN101673733A (en) * | 2008-09-09 | 2010-03-17 | 联发科技股份有限公司 | Integrated circuit chip and seal ring structure of same |
| US20100084751A1 (en) * | 2008-10-03 | 2010-04-08 | Qualcomm Incorporated | Double Broken Seal Ring |
| US20100193894A1 (en) * | 2009-01-30 | 2010-08-05 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device |
-
2012
- 2012-09-18 CN CN2012103481894A patent/CN102832178A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060055007A1 (en) * | 2004-09-13 | 2006-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structure for integrated circuit chips |
| CN101447479A (en) * | 2007-11-26 | 2009-06-03 | 台湾积体电路制造股份有限公司 | Structures for preventing cross-talk between through-silicon vias and integrated circuits |
| CN101673733A (en) * | 2008-09-09 | 2010-03-17 | 联发科技股份有限公司 | Integrated circuit chip and seal ring structure of same |
| US20100084751A1 (en) * | 2008-10-03 | 2010-04-08 | Qualcomm Incorporated | Double Broken Seal Ring |
| US20100193894A1 (en) * | 2009-01-30 | 2010-08-05 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108133911A (en) * | 2017-12-21 | 2018-06-08 | 王孝裕 | A kind of seal ring structure for being used to protect IC chip |
| WO2020255573A1 (en) * | 2019-06-18 | 2020-12-24 | 株式会社Ｊｖｃケンウッド | Semiconductor wafer and manufacturing method for semiconductor chip |
| JP2020205363A (en) * | 2019-06-18 | 2020-12-24 | 株式会社Ｊｖｃケンウッド | Manufacturing method for semiconductor chip and semiconductor wafer |
| EP3989265A4 (en) * | 2019-06-18 | 2022-07-27 | JVCKenwood Corporation | Semiconductor wafer and manufacturing method for semiconductor chip |
| JP7218678B2 (en) | 2019-06-18 | 2023-02-07 | 株式会社Ｊｖｃケンウッド | Method for manufacturing semiconductor wafer and semiconductor chip |
| CN114642377A (en) * | 2022-02-16 | 2022-06-21 | 美智纵横科技有限责任公司 | Interaction device and self-moving cleaning equipment with same |
| CN114642377B (en) * | 2022-02-16 | 2024-05-10 | 美智纵横科技有限责任公司 | Interactive device and self-moving cleaning equipment with same |
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Legal Events
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121219 |