CN102818985B - BIT (Built-In Test) circuit of multipath ground/open discrete magnitude input signal - Google Patents
BIT (Built-In Test) circuit of multipath ground/open discrete magnitude input signal Download PDFInfo
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Abstract
The invention provides a BIT (Built-In Test) circuit of a multipath ground/open discrete magnitude input signal, which is mainly used for solving the problems of long test cycle, high measurement cost and poor reliability of test result in prior art. The BIT circuit of a multipath ground/open discrete magnitude input signal comprises at least two paths of serially connected second order filter circuits, a buffer circuit and a drive circuit, wherein one end of the second order filter circuit is a discrete magnitude input end while the other end thereof is a data output end, and the buffer circuit and the drive circuit are further connected with a decoding control circuit which is used for controlling data transmission and instruction decoding. The BIT circuit of a multipath ground/open discrete magnitude input signal only additionally adds two combined relays in hundreds of normal signal processing circuits, so that circuits are simple, practical and reliable, and the testability and the reliability of the circuits are improved greatly.
Description
Technical field
The present invention relates to a kind of multichannel/drive the BIT test circuit of discrete magnitude input signal, for the processing to discrete signal.
Background technology
In computing machine discrete magnitude input circuit, ground/open form discrete magnitude independent input port number Jin Bai road, discrete signal processing circuit generally comprises the compositions such as input isolation circuit, EMI (electromagnetic compatibility) circuit, level shifting circuit, buffering drive circuit, decoding control circuit, BIT (self-test) support circuit.
Ground/open form discrete magnitude independent input number of channels is larger, and normal signal treatment circuit is very complicated, applies existing method of testing when it is tested, and because mechanism for testing self is also comparatively complicated, testing cost is high, and test period is long, and reliability is poor; Therefore, be badly in need of providing a kind of test perfect, simple and practical BIT test circuit to computing machine discrete magnitude input circuit carry out simply, fast, measurement that reliability is high.
Summary of the invention
The invention provides a kind of multichannel/drive the BIT test circuit of discrete magnitude input signal, mainly solved prior art test period length, measured the problem that cost is high and test result reliability is poor.
Concrete technical solution of the present invention is as follows:
This multichannel ground/open BIT test circuit of discrete magnitude input signal, comprise the second-order filter circuit that at least two-way is connected successively, buffer circuit and driving circuit, second-order filter circuit one end is discrete magnitude input end, the other end is data output end, described buffer circuit also with for controlling data transmission is connected with the decoding control circuit of Instruction decoding with driving circuit, on wire before the second-order filter of described second-order filter circuit, be provided with the first tie point, on the first tie point, be connected with the first relay and resistance, the first relay comprises two grades, one grade for lifting power supply, one grade is analogue ground, after the second-order filter of described second-order filter circuit, on the wire before buffer circuit, be provided with the second tie point, be connected with the second relay and resistance on the second tie point, the second relay comprises two grades, and one grade for lifting power supply, and one grade is digital grounding end, between the first tie point of second-order filter circuit, buffer circuit and the driving circuit of the series connection of described each road and the first tie point, be all communicated with, between the second tie point and the second tie point, be all communicated with.
The above-mentioned second-order filter circuit of having set up the first relay, the second relay and resistance comprises EMI circuit and level shifting circuit.
Between above-mentioned discrete magnitude input end and EMI circuit, be also provided with for preventing from inputting the buffer circuit that abnormal signal disturbs.
Above-mentioned EMI circuit is comprised of LC network (L1, C1), for high frequency noise and the burr superposeing on filtering input signal cable.
Above-mentioned level shifting circuit consists of resistor network R1, R2, R3, and it is converted to a TTL compatible logic level by the signal receiving and overstress protection is provided.
Above-mentioned buffer circuit and driving circuit are isolation and strengthen bus driver and utilize Schmidt's characteristic signal to be carried out to buffer circuit and the driving circuit of debounce processing.
The invention has the advantages that:
This multichannel ground/drive the BIT test circuit of discrete magnitude input signal only additionally increases by two banked relays in the normal signal treatment circuit of over one hundred road, and circuit is simple, practical reliable, greatly improves testability and the reliability of circuit.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Embodiment
Below in conjunction with specific embodiment, the principle of the invention and structure are described in detail, as shown in Figure 1:
This multichannel ground/open BIT test circuit of discrete magnitude input signal, comprise the second-order filter circuit that at least two-way is connected successively, buffer circuit and driving circuit, second-order filter circuit one end is discrete magnitude input end, the other end is data output end, buffer circuit also with for controlling data transmission is connected with the decoding control circuit of Instruction decoding with driving circuit, on wire before the second-order filter of second-order filter circuit, be provided with the first tie point, on the first tie point, be connected with the first relay K 1 and resistance R 1, the first relay K 1 comprises two grades, one grade for lifting power supply, one grade is analogue ground AGND, after the second-order filter of second-order filter circuit, on the wire before buffer circuit, be provided with the second tie point, be connected with the second relay K 2 and resistance R 3, the second relays comprise two grades on the second tie point, one grade for lifting power supply, and one grade is digital grounding end GND, between the first tie point of second-order filter circuit, buffer circuit and the driving circuit of the series connection of each road and the first tie point, be all communicated with, between the second tie point and the second tie point, be all communicated with.
The above-mentioned second-order filter circuit of having set up the first relay K 1, the second relay K 2 and resistance R 1, R3 comprises EMI circuit and level shifting circuit; Between discrete magnitude input end and EMI circuit, be also provided with for preventing and input the buffer circuit V1 that abnormal signal disturbs, V1 is generally diode-isolated circuit, prevents from inputting abnormal signal and disturbs; EMI circuit is comprised of LC network (L1, C1), for high frequency noise and the burr superposeing on filtering input signal cable; Level shifting circuit consists of resistor network R1, R2, R3, and it is converted to a TTL compatible logic level by the signal receiving and overstress protection is provided; Buffer circuit and driving circuit are isolation and strengthen bus driver and utilize Schmidt's characteristic signal to be carried out to buffer circuit and the driving circuit of debounce processing.
Below in conjunction with concrete scheme, the present invention is described in detail:
Discrete magnitude input terminal voltage is set between-0.3V～+ 1.5V.The type input of mechanical switch types of contacts sky/ground, gets R1=2.7K Ω, R2=27K Ω, R3=10K Ω; Electronic on-off-type input, gets R1=8.2K Ω, R2=100K Ω, R3=39K Ω.When external switch (K3) is closed, by mechanical switch contact current, be 5.3mA, the electric current by electronic switch is 1.5mA, and now input sample should be a TTL low level.When switch (K3) disconnects, input sample should be a TTL high level.
Because the input impedance of buffering drive circuit device is very large, and logical zero level is-0.3V～0.8V, logical one level is that 3.5V～5V is (for the invalid state 0.8V～3.5V in centre, by R1, lift as high level), therefore can calculating parameter as follows: when K3 is closed, to calculate R1 resistance:
R1=(15-0.3) V/5.3mA ≈ 2.8K Ω, gets R1=2.7K Ω;
When K3 disconnects, V1 terminal voltage V1=R3/ (R1+R2+R3) * 15V;
Get V1=3.75V, R3=10K Ω, R2=27K Ω;
So, to the input of sky/ground, mechanical switch-type contact type, get R1=2.7K Ω, R2=27K Ω, R3=10K Ω.For electronic on-off-type, input: R1=(15-0.3)/1.5mA=9.8K Ω, gets R1=8.2K Ω; Get equally R2=100K Ω; R3=(R1+R2) * R4/ (15-4)=39K Ω (during switch cut-off, getting V1=4.0V), gets R3=39K Ω.
In this discrete magnitude multi channel signals input processing, BIT test circuit mainly completes each channel signal self-test by " two relays (K1, K2) carry out combinations of states switching ".
When carrying out outside discrete magnitude signal input sample, relay K 1 is put initial state for "+15V ", and relay K 2 is put initial state for " GND "; For " open circuit " state (logic " 0 ") of outside relay K 3, " ground connection " state (logic " 1 "), can correctly read two states by bus.
When carrying out BIT test, relay K 3 is put open-circuit condition, and relay K 1 configuration state is " AGND ", relay K 2 put respectively " GND " (logic " 0 ") or " 5V " (logic " 1 "), can correctly read two states by bus.
Generally, AGND and GND first distinguish ground connection, and last module-external a bit altogether, is eliminated ground wire and disturbed.This BIT test circuit only additionally increases by two banked relays in the normal signal treatment circuit of over one hundred road, and circuit is simple, practical reliable, greatly improves testability and the reliability of circuit.
Claims (6)
1. multichannel ground/the open BIT test circuit of discrete magnitude input signal, comprise the second-order filter circuit that at least two-way is connected successively, buffer circuit and driving circuit, second-order filter circuit one end is discrete magnitude input end, the other end is data output end, described buffer circuit also with for controlling data transmission is connected with the decoding control circuit of Instruction decoding with driving circuit, it is characterized in that: on the wire before the second-order filter of described second-order filter circuit, be provided with the first tie point, on the first tie point, be connected with the first relay and resistance, the first relay comprises two grades, one grade for lifting power supply, one grade is analogue ground, after the second-order filter of described second-order filter circuit, on the wire before buffer circuit, be provided with the second tie point, be connected with the second relay and resistance on the second tie point, the second relay comprises two grades, and one grade for lifting power supply, and one grade is digital grounding end, between the first tie point of second-order filter circuit, buffer circuit and the driving circuit of the series connection of described each road and the first tie point, be all communicated with, between the second tie point and the second tie point, be all communicated with.
2. multichannel according to claim 1 ground/drive the BIT test circuit of discrete magnitude input signal, is characterized in that: described in set up the first relay, the second relay and resistance second-order filter circuit comprise EMI circuit and level shifting circuit.
3. multichannel according to claim 2 ground/drive the BIT test circuit of discrete magnitude input signal, is characterized in that: between described discrete magnitude input end and EMI circuit, be also provided with for preventing from inputting the buffer circuit of abnormal signal interference.
4. multichannel according to claim 3 ground/drive the BIT test circuit of discrete magnitude input signal, is characterized in that: described EMI circuit is comprised of LC network (L1, C1), for high frequency noise and the burr superposeing on filtering input signal cable.
5. multichannel according to claim 4 ground/the open BIT test circuit of discrete magnitude input signal; it is characterized in that: described level shifting circuit consists of resistor network R1, R2, R3, it is converted to a TTL compatible logic level by the signal receiving and overstress protection is provided.
6. multichannel according to claim 5 ground/drive the BIT test circuit of discrete magnitude input signal, is characterized in that: described buffer circuit and driving circuit are isolation and strengthen bus driver and utilize Schmidt's characteristic signal to be carried out to buffer circuit and the driving circuit of debounce processing.
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| CN201210333066.3A CN102818985B (en) | 2012-09-10 | 2012-09-10 | BIT (Built-In Test) circuit of multipath ground/open discrete magnitude input signal |
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| CN201210333066.3A CN102818985B (en) | 2012-09-10 | 2012-09-10 | BIT (Built-In Test) circuit of multipath ground/open discrete magnitude input signal |
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| CN102818985B true CN102818985B (en) | 2014-09-24 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103853695B (en) * | 2013-12-10 | 2016-11-02 | 中国航空工业集团公司第六三一研究所 | A kind of power-on self-test circuit of discrete magnitude |
| CN105699798A (en) * | 2014-11-28 | 2016-06-22 | 上海航空电器有限公司 | BIT self-detection method of onboard complex alarm equipment |
| CN106200418B (en) * | 2016-08-17 | 2019-01-25 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of TT&C system discrete output signal conditioning circuit |
| CN106950443A (en) * | 2017-02-22 | 2017-07-14 | 庆安集团有限公司 | Electricity BIT test circuits on one kind input discrete magnitude |
| CN110542848B (en) * | 2019-09-20 | 2021-07-20 | 天津津航计算技术研究所 | Discrete magnitude acquisition power-on BIT self-detection circuit based on micro relay |
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