CN102800623A - Method of forming double-embedding structure - Google Patents
Method of forming double-embedding structure Download PDFInfo
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- CN102800623A CN102800623A CN2011101394882A CN201110139488A CN102800623A CN 102800623 A CN102800623 A CN 102800623A CN 2011101394882 A CN2011101394882 A CN 2011101394882A CN 201110139488 A CN201110139488 A CN 201110139488A CN 102800623 A CN102800623 A CN 102800623A
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- photoresist layer
- damascene structure
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Abstract
The invention provides a method of forming a double-embedding structure, which comprises the steps of: providing a substrate, wherein a component structure is formed in the substrate, and a medium layer is formed on the substrate; forming a photoresist layer on the medium layer; embossing the photoresist layer through an embossing mould to form a patterned photoresist layer, defining the position of the double-embedding structure, wherein the patterned photoresist layer comprises a first part and a second part, the second part is located above a position corresponding to an interconnecting ditch groove in the medium layer, and the height of the second part is smaller than that of the first part; etching the medium layer with the patterned photoresist layer as a mask film to form the interconnecting ditch groove and a through hole; removing the photoresist layer left in the etching procedure; and filling conductive materials in the interconnecting ditch groove and the through hole to form the electric connection of the double-embedding structure and the component structure. If the medium layer is a porous low k medium layer, the damage on the porous low k medium layer can be at least reduced. Furthermore, compared with the prior art, the technique steps can be saved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the method that forms dual-damascene structure.
Background technology
In semiconductor device, reduce RC (resistance capacitance delay) and postpone, can improve the performance of semiconductor device.Along with the development of semiconductor technology, semiconductor technology strides forward towards littler process node under the driving of Moore's Law constantly, and process node enters into 65 nanometers, 45 nanometers, even 32 lower nanometers.Along with the continuous progress of semiconductor technology, the function of device is gradually become strong, and the integrated level of device is increasingly high, and the characteristic size of device (critical dimension, CD) more and more littler.The characteristic size of device is more and more littler, and the integrated level of device is increasingly high, need further reduce RC accordingly and postpone, and so just can improve the performance of semiconductor device.
In the prior art, postpone in order to reduce RC, along with development of semiconductor, the material of dielectric layer becomes low-k materials from silica, is changed to ultralow k material from low-k materials.Postpone in order further to reduce RC, the porous low k material becomes dielectric layer material of future generation.Yet the method that forms dual-damascene structure in the prior art comprises: with reference to figure 1, be provided the semiconductor-based end 10, be formed with device architecture in this semiconductor-based end 10, on this semiconductor-based end 10, be formed with dielectric layer 11.With reference to figure 2, on dielectric layer 11, form hard mask layer 12, the material of this hard mask layer 12 is a metal.On hard mask layer 12, form the first patterned photoresist layer 13, this first patterned photoresist layer 13 defines the position of interconnection channel (Trench).With reference to figure 3; With the first patterned photoresist layer 13 is mask etching hard mask layer 12; Remove the hard mask that is not hidden by the first patterned photoresist layer 13, define the position of interconnection channel at hard mask layer 12, the first patterned photoresist layer 13 is removed in ashing afterwards.With reference to figure 4, form the photoresist layer 14 of second graphical on the hard mask layer 12 after graphically, define the position of through hole.With reference to figure 5, with the photoresist layer 14 of second graphical and graphical after hard mask layer 12 be mask, etching dielectric layer 11 forms opening 15.With reference to figure 6, the photoresist layer 14 of second graphical is removed in ashing, is mask etching opening 15 with the hard mask layer 12 after graphical, forms interconnection channel 16 and through hole 17.Remove hard mask layer 12 at last, in interconnection channel 16 and through hole 17, fill copper, form dual-damascene structure, the through hole 17 corresponding plugs that form, interconnection channel 16 corresponding formation interconnection lines.
The above forms the method for dual-damascene structure and uses cineration technics twice, and when dielectric layer 11 was the porous low k dielectric layer, cineration technics can damage the porous low k dielectric layer, thereby can influence the performance of device.
Summary of the invention
The problem that the present invention solves is that the method for the formation dual-damascene structure of prior art is prone to cause the problem to the damage of porous low k dielectric layer.
For addressing the above problem, the present invention provides a kind of method that forms dual-damascene structure, comprising:
Substrate is provided, is formed with device architecture in the said substrate, be formed with dielectric layer in the said substrate;
On said dielectric layer, form photoresist layer;
Utilize impressing mould to impress said photoresist layer; Form patterned photoresist layer; Define the position of dual-damascene structure; Said patterned photoresist layer comprises first and second portion, and said second portion is arranged in the top, position of the corresponding interconnection channel of dielectric layer, and the height of said second portion is less than the height of first;
With said patterned photoresist layer is the said dielectric layer of mask etching, forms interconnection channel and through hole;
Remove the remaining photoresist layer of etching;
Filled conductive material in said interconnection channel and through hole forms dual-damascene structure, is electrically connected with said device architecture.
Optional, utilize impressing mould to impress said photoresist layer, form patterned photoresist layer and comprise:
Utilize impressing mould to impress said photoresist layer, form patterned photoresist layer, have residual photoresist layer between said first and the second portion;
Solidify said photoresist layer through impression;
Remove said impressing mould;
Remove said residual photoresist layer.
Optional, utilize the method for UV-irradiation to solidify said photoresist layer through impression.
Optional, utilize dry etching to remove said residual photoresist layer.
Optional, the height of said through hole is that the height of said second portion multiply by the etch rate of dielectric layer and the ratio of the etch rate of photoresist layer.
Optional, the material of said dielectric layer is selected from low-k materials, ultralow k material or porous low k material.
Optional, the method for said formation photoresist layer is spin-coating method, spraying process or spread coating.
Optional, filled conductive material in said interconnection channel and through hole forms dual-damascene structure and comprises:
Utilize vapour deposition or electric plating method filled conductive material in said interconnection channel and through hole, the surface of said electric conducting material exceeds the surface of said dielectric layer;
The said electric conducting material of planarization, the surface that makes said electric conducting material is surperficial equal with said dielectric layer.
Optional, said electric conducting material is copper or tungsten.
Optional, utilize ashing to remove the remaining photoresist layer of etching.
Optional, utilize coining tool once to impress and form patterned photoresist layer or utilize the combination multi-impression of a plurality of coining tools to form patterned photoresist layer.
Compared with prior art, the present invention has the following advantages:
The method of the formation dual-damascene structure of present technique scheme; Utilize the method that impresses to impress the photoresist layer that is formed on the dielectric layer and form patterned photoresist layer, said patterned photoresist layer comprises first and second portion, and said second portion is arranged in the top, position of the corresponding interconnection channel of dielectric layer; The height of second portion is less than the height of first; Being the 3-D graphic that patterned photoresist layer has defined dual-damascene structure, afterwards, is that the mask etching dielectric layer just can form interconnection channel and through hole with this patterned photoresist layer; The present technique scheme only forms interconnection channel and through hole with accomplishing once a graphical step etching of step; Therefore flow process is simple, and processing step reduces, and can enhance productivity.
And in specific embodiment, dielectric layer is when hanging down the k porous medium layer, owing to have only a step to remove the cineration step of the remaining photoresist layer of etching, so can reduce in the cineration technics hanging down the damage of k porous medium layer.
Description of drawings
Fig. 1～Fig. 6 is the cross-sectional view of method of the formation dual-damascene structure of prior art;
Fig. 7 is the schematic flow sheet of method of the formation dual-damascene structure of the specific embodiment of the invention;
Fig. 8～Figure 12 is the cross-sectional view of method of the formation dual-damascene structure of the specific embodiment of the invention.
Embodiment
The method of the formation dual-damascene structure of present technique scheme; Utilize the method that impresses to impress the photoresist layer that is formed on the dielectric layer and form patterned photoresist layer, said patterned photoresist layer comprises first and second portion, and said second portion is arranged in the top, position of the corresponding interconnection channel of dielectric layer; The height of second portion is less than the height of first; Being the 3-D graphic that patterned photoresist layer has defined dual-damascene structure, afterwards, is that the mask etching dielectric layer just can form interconnection channel and through hole with this patterned photoresist layer; The present technique scheme only forms interconnection channel and through hole with accomplishing once a graphical step etching of step; Therefore flow process is simple, and processing step reduces, and can enhance productivity.
And in specific embodiment, dielectric layer is when hanging down the k porous medium layer, owing to have only a step to remove the cineration step of the remaining photoresist layer of etching, so can reduce in the cineration technics hanging down the damage of k porous medium layer.
In order to make those skilled in the art can better understand the present invention, specify embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 7 is the schematic flow sheet of method of the formation dual-damascene structure of the specific embodiment of the invention, ginseng Fig. 7, and the method for the formation dual-damascene structure of the specific embodiment of the invention comprises:
Step S71 provides substrate, is formed with device architecture in the said substrate, is formed with dielectric layer in the said substrate;
Step S72 forms photoresist layer on said dielectric layer;
Step S73; Utilize impressing mould to impress said photoresist layer; Form patterned photoresist layer, define the position of dual-damascene structure, said patterned photoresist layer comprises first and second portion; Said second portion is arranged in the top, position of the corresponding interconnection channel of dielectric layer, and the height of said second portion is less than the height of first;
Step S74 is the said dielectric layer of mask etching with said patterned photoresist layer, forms interconnection channel and through hole;
Step S75 removes the remaining photoresist layer of etching;
Step S76, filled conductive material in said interconnection channel and through hole forms dual-damascene structure, is electrically connected with said device architecture.
Fig. 8～Figure 12 is the cross-sectional view of method of the formation dual-damascene structure of the specific embodiment of the invention; In order to make those skilled in the art can better understand the method for the formation dual-damascene structure of the specific embodiment of the invention, below in conjunction with specific embodiment and combine to specify the method for the formation dual-damascene structure of the specific embodiment of the invention with reference to figure 7 and Fig. 8～Figure 12.
In conjunction with reference to figure 7 and Fig. 8, execution in step S71 provides substrate 20, is formed with the device architecture (not shown) in the said substrate 20, is formed with dielectric layer 22 in the said substrate 20.In this specific embodiment, be formed with etching barrier layer 21 between substrate 20 and the dielectric layer 22.The material of substrate 20 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, III-V group element compound, monocrystalline silicon carbide or silicon-on-insulator (SOI) structure.Can be formed with device architecture, for example MOS transistor at semiconductor-based the end 20.Dielectric layer 22 can be single layer structure, also can be sandwich construction.In this specific embodiment, the material of said dielectric layer 22 is selected from low-k materials, ultralow k material or porous low k material, perhaps also can be selected from their combination in any.Wherein low-k materials can be SiO
2, SiOF, SiCOH, SiO, SiCO or SiCON.Ultralow k dielectric layer material can be black diamond etc.The material of etching barrier layer 21 can be silicon nitride (SiN).The porous low k material can be p-SiCOH, and (Diethoxymethylsilane, DEMS) as presoma (precursor), (alpha-terpinene ATRP) prepares as pore former (porogen) terpinene its preparation method in order to use methyldiethoxysilane.
In conjunction with reference to figure 7 and Fig. 9, execution in step S72 forms photoresist layer 23 on said dielectric layer 22.The method of said formation photoresist layer is spin coating (spin-on coating), spraying (spray coating), drip and to be coated with (dip coating), to brush (brush coating) or evaporation, can select corresponding method according to actual conditions.Need to prove that the thickness of photoresist layer 23 need satisfy certain requirement, with guarantee after imprint process and etching technics in, photoresist layer 23 can play the effect of mask.
In conjunction with reference to figure 7 and Figure 10 d; Execution in step S73 utilizes the said photoresist layer 23 of impressing mould 30 impressions, forms patterned photoresist layer 24; Define the position of dual-damascene structure; Said patterned photoresist layer 24 comprises first 241 and second portion 242, and said second portion 242 is arranged in the top, position of the corresponding interconnection channel of dielectric layer, and the height of second portion 242 is less than the height of first 241.In the specific embodiment of the invention; Utilize the said photoresist layer 23 of impressing mould 30 impressions, form patterned photoresist layer 24 and comprise:, impressing mould 30 is provided with reference to figure 10a, Figure 10 b, Figure 10 c; Utilize the said photoresist layer 23 of impressing mould 30 impressions; Form patterned photoresist layer 24, patterned photoresist layer 24 comprises first 241 and second portion 242, has residual photoresist layer 243 between said first 241 and the second portion 242; After the imprint lithography glue-line, solidify said photoresist layer through impression; With reference to figure 10d, solidifying behind the photoresist layer of impression, remove said impressing mould 30, remove said residual photoresist layer 243 (combination) afterwards with reference to figure 10c, in this specific embodiment, utilize dry etching to remove said residual photoresist layer 243.
In this specific embodiment, the method for curing does not have particular restriction, and is known for the those skilled in the art, such as but not limited to illumination curing or hot curing, solidifies with the non-polarized light radiation modality in the preferred embodiment.Generally speaking, the restriction of the no specific electric field concussion of non-polarized light general reference direction, and light source with certain wave-length coverage, for example ultraviolet ray, infrared ray or heat ray etc. are preferably with ultraviolet light polymerization.In the specific embodiment of the invention, preferably utilize the method for UV-irradiation to solidify said photoresist layer through impression.
Need to prove in the above-described specific embodiment of the present invention, to have the 3-D graphic of dual-damascene structure on the impressing mould 30, therefore can utilize coining tool once to impress and form patterned photoresist layer 24.But the invention is not restricted to once impress; Also can utilize the combination multi-impression of a plurality of coining tools to form patterned photoresist layer; That is to say; An impressing mould does not have the 3-D graphic of dual-damascene structure, need be combined by a plurality of impressing moulds to constitute the 3-D graphic of dual-damascene structure, and these a plurality of impressing moulds of impression form patterned photoresist layer respectively.
In conjunction with reference to figure 7 and Figure 11, execution in step S74 is the said dielectric layer 22 of mask etching with said patterned photoresist layer 24, forms interconnection channel 26 and through hole 25.When etching dielectric layer 22; The second portion 242 of patterned photoresist layer 24 (combining with reference to figure 10d) also is etched removal; After being removed, continues second portion 242 dielectric layer 22 of etching second portion 242 belows; First 241 is always mask, though lossy in the process of etching, in etching process all the time as the dielectric layer 22 of mask protection below it; Therefore through the mask effect etching dielectric layer 22 of patterned photoresist layer 24, can in dielectric layer 22, form interconnection channel 26 and through hole 25.In the specific embodiment of the invention, owing between substrate 20 and dielectric layer 22, be formed with etching barrier layer 21, therefore at the said etching barrier layer 21 of etching dielectric layer 22 continued etchings, until exposing substrate 20.The height of the remaining dielectric layer 221 of interconnection channel 26 below etchings (be the height of through hole, in this specific embodiment,, alleviate the height of etching barrier layer 21 for the height of through hole) d2=d1*ER owing to have etching barrier layer 21
BD/ ER
PR, wherein, d2 represents the height of the dielectric layer 221 of interconnection channel 26 belows, the height of the second portion 242 of the photoresist layer 24 of d1 representative of graphicsization (with reference to figure 10d), ER
BDRepresentative is to the etch rate of dielectric layer 22, ER
PRRepresentative is to the etch rate of photoresist layer.Because in the specific embodiment of the invention; The height of through hole 25 is the height that d2 adds etching barrier layer 21, the height d1 of second portion 242 that therefore can be through the patterned photoresist layer 24 of control and to the etch rate of dielectric layer 22, the photoresist height than control through hole 25.
D2=d1*ER once is described below
BD/ ER
PRPrinciple: with reference to figure 10d, to the etch period T=h/ER of dielectric layer 22
BD, wherein h represents the thickness of dielectric layer, to the etch period t=d1/ER of the second portion 242 of patterned photoresist layer 24
PR, d2=h-(T-t) * ER
BD=h-(h/ER
BD-d1/ER
PR) * ER
BD=h-(h-d1*ER
BD/ ER
PR)=d1*ER
BD/ ER
PR
In conjunction with reference to figure 7 and Figure 12, execution in step S75 and step S76 remove the remaining photoresist layer of etching, filled conductive material in said interconnection channel 26 and through hole 25, and formation dual-damascene structure 27 is electrically connected with said device architecture.In this specific embodiment, utilize ashing to remove the remaining photoresist layer of etching, the first of just removing graphical photoresist layer.Ashing is removed after the remaining photoresist layer, utilizes vapour deposition or electric plating method filled conductive material in said interconnection channel and through hole, and the surface of said electric conducting material exceeds the surface of said dielectric layer; The said electric conducting material of planarization, the surface that makes said electric conducting material is surperficial equal with said dielectric layer.Wherein, the corresponding embolism 272 that forms of filled conductive material in through hole, the corresponding interconnection line 271 that forms of filled conductive material in interconnection channel, embolism 272 is electrically connected with substrate 20 interior device architectures.In this specific embodiment, said electric conducting material is copper or tungsten.
The method of the formation dual-damascene structure of the specific embodiment of the invention; Compare with the method for the formation dual-damascene structure of prior art; Only use the step (prior art is the step that photoresist is removed in twice ashing) that photoresist is removed in an ashing; When dielectric layer is the porous low k dielectric layer, can reduce damage at least to the porous low k dielectric layer.And; In the specific embodiment of the invention; Utilize the method for impression to form the patterned photoresist layer that defines the dual-damascene structure 3-D graphic; Compared with prior art can save processing step, and the method for impression can avoid utilizing the optical proximity effect in the graphical photoresist layer technology of method of photoetching etc.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. a method that forms dual-damascene structure is characterized in that, comprising:
Substrate is provided, is formed with device architecture in the said substrate, be formed with dielectric layer in the said substrate;
On said dielectric layer, form photoresist layer;
Utilize impressing mould to impress said photoresist layer; Form patterned photoresist layer; Define the position of dual-damascene structure; Said patterned photoresist layer comprises first and second portion, and said second portion is arranged in the top, position of the corresponding interconnection channel of dielectric layer, and the height of said second portion is less than the height of first;
With said patterned photoresist layer is the said dielectric layer of mask etching, forms interconnection channel and through hole;
Remove the remaining photoresist layer of etching;
Filled conductive material in said interconnection channel and through hole forms dual-damascene structure, is electrically connected with said device architecture.
2. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that, utilizes impressing mould to impress said photoresist layer, forms patterned photoresist layer and comprises:
Utilize impressing mould to impress said photoresist layer, form patterned photoresist layer, have residual photoresist layer between said first and the second portion;
Solidify said photoresist layer through impression;
Remove said impressing mould;
Remove said residual photoresist layer.
3. the method for formation dual-damascene structure as claimed in claim 2 is characterized in that, utilizes the method for UV-irradiation to solidify said photoresist layer through impression.
4. the method for formation dual-damascene structure as claimed in claim 2 is characterized in that, utilizes dry etching to remove said residual photoresist layer.
5. the method for formation dual-damascene structure as claimed in claim 2 is characterized in that, the height of said through hole is that the height of said second portion multiply by the etch rate of dielectric layer and the ratio of the etch rate of photoresist layer.
6. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that, the material of said dielectric layer is selected from low-k materials, ultralow k material or porous low k material.
7. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that, the method for said formation photoresist layer is spin-coating method, spraying process or spread coating.
8. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that, filled conductive material in said interconnection channel and through hole forms dual-damascene structure and comprises:
Utilize vapour deposition or electric plating method filled conductive material in said interconnection channel and through hole, the surface of said electric conducting material exceeds the surface of said dielectric layer;
The said electric conducting material of planarization, the surface that makes said electric conducting material is surperficial equal with said dielectric layer.
9. like the method for claim 1 or 8 described formation dual-damascene structures, it is characterized in that said electric conducting material is copper or tungsten.
10. the method for formation dual-damascene structure as claimed in claim 1 is characterized in that, utilizes ashing to remove the remaining photoresist layer of etching.
11. the method for formation dual-damascene structure according to claim 1 or claim 2 is characterized in that, utilizes coining tool once to impress and forms patterned photoresist layer or utilize the combination multi-impression of a plurality of coining tools to form patterned photoresist layer.
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| CN2011101394882A CN102800623A (en) | 2011-05-26 | 2011-05-26 | Method of forming double-embedding structure |
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| CN2011101394882A CN102800623A (en) | 2011-05-26 | 2011-05-26 | Method of forming double-embedding structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050202350A1 (en) * | 2004-03-13 | 2005-09-15 | Colburn Matthew E. | Method for fabricating dual damascene structures using photo-imprint lithography, methods for fabricating imprint lithography molds for dual damascene structures, materials for imprintable dielectrics and equipment for photo-imprint lithography used in dual damascene patterning |
| CN1698182A (en) * | 2003-06-20 | 2005-11-16 | 松下电器产业株式会社 | Method for manufacturing semiconductor device |
| CN1860605A (en) * | 2003-09-29 | 2006-11-08 | 国际商业机器公司 | Fabrication method |
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- 2011-05-26 CN CN2011101394882A patent/CN102800623A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1698182A (en) * | 2003-06-20 | 2005-11-16 | 松下电器产业株式会社 | Method for manufacturing semiconductor device |
| CN1860605A (en) * | 2003-09-29 | 2006-11-08 | 国际商业机器公司 | Fabrication method |
| US20050202350A1 (en) * | 2004-03-13 | 2005-09-15 | Colburn Matthew E. | Method for fabricating dual damascene structures using photo-imprint lithography, methods for fabricating imprint lithography molds for dual damascene structures, materials for imprintable dielectrics and equipment for photo-imprint lithography used in dual damascene patterning |
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Application publication date: 20121128 |