CN102799551B - The Apparatus for () and method therefor of synchronous selection pass transmission in advance - Google Patents
The Apparatus for () and method therefor of synchronous selection pass transmission in advance Download PDFInfo
- Publication number
- CN102799551B CN102799551B CN201210211885.0A CN201210211885A CN102799551B CN 102799551 B CN102799551 B CN 102799551B CN 201210211885 A CN201210211885 A CN 201210211885A CN 102799551 B CN102799551 B CN 102799551B
- Authority
- CN
- China
- Prior art keywords
- data
- signal
- bus
- timing signal
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 214
- 230000005540 biological transmission Effects 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title claims abstract description 29
- 230000003111 delayed effect Effects 0.000 claims description 71
- 230000009471 action Effects 0.000 claims description 31
- 230000008520 organization Effects 0.000 claims description 31
- 238000012360 testing method Methods 0.000 claims description 31
- 230000008859 change Effects 0.000 claims description 9
- 230000006870 function Effects 0.000 description 19
- 230000007246 mechanism Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000005457 optimization Methods 0.000 description 8
- 238000012546 transfer Methods 0.000 description 8
- 102100040577 Dermatan-sulfate epimerase-like protein Human genes 0.000 description 6
- 101000816741 Homo sapiens Dermatan-sulfate epimerase-like protein Proteins 0.000 description 6
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 6
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 102100025800 E3 SUMO-protein ligase ZBED1 Human genes 0.000 description 5
- 101000786317 Homo sapiens E3 SUMO-protein ligase ZBED1 Proteins 0.000 description 5
- 102100027841 Acyl-CoA wax alcohol acyltransferase 2 Human genes 0.000 description 4
- UDHXJZHVNHGCEC-UHFFFAOYSA-N Chlorophacinone Chemical compound C1=CC(Cl)=CC=C1C(C=1C=CC=CC=1)C(=O)C1C(=O)C2=CC=CC=C2C1=O UDHXJZHVNHGCEC-UHFFFAOYSA-N 0.000 description 4
- DOEADYYICZVJDD-UHFFFAOYSA-N [4-[(4-aminophenyl)diazenyl]phenyl]arsonic acid Chemical compound C1=CC(N)=CC=C1N=NC1=CC=C([As](O)(O)=O)C=C1 DOEADYYICZVJDD-UHFFFAOYSA-N 0.000 description 4
- 108010024239 aromatic amino acid aminotransferase Proteins 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 241000196324 Embryophyta Species 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 206010044565 Tremor Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003319 supportive effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
Abstract
The Apparatus for () and method therefor of a kind of synchronous selection pass in advance transmission.Should shift to an earlier date synchronous selection pass transmission equipment, in order to compensate the misalignment on synchronous data bus, this equipment comprises a resistance circuit, a core clock generator and a synchronous gate driver.This resistance circuit is in order to provide a ratio signal, and this ratio signal indicates a lead, with a synchrodata gating signal relevant with a data group in advance.This core clock generator, is coupled to this ratio signal, and this core clock generator shifts to an earlier date a data strobe timing signal with this lead.This synchronous selection pass driver in order to receive this data strobe timing signal, and produces this synchrodata gating signal according to this data strobe timing signal, and with this lead this synchrodata gating signal in advance.
Description
Technical field
The present invention relates to a kind of microelectronic, particularly relate to the Apparatus and method for of a kind of data relevant with reception to the transmission of source synchronous signal and clock synchronous.
Background technology
Modern computer system adopts a kind of source synchronous system bus to provide the exchanges data between bus agent device, the exchanges data of such as boundary between microprocessor and hub memory.Source synchronous bus protocol makes data transmit by a bus speed at a high speed.The principle of operation of source synchronous agreement is that data are output in bus by a transfer bus proxy server and continues a set time, and sends or change one and correspond to the data-strobe signal (strobesignal) of these data to indicate these data of reception bus agent device to be effective.Data signals and data-strobe signal are all transmitted along identical travel path by bus, and therefore when the conversion corresponding data-strobe signal being detected, receiver relatively can confirm that data are effective.
But data-strobe signal and data signals are easily because some reasons make a mistake.One of source of mistake is the inaccurate of clock generation circuit, and clock generation circuit is generally phase-locked loop (phaselockedloop), is effective in order to be blocked in data signals in bus and conversion gated data to indicate these data.These inaccurate may from the limit of design, the tolerance of manufacture or the factor of environment.In ideal conditions, gated data is that the midway between data validity interval is accurately changed, and makes receiver receive the setup times of data and the retention time is equal.Inaccurate crooked (skewing) that may cause data signals and/or data-strobe signal in relevant clock generation circuit, makes condition of acceptance be not optimal.
The source of another mistake caused by the distribution of the data-strobe signal in a receiving trap.Although system designer guarantees that gating signal and relevant data signals thereof transmit along the upper identical transmission path of a system board (i.e. motherboard) with exhausting one's ability, but well known be, once data-strobe signal enters receiving trap, all inner synchronous receiver relevant with data-strobe signal must be dispensed to.In some device, need extra transmission length to transmit data-strobe signal to different receivers, so may be delayed the delivery time of data signals, and then the phase place producing synchronous driving is crooked.
Therefore, the device and method of the signal unjustified (misalignment) compensated on synchronous data bus is necessary.
By adjustment one data strobe and corresponding data signals thereof, the signal on synchronous bus is made to be that the technology optimally transmitted also is necessary.
In addition, adjustment one data strobe and the mechanism of relevant data signals under motherboard grade thereof is provided also to be necessary.
Moreover, in order to reach optimization accepting state, a kind of under motherboard grade by synchronous bus signal aim at programmable device be also necessary.
Summary of the invention
The present invention is directed to prior art problem, shortcoming and restriction to propose to solve.In addition, the invention provides one preferably technology with the transmission of the source synchronous signal in the different device of optimization and reception, such as microprocessor and supportive device thereof.In one embodiment, provide a kind of device in order to compensate the non-alignment on synchronous data bus, this device comprises a resistor network, a core clock generator and a synchronous gate driver.This resistor network in order to provide a ratio signal to indicate a lead, with in advance relevant with a data group synchrodata gating signal.This core clock generator is coupled to this ratio signal, shifts to an earlier date a data strobe timing signal with this lead.This synchronous selection pass driver receives this data strobe timing signal, and produces this synchrodata gating signal according to this data strobe timing signal, and with this lead this synchrodata gating signal in advance.
Also the one that provides of the present invention shifts to an earlier date synchronous selection pass transmitting device, in order to compensate the non-alignment on synchronous data bus, should comprise a resistor network and a microprocessor by synchronous selection pass transmitting device in advance.This resistor network is in order to provide a ratio signal, and this ratio signal indicates a lead, with a synchrodata gating signal relevant with a data group in advance.This microprocessor comprises a core clock generator and a synchronous gate driver.This core clock generator is coupled to this ratio signal, shifts to an earlier date a data strobe timing signal with this lead.This synchronous selection pass driver receives this data strobe timing signal, and produces this synchrodata gating signal according to this data strobe timing signal, and wherein this synchrodata gating signal with this lead in advance.
The present invention also provides a kind of method of the non-alignment compensated on synchronous data bus, comprises and provides a ratio signal by a resistor network, and this ratio signal indicates a lead, with a synchrodata gating signal relevant with a data group in advance; Couple a core clock generator to this ratio signal, make this core clock generator shift to an earlier date a data strobe timing signal with this lead; And provide data strobe timing signal to synchronous gate driver, produce this synchrodata gating signal according to this data strobe timing signal, and with this lead this synchrodata gating signal in advance.
About the applicability in industry, in the microprocessor that the computer installation that invention can be implemented in general service or specific use uses.
Accompanying drawing explanation
Fig. 1 shows the calcspar of an embodiment of source synchronous data system now.
Fig. 2 shows the sequential chart of the source synchronous signal situation of the source synchronous data system of Fig. 1.
Fig. 3 shows the calcspar of an embodiment of synchronous selection pass transmission equipment in advance of the present invention.
Fig. 4 shows the calcspar of an embodiment of radial synchronous selection pass distributing equipment of the present invention.
Fig. 5 shows the calcspar of an embodiment of Lag synchronization data receiver of the present invention.
Fig. 6 shows the calcspar of an embodiment of delay locked loop of the present invention.
Fig. 7 shows the calcspar of an embodiment of optimization sync signal programmable device of the present invention.
Reference numeral explanation
100 source synchronous data systems
102 bus clock generators
110 device A
111 core clock generators
112 synchronous selection pass drivers
113 synchrodata drivers
120 device B
122 synchronous receivers
200 sequential charts
201 describe bus timing signal
202 data timing signals
203 data strobe timing signals
210 first situations
211 signals
212 data-strobe signal
220 second situations
221 signals
222 data-strobe signal
300 shift to an earlier date synchronous selection pass transmission equipment
310 shift to an earlier date gated transmission device
311 core clock generators
331 phase-locked loops element forward
332 frequency dividers
333 delay locked loops
312 synchronous selection pass drivers
400 radial synchronous selection pass distributing equipments
420 device C
434 composite delay elements
434.1 ~ 434.N delay element
422 synchronous receivers
500 Lag synchronization data receivers
520 delayed data receiving traps
522 synchronous receivers
533 delay locked loops
600 delay locked loops
601 delayed encoders
602 multiplexers
603 analog-to-digital converters
700 optimization sync signal programmable devices
701 shift to an earlier date signal device
711 core clock generators
712 synchronous selection pass drivers
722 synchronous receivers
731 testing action united organization interfaces
732 synchronous bus optimizers
733 delay locked loops
BCLK bus timing signal
DCLK data timing signal
DSCLK data strobe timing signal
DSTROBE, DSTROBE1 ~ DSTROBEN data-strobe signal
DATA1 ~ DATAN data bit signal
Between I dynamic stage
The V valid period
T1, T2, T3, T4 time
R1, R2 resistance
RAT ratio signal
VDD reference voltage
REF reference signal
DREF postpones reference signal
DDATA delayed data position signal
IN, OUT signal
DSEL [63:0] the delayed selection culture bus
U1A, U1B, U2A, U2B ~ U63A, U63B reverser
D0 ~ D63 postpones tap
JTAG [N:0] standard testing action united organization bus
DSTROBEX, DSTROBEY data-strobe signal
ARAT, DRAT bus
Embodiment
For further illustrating each embodiment, the invention provides drawings attached.Accompanying drawing is a part for disclosure of the present invention, and it is mainly in order to illustrate embodiment, and can explain the operation principles of embodiment in conjunction with the associated description of instructions.With reference to these contents, those skilled in the art will be understood that other possible embodiments and advantage of the present invention.Therefore, the invention is not restricted to the embodiment of following display and description, so should authorize the widest scope meeting following principle of operation and novel feature.
Because above-mentioned prior art discussion is about being used for transmitting and receive the source synchronous signal transmission and relevant technology that the device of data uses now, the shortcoming of prior art and restriction are by composition graphs 1, Fig. 2 discussion.Then, the present invention discusses with reference to Fig. 3 to Fig. 7.The present invention is by postpone and the mechanism of data-strobe signal in advance in a pair device and data bit signal overcomes shortcoming and the restriction of prior art, thus correct the non-alignment (misalignment) of the gating signal that caused by any reason and data signals, with optimization this to the flux between device.
First please refer to Fig. 1, its display is according to now in transmission and the system block diagrams of receipt source synchrodata.Source synchronous data system 100 comprises a signal transmission 110 (hereinafter referred to as device A) and a receiving trap 120 (hereinafter referred to as device B), device A110 is coupled to receiving trap 120 by a source synchronous bus 130, and source synchronous bus 130 comprises a data-strobe signal DSTROBE and relative multiple data bit signal DATA1 ~ DATAN.Source synchronous data system 100 also comprises a bus clock generator 102, and it is coupled to device A100 by bus timing signal BCLK.Device A110, device B120 and bus clock generator 102 are all arranged in a motherboard (not shown) usually, and data bit signal DATA1 ~ DATAN, data-strobe signal DSTROBE and bus timing signal BCLK are then in fact as the path interconnecting mechanism between device A110 and device B120.Data-strobe signal DSTROBE is from a 13S input media B120, and data bit signal DATA1 ~ DATAN is respectively from point 131 ~ 13N input media B120.According to the typical synchronization implementation aspect of one, the physical length (physicallength) of the access record of one group of data bit signal DATA1 ~ DATAN and relative data-strobe signal DSTROBE is equal, make any transmission line effect experienced by data-strobe signal DSTROBE, such as transmission delay, also experienced by data bit signal DATA1 ~ DATAN.The target of source synchronous data system 100 is the state (state) of the valid period midway accurately translation data gating signal DSTROBE of the data bit signal DATA1 ~ DATAN in bus 130, the best reception state that the transmission data therefore in generator B120 are suitable.
Device A110 has the synchronous gate driver 112 of a core clock generator 111, one and multiple synchrodata driver 113, and core clock generator 111 is coupled to synchronous selection pass driver 112 and multiple synchrodata driver 113.Core clock generator 111 produces a boundary in the data strobe timing signal DSCLK of other a timing signal (not shown) and data timing signal DCLK.The data-strobe signal DSTROBE that synchronous selection pass driver 112 produces and data strobe timing signal DSCLK same-phase, data bit signal DATA1 ~ DATAN that synchrodata driver 113 produces and data timing signal DCLK same-phase.Data strobe timing signal DSCLK and data timing signal DCLK obtains according to bus timing signal BCLK, therefore can and source synchronous data system 100 in other device (not shown) between data transmission and receive comprehensive synchronization.According to a typical embodiment, data timing signal DCLK and data strobe timing signal DSCLK is the frequency multiplication of bus timing signal BCLK, and the aligning (alignment) making the data strobe DSTROBE of data bit signal DATA1 ~ DATAN within the valid period in bus 130 is accurately.In other examples, two kinds of gating types can adopt single derivative timing signal, and at an edge trigger data transmission of derivative timing signal, and at another edge-triggered one gating of derivative timing signal.
Device B120 comprises the synchronous receiver 122 of multiple correspondence, and one in each reception data bit signal DATA1 ~ DATAN of multiple synchronous receiver 122, all synchronous receivers 122 receive data-strobe signal DSTROBE.When data-strobe signal DSTROBE timing (data-strobe signal DSTROBE changes state), synchronous receiver 122 checks one in its other data bit signal DATA1 ~ DATAN respectively.
What those skilled in the art can understand is, source synchronous data system 100 in Fig. 1 represents the enforcement aspect simplified of device A110 and device B120, and it may find in the calculation element of type or laptop computer, flat computer or any specific use and instrument on the table.More specifically, device A110 and device B120 can be realized by CPU (central processing unit) (centralprocessingunit, CPU) or microprocessor, chipset (supportingchipset) or memory interface, hub memory or controller, direct memory access (DMA) unit (directmemoryaccessunit), graphics controller and similar device thereof.Commonly, these devices 110,120 can be bus agent device, and are coupled mutually by point-to-point source synchronous bus 130, exemplified by the bus 130 of Fig. 1.
From broadly, in order to transmit data, bus agent device one of them (as device A110) is by the data bit signal DATA1 ~ DATAN in driving bus 130 and the subset (subset) in data-strobe signal DSTROBE, and another bus agent device (as device B120) detect and receive drive signal time, acquisition data can be carried out by the state of the data bit signal DATA1 ~ DATAN in bus 130 and the one or more subsets in data strobe DSTROBE.Bus protocol now for the data transmission between two bus agent devices has many kinds, and the detailed description of these different technology has exceeded the scope of the application's book.Can fully understand at this, during bus transfer, " data " be transmitted between two or more bus agent device 110,120 can comprise address information, the data relevant with address information, control information or status information, are so not limited thereto.No matter the kind of the data of transmission in bus 130 why, it should be noted that, the bus protocol that the data system 100 of source synchronous now of the application's book adopts is a kind of common " source synchronous " agreement, realizes with very high bus speed to transmit data.Bus protocol against existing technologies, the principle of source synchronous communications protocol operation is, data bit signal DATA1 ~ DATAN in one data group is exported to bus 130 and continues a regular time by transfer bus proxy server 110, and the data-strobe signal DSTROBE sent corresponding to data bit signal DATA1 ~ DATAN, to indicate these data of reception bus agent device 120 to be effective.As above mentioned, the target of source synchronous data system 100 is the validity being represented data bit signal DATA1 ~ DATAN by data-strobe signal DSTROBE at a time point (being generally the midway of data bit signal DATA1 ~ DATAN valid period), and this is optimum for receiving trap 120 receives data bit signal DATA1 ~ DATAN.
What those skilled in the art may appreciate that is, under very high transmission speed, one group of data bit signal DATA1 ~ DATAN and the corresponding entity of data-strobe signal DSTROBE and the transmission path of electric parameter, and in two devices 110,120 one, boundary and other transmission paths organizing signal (not shown) in the bus 130 between other possible device (not shown) may be suitable different, this is one of advantage of point-to-point source synchronous communications protocol.That is, two devices 110,120 only couple mutually by specific data bit signal DATA1 ~ DATAN and relevant data-strobe signal DSTROBE, so can prevent many problems that shared-bus system is intrinsic, specifically the impact of the transmission delay of transmission path, bus impedance and electrical specification receives the stable or effective time of data bit signal DATA1 ~ DATAN that bus agent device 120 receives.For this reason, source synchronous bus protocol is commercially quite general.In typical enforcement aspect, the data-strobe signal DSTROBE relevant with one group of data bit signal DATA1 ~ DATAN transmits doing along the transmission path identical with this group data bit signal DATA1 ~ DATAN, and data-strobe signal DSTROBE like this will demonstrate the transport property identical with data bit signal DATA1 ~ DATAN itself.If the data comprised at data bit signal DATA1 ~ DATAN are that in effective period, data-strobe signal DSTROBE is set up, and when receiving bus agent device 120 and detecting that data-strobe signal DSTROBE is effective, then data bit signal DATA1 ~ DATAN is also effective beyond doubt.
Even if there is above-mentioned advantage, the present invention notices the integrality still having other factors adversely to affect source synchronous interface, i.e. the mode transmitted in device B120 after a 13S access to plant B120 of data-strobe signal DSTROBE.As shown in the figure, when data bit signal DATA1 ~ DATAN and data-strobe signal DSTROBE transfers to device B120 along intimate identical transmission path from device A110, once data-strobe signal DSTROBE is from a 13S access to plant B120, N number of different synchronous receiver 122 must be transferred in device B120.Although and a synchronous receiver 122 is arranged on the place of chip layout that closely corresponding data bit signal DATA1 ~ DATAN inputs to device B120 ideally, data-strobe signal DSTROBE is not the same concerning data-strobe signal DSTROBE, this is because must distribute to all synchronous receivers 122 corresponding to data bit signal DATA1 ~ DATAN.Although therefore the present invention observes one of them that may arrange synchronous receiver 122, make its data bit signal DATA1 ~ DATAN and data-strobe signal DSTROBE transfer to the transmission path of the input of synchronous receiver 122 from device A110 identical nearly, the associated transport path of remaining data bit signal DATA1 ~ DATAN will be different from the transmission path (viewed by synchronous receiver 122 input end of correspondence) of data-strobe signal DSTROBE.This is because the physical path of data-strobe signal DSTROBE is longer than or is shorter than the physical path of remaining data bit signal DATA1 ~ DATAN, and also comprise the buffering of the data-strobe signal DSTROBE for distributing.Therefore, the conversion of data-strobe signal DSTROBE probably during the data validity of remaining data bit signal DATA1 ~ DATAN in early than or be later than device A110 institute arranger.In fact, the present invention considers that a kind of extreme example is, the transmission of the data-strobe signal DSTROBE in device B120 can not control via the deviser of device A110, configuration like this transfers to one or more transmission paths of corresponding synchronous receiver 122, making when data-strobe signal DSTROBE changes state is effective to indicate data bit signal DATA1 ~ DATAN, when data-strobe signal DSTROBE changes state, may occur correspond to one or more transmission path data bit signal DATA1 ~ DATAN in one or more be not effective.
In addition, because the data strobe timing signal DSCLK relevant to the data bit signal DATA1 ~ DATAN passing through synchronous bus 130 and data timing signal DCLK normally produced by the mimic channel (i.e. phase-locked loop) in core clock generator 111, the present inventor emphasizes that the signal caused by the design and manufacture of core clock generator 111 itself trembles, work period and inaccuracy, the reception of the synchronous receiver 122 that data-strobe signal DSTROBE will be made to show in the Usefulness Pair device B120 of data bit signal DATA1 ~ DATAN is undesirable, therefore the non-alignment of the data-strobe signal DSTROBE in device B120 and data bit signal DATA1 ~ DATAN is made more to worsen.Can with reference to the explanation do discussion more specifically of figure 2 by the observed problem to the imperfect switching of the data-strobe signal DSTROBE relative to data bit signal DATA1 ~ DATAN of synchronous receiver 122.
Fig. 2 is sequential Figure 200 that description two may appear at the source synchronous signal situation 210,220 of the source synchronous data system 100 li of Fig. 1.In the first situation 210, the data-strobe signal 212 in receiving trap is synchronous to relevant signal 211, and in the second situation 220, data-strobe signal 222 is asynchronous to relevant signal 221.The difference of transmission path is caused, so that produce the relative phase of the signal 211,221 of data-strobe signal 212,222 and correspondence due to the inaccuracy in the inaccuracy of above-mentioned transmission, buffering, assignment latency or clock generator or transmitting device or receiving trap or error.
Sequential Figure 200 describes bus timing signal BCLK201, and signal derives data timing signal DCLK202 and data strobe timing signal DSCLK203 thus.Shown in composition graphs 1, data timing signal DCLK202 and data strobe timing signal DSCLK203 is dispensed to the synchrodata driver relevant with data bit signal DATA1 ~ DATAN and data strobe driver in transmitting device.Driver utilizes timing signal 202,203 to carry out accurately arranging data position signal DATA1 ~ DATAN on a synchronous bus, also to show the validity of data bit signal DATA1 ~ DATAN, make receiving trap correctly can receive data bit signal DATA1 ~ DATAN.Should be noted, the frequency of data timing signal DCLK202 and data strobe timing signal DSCLK203 is the twice of the frequency of bus timing signal BCLK201, this is used to show particularly be clearly intended to, the problem that the prior art that those skilled in the art may appreciate that with teaching is relevant, namely the timing signal 202,203 in present-day devices is according to its object and crooked accurately, and relative frequency range is from 2 times to 64 times of bus timing signal BCLK201 frequency, and frequency is as shown in sequential Figure 200, for comparatively clearly showing the limit of technology today.
Sequential Figure 200 also demonstrates, the first situation 210 times, it is synchronous for inputting 212 about a data input 211 of data bit signal DATA1 and a data strobe in first receiver, and the second situation 220 times, be asynchronous about a data input 221 of data bit signal DATAN and data strobe input 222 in the n-th receiver.As for the data-strobe signal DSTROBE relevant with other all data bit signal DATA2 ~ DATA (N-1) in data bit signal DATA1 ~ DATAN, may show compared to the more or less aligning of the input such as shown in sequential Figure 200.
Therefore, at time T1, the transmission of data bit signal DATA1 ~ DATAN is the midway of the valid period (V) on synchronous bus substantially, as shown in the figure, is the drop edge place dropping on data timing signal DCLK202.It is noted that the setting (assertion) of data bit signal DATA1 ~ DATAN in bus can occur in other edges or the phase place place of data timing signal DCLK202.At this time point, data strobe timing signal DSCLK203 also switches, therefore setting data gating signal DSTROBE.Receiving the time of data-strobe signal DSTROBE according to the input 212 of the first situation 210, first receiver, be in fact the midway of the valid period at data bit signal DATA1, and DATA1 received by the input 211 of the first receiver.For the reception of data bit signal DATA1, this is an optimal cases, and demonstrates the effect of transmission line, and the transmission time specifically inputting 211 and 212 display data bit signal DATA1 and data-strobe signal DSTROBE is almost equal.Input 211,212 shows same best reception condition at time T2.
But the second situation 220 is really not so because input 222 time T3 and T4 be detect data-strobe signal DSTROBE state change the time, but now data bit signal DATAN be regarded as in input 221 invalid.That is, due to aforementioned mentioned reason, data-strobe signal DSTROBE lags behind the phase place of data bit signal DATAN in input 221 in the phase place of input 222.Cause the possible reason of this phenomenon to be that data-strobe signal DSTROBE has to pass through a long path, this path inputs to receiving trap by one, to arrive the receiver of data bit signal DATAN.Another possible reason is inaccurate in transmitting device.Can also be that other reasons causes.
Therefore, the present inventor observes, once a device complete design and manufacture, namely reasonable manner does not correct these problems, comprise, via motherboard transmission, transmission delay is increased to one or more data bit signal DATA1 ~ DATAN or data-strobe signal DSTROBE, to compensate the problem of transmission or receiving trap.
In addition, the present invention notices provides the mechanism of the phase differential between the data bit signal DATA1 ~ DATAN in a kind of adjustable or amendment source synchronous bus and data-strobe signal DSTROBE to have active demand, and this mechanism does not need to revise the layout on motherboard and wiring, do not need to revise one or more reception and conveyer yet.
Relative phase difference between the one group of data bit signal that the invention provides a kind of data-strobe signal of receiving each receiver in receiving trap and correspondence makes the device and method of finely tuning, to overcome the problem of aforesaid prior art.Next, with reference to Fig. 3 to Fig. 7, the present invention is described.
Please refer to Fig. 3, is the calcspar of an embodiment of synchronous selection pass transmission equipment 300 in advance according to the present invention.In advance synchronous selection pass transmission equipment 300 comprises one and shifts to an earlier date gated transmission device 310, gated transmission device 310 is coupled to a bus timing signal BCLK in advance, and produce a data-strobe signal DSTROBE, the device A110 of similar Fig. 1 substantially, passes through a ratio signal RAT except gated transmission device in advance 310 of the present invention and shifts to an earlier date the transmission of data-strobe signal DSTROBE relative to its relevant data bit signal (figure does not illustrate).Ratio signal RAT is coupled to resistance R1 and R2.Resistance R1 is coupled to a reference voltage VDD, and reference voltage VDD is also coupled to gated transmission device 310 in advance.Resistance R2 is also coupled to a common ground reference voltage.
Gated transmission device 310 comprises core clock generator 311 and a synchronous gate driver 312 in advance.Synchronous selection pass driver 312 output data strobe signal DSTROBE.Core clock generator 311 comprises phase-locked loop element 331, frequency divider 332 and a delay locked loop 333 forward.Phase-locked loop forward element 331 can produce a data strobe timing signal DSCLK as is known to the person skilled in the art.Core clock generator 311 also comprises a frequency divider 332, and it receives a reference signal REF, and reference signal REF is a feedback signal of data strobe timing signal DSCLK.Core clock generator 311 also comprises a delay locked loop 333, and it is coupled to frequency divider 332, and delay locked loop 333 receives ratio signal RAT.Delay locked loop 333 provides a delay reference signal DREF to be fed back to phase-locked loop element 331 forward.
During operation, core clock generator 311 produces data strobe timing signal DSCLK, and the frequency of data strobe timing signal DSCLK is the multiple of the frequency of bus timing signal BCLK, its medium multiple determined by any means known of the phase-locked loop configuration of element 331 and frequency divider 332 forward.In addition, core clock generator 311 by ratio signal RAT with the phase place relative to bus timing signal BCLK in advance data strobe timing signal DSCLK.According to an embodiment, ratio signal RAT is the over half of its cycle in order to specific data gating timing signal DSCLK's in advance.According to another embodiment, the ratio of resistance R2 ratio resistance R1 determines a magnitude of voltage of ratio signal RAT, and this magnitude of voltage detected by delay locked loop 333, and its size is the number percent of reference voltage VDD.The delay proportional with the magnitude of voltage of ratio signal RAT is introduced the output of frequency divider 332 by delay locked loop 333, with the reference signal DREF that is delayed, so make phase-locked loop forward element 331 with same retardation in advance data strobe timing signal DSCLK.According to an embodiment, if the ratio of resistance R2 ratio resistance R1 is minimum, namely resistance R2 equals 0 ohm, then delay locked loop 333 can not be delayed, and the core clock generator 111 of the similar in fact Fig. 1 of the effect of core clock generator 311.If the ratio of resistance R2 ratio resistance R1 is very big, namely resistance R1 equals 0 ohm, the retardation that then delay locked loop 333 produces is similar to the half in the cycle of data strobe timing signal DSCLK, so causes the lead of data strobe timing signal DSCLK to be similar to same retardation.If the ratio of resistance R2 ratio resistance R1 equals 1, namely resistance R1 equals resistance R2, the delay that then delay locked loop 333 produces is similar to 1/4th of the cycle of data strobe timing signal DSCLK, so causes the lead of data strobe timing signal DSCLK to be similar to identical retardation.Other mechanism are also considered, and delay locked loop 333 produces larger delay, so cause the half being greater than its cycle in advance of data strobe timing signal DSCLK.Other embodiments then consider the scheme of nonlinear lead.
According to another embodiment, before delay locked loop 333 is configured at frequency divider 332 by core clock generator 311, be a feedback circuit concerning data strobe timing signal DSCLK.That is, the present embodiment derives the retardation of delayed data gating timing signal DSCLK by ratio signal RAT, then being divided by delayed data gating timing signal DSCLK occurs frequently postpones reference signal DREF, but not equal data strobe timing signal DSCLK by intimate for a feedback signal delay, the retardation postponing this feedback signal is then derived by ratio signal RAT.
In advance gated transmission device 310 of the present invention in order to the function that performs and computing described above.Gated transmission device 310 comprises logic, circuit, device or microcode (microcode) in advance, wherein microcode and micro-order (microinstruction) or presumptive instruction (nativeinstruction), or by the combination of logic, circuit, device or microcode, or in order to perform the equivalence element of the function identical with the present invention and computing.The element being used for realizing these computings and function in advance in gated transmission device 310 may share with other circuit or microcodes etc., and other circuit or microcode shift to an earlier date the element being used for performing other functions and/or computing in gated transmission device 310.Scope according to instructions of the present invention, microcode is a term (term) be used for reference to multiple micro-order, and a micro-order (also can be referenced as a presumptive instruction) is instruction performed under a unit (unit) standard.For example, multiple micro-order is directly performed by the microprocessor of a Reduced Instruction Set Computer (reduceinstructionsetcomputer, RISC).Complex instruction set computer (CISC) (complexinstructionsetcomputer, CISC) microprocessor, the processor that such as x86 is compatible, x86 instruction is translated to relevant micro-order, and relevant micro-order is directly performed by the multiple unit in a unit or the microprocessor of a complex instruction set computer (CISC).
By this, gated transmission device 310 in advance of the present invention can shift to an earlier date the transmission of data-strobe signal DSTROBE relative to the transmission of its relevant data bit signal, to compensate the phase place misalignment of the signal that receiving trap receives.
Then, please refer to Fig. 4, is the calcspar of an embodiment of synchronous (radialsynchronous) gating distributing equipment 400 of radial direction of the present invention.Radial synchronous selection pass distributing equipment 400 can the synchronous selection pass transmission equipment 300 in advance of composition graphs 3 use.Radial synchronous selection pass distributing equipment 400 comprises a receiving trap 420 (hereinafter referred to as device C), the device A120 of device C420 and Fig. 1 is similar, both principle difference is, device C420 of the present invention comprises a composite delay element 434, and composite delay element 434 makes to be used in device C420 all delay paths equalizations of reception from the data-strobe signal DSTROBE of transmitting device (not shown).Device C420 also comprises multiple synchronous receiver 422, in order to receive one or more data bit signal DATA1 ~ DATAN along with data-strobe signal DSTROBE.The first data bit signal DATA1 in multiple data bit signal DATA1 ~ DATAN is from the 1: 431 input media C420, and display is from the first transmission delay of the 1: 431 synchronous receiver 422 associated to it.Last data bit signal DATAN in multiple data bit signal DATA1 ~ DATAN from last point 433 input media C420, and shows the last transmission delay of the synchronous receiver 422 associated to it from last point 433.One or more data bit signal DATA1 ~ DATAN shows the most long transmission delays relative to a remaining data bit signal in multiple data bit signal DATA1 ~ DATAN.
Data-strobe signal DSTROBE from point 432 input media C420, and is sent to composite delay element 434.Composite delay element 434 comprises multiple delay element 434.1 ~ 434.N, and each of delay element 434.1 ~ 434.N is associated with corresponding synchronous receiver 422.One time delay is introduced data-strobe signal DSTROBE is sent to corresponding synchronous receiver 422 transfer path from composite delay element 434 by each of delay element 434.1 ~ 434.N.According to an embodiment, the transmission path of each that the retardation of each of multiple delay element 434.1 ~ 434.N makes data-strobe signal DSTROBE be sent to multiple synchronous receiver 422 from point 432 equals described most long transmission delays.According to an embodiment, each of delay element 434.1 ~ 434.N comprises one or more pairs of reverser (inverter).Under the manufacturing process of 32 how rice, often pair of reverser produces the gate delay (gatedelay) of 20 psecs (picoseconds) nearly, so will cause the delay that 20 psecs occur on the associated transport path of data-strobe signal DSTROBE.
By this, the data-strobe signal DSTROBE that the radial synchronous selection pass distributing equipment 400 in Fig. 4 makes the receiver 422 in device C420 receive all has almost equal phase delay relative to each data bit signal DATA1 ~ DATAN.Therefore, the advantage of gated transmission device 310 is in advance, by the resistance value selecting resistance R1 and resistance R2, the phase place of each of multiple data-strobe signal DSTROBE1 ~ DSTROBEN that multiple synchronous receiver 422 is received, is advanced to the midway of the valid period of each of corresponding data bit signal DATA1 ~ DATAN just.For example, if under 32 how rice technology, most long delay is 10 psecs, the transmission path making data-strobe signal DSTROBE transfer to corresponding synchronous receiver 422 is produced extra delay by each of then delay element 434.1 ~ 434.N, and then make a little 432 to equal 10 psecs to all transmission delays receiving input, and the resistance value of resistance R1 and resistance R2 is selected to make the transmission of data-strobe signal DSTROBE shift to an earlier date 10 psecs relative to the transmission of data bit signal DATA1 ~ DATAN.
Device C420 of the present invention is in order to perform above-mentioned function and computing.Device C420 comprises logic, circuit, device or microcode, wherein microcode and micro-order or presumptive instruction, or the combination of logic, circuit, device or microcode, or in order to perform the equivalence element of the function identical with the present invention and computing.The element being used for realizing these computings and function in device C420 of the present invention may share with other circuit or microcodes etc., and other circuit or microcode are the elements being used for performing other functions and/or computing in device C420 of the present invention.
Then, please refer to Fig. 5, is the calcspar of an embodiment of Lag synchronization data receiver 500 of the present invention.Lag synchronization data receiver 500 comprises a delayed data receiving trap 520, it is similar to the receiving trap 120 of Fig. 1, with receiving trap 120 unlike, in order to the valid period of the one or more data bit signals by synchronous receiver 522 aims at corresponding data-strobe signal DSTROBE, delayed data receiving trap 520 can make the transmission path of one or more data bit signals of a data group be delayed.In the present embodiment, relative to data bit signal DATA, the phase place of data-strobe signal DSTROBE is shifted to an earlier date, but relative to data-strobe signal DSTROBE the phase place of delayed data position signal DATA.
By this, delayed data receiving trap 520 is coupled to ratio signal RAT and reference voltage VDD.First resistance R1 is coupled between ratio signal RAT and reference voltage VDD, and the second resistance R2 is coupled to ratio signal RAT and ground connection reference voltage.Delayed data receiving trap 520 comprises delay locked loop 533 and a synchronous receiver 522, delay locked loop 533 is in order to receive data bit signal DATA, and generation a delayed data position signal DDATA, delayed data position signal DDATA comprise a delay more proportional than the ratio of R1 with R2.Delayed data position signal DDATA inputs synchronous receiver 522 along with data-strobe signal DSTROBE.
During practical operation, delay locked loop 533 carrys out the phase place of delayed data position signal DATA relative to data-strobe signal DSTROBE by the numerical value pointed by ratio signal RAT.According to an embodiment, ratio signal RAT makes the delay of data bit signal DATA be not more than the half in the cycle of data-strobe signal DSTROBE.According to an embodiment, the magnitude of voltage of the ratio signal RAT that delay locked loop 533 detects is decided by the ratio of resistance R2 ratio resistance R1, wherein detected magnitude of voltage and reference voltage VDD proportional, and delay locked loop 533 makes the delayed data position signal DDATA of output produce a delay proportional with ratio signal RAT, synchronous receiver 522 like this more appropriately can receive data bit signal DATA.According to an embodiment, if the ratio of resistance R2 ratio resistance R1 is minimum, namely resistance R2 equals 0 ohm, then delay locked loop 533 can not be delayed, and the accepting state of synchronous receiver 522 equals in fact the synchronous receiver 122 of Fig. 1.If the ratio of resistance R2 ratio resistance R1 is very big, namely resistance R1 equals 0 ohm, the delay that then delay locked loop 533 produces is similar to the half in the cycle of data-strobe signal DSTROBE, so causes the retardation of data bit signal DATA to be similar to same retardation.If the ratio of resistance R2 ratio resistance R1 equals 1, namely resistance R1 equals resistance R2, the delay that then delay locked loop 533 produces is similar to 1/4th of the cycle of data-strobe signal DSTROBE, so causes the retardation of data bit signal DATA to be similar to same retardation.Other mechanism are also considered, and delay locked loop 533 produces larger delay, so cause the delay of data bit signal DATA to be greater than the half in its cycle.Other embodiments then consider the nonlinear retardation produced by delay locked loop 533.
In order to clearly express, Fig. 5 only shows a synchronous receiver 522, but the present invention also considers that multiple delay locked loop 533 and multiple corresponding synchronous receiver 522 are to transmit the data bit signal DATA of a data group, wherein ratio signal RAT is dispensed to each of delay locked loop 533, and identical retardation is introduced in each transmission path of data bit signal DATA.
The delayed data receiving trap 520 of Fig. 5 in order to the one or more data bit signal DATA in delayed data group, especially when delayed data receiving trap 520 comprises the radial data gating distribution mechanism being similar to Fig. 4.The device C420 of Fig. 4 increases the delay of the transmission path of the multiple data-strobe signal DSTROBE1 ~ DSTROBENs relevant with data group, make all transmission paths all have a phase delay (phaselag) relative to the slowest transmission path, so the one or more of data bit signal DATA1 ~ DATAN must be aimed at (realign) again with data-strobe signal DSTROBE1 ~ DSTROBEN.By this, the device C420 delayed data reception mechanism of Fig. 5 being incorporated to Fig. 4 will make the alignment result of these signals better.
Delayed data receiving trap 520 of the present invention in order to perform function and computing described above.Delayed data receiving trap 520 comprises logic, circuit, device or microcode, wherein microcode and micro-order or presumptive instruction, or the combination of logic, circuit, device or microcode, or in order to perform the equivalence element of the function identical with the present invention and computing.The element being used for realizing these computings and function in delayed data receiving trap 520 may share with other circuit or microcodes etc., and other circuit or microcode are the elements being used for performing other functions and/or computing in delayed data receiving trap 520.
Then, please refer to Fig. 6, it shows the calcspar of an embodiment of delay locked loop 600 of the present invention.Delay locked loop 600 can be applicable to Fig. 3 and 5 figure.Delay locked loop 600 comprises an analog-to-digital converter (analog-to-digitalconverter) 603, analog-to-digital converter 603 is in order to receive ratio signal RAT, and wherein the value of ratio signal RAT indicates the delay of the transmission path of a signal IN.When delay locked loop 600 applies to the gated transmission device 310 in advance of Fig. 3, signal IN is the output of frequency divider 332, and signal OUT is for postponing reference signal DREF.When delay locked loop 600 applies to the delayed data receiving trap 520 of Fig. 5, signal IN is data bit signal DATA, and signal OUT is delayed data position signal DDATA.Ratio signal RAT is converted to a digital signal by analog-to-digital converter 603, and digital signal is transferred to delayed encoder 601.Delayed encoder 601 is in the upper state producing signal of a delayed selection culture bus DSEL [63:0], and in order to clearly illustrate, Fig. 6 only shows 64, but the present invention is not limited thereto, and the running of the position of other different numbers is also identical.The delayed selection culture bus DSEL [63:0] is coupled to a multiplexer 602, and the selection as multiplexer 602 inputs.Signal IN by multiple reverser to (inverterpair) U1A, U1B ..., U63A, U63B, each has identical gate delay.Postpone the input of tap D0 ~ D63 as multiplexer 602, and the signal OUT that multiplexer 602 exports is according to the value of the delayed selection culture bus DSEL [63:0], position wherein in the delayed selection culture bus DSEL [63:0] only has one to be set up separately (asserted), the delay tap D0 ~ D63 sent in order to indicate multiplexer 602 1.For example, if all positions are not set up, multiplexer 602 is selected to postpone tap D0, then all signal IN all do not postpone.If arrange position 63, then multiplexer 602 is selected to postpone tap D63, then signal IN produces maximum retardation.Should be noted, the size of delay locked loop 600 of the present invention (namely reverser to U1A, U1B ..., U63A, U63B number, postpone the number of tap D0 ~ D63 and the number of the delayed selection culture bus DSEL [63:0]) be not limited to this, also can consider other different numbers.In addition, increase between postponing the right comparatively long delay that number can increase and design requirement matches of the reverser between tap D0 ~ D63.
Delay locked loop 600 comprises logic, circuit, device or microcode, wherein microcode and micro-order or presumptive instruction, or the combination of logic, circuit, device or microcode, or in order to perform the equivalence element of the function identical with the present invention and computing.The element being used for realizing these computings and function in delay locked loop 600 may share with other circuit or microcodes etc., and other circuit or microcode are the elements being used for performing other functions and/or computing in delay locked loop 600.
Then, please refer to Fig. 7, it shows the calcspar of an embodiment of optimization sync signal programmable device 700 of the present invention.Optimization sync signal programmable device 700 comprises one and shifts to an earlier date signal device 701, in order to optimization sync signal.Signal device 701 comprises a core clock generator 711 in advance, and core clock generator 711 in order to receive bus timing signal BCLK, and produces the synchronous gate driver 712 of a data strobe timing signal DSCLK to.Synchronous selection pass driver 712 produces one in multiple data-strobe signal DSTRPBEX, and multiple data-strobe signal DSTRPBEX is relevant with the data bit signal (not shown) corresponding to particular address group, as described above.
Signal device 701 also comprises a delay locked loop 733 in advance, and delay locked loop 733 receives a data bit signal DATA, and produces a delayed data position signal DDATA, and is sent to synchronous receiver 722.Synchronous receiver 722 also receives an other data-strobe signal DSTROBEY, and data-strobe signal DSTROBEY is relevant with data bit signal DATA.
In addition, signal device 701 also comprises a testing action united organization interface (JointTestActionGroup in advance, JTAG) 731, jtag interface 731 receives the control information in standard testing action united organization interface JTAG [N:0], and transmits information to the one synchronous bus optimizer 732 that is applied to data-strobe signal DSTRPBEX and delayed data position signal DATA in advance.Synchronous bus optimizer 732 produces a gating Advanced information able to programme, and passing ratio bus ARAT is sent to core clock generator 711.And synchronous bus optimizer 732 produces a programmable data position deferred message, and passing ratio bus DRAT is sent to delay locked loop 733.
During practical operation, adopt the JTAG programming technique known for one or more data strobe is (in order to clearly illustrate, only show a data-strobe signal DSTRPBEX in advance) design an accurate lead, and for one or more data bit signal DATA(is in order to clearly illustrate, only show a data bit signal DATA) design an accurate retardation.Programming operation when signal device 701 programmes at JTAG the state be allowed in advance, such as, under resetting (RESET) state, can be performed.When programming has been performed, the function of bus ARAT, DRAT has been similar in fact the bus RAT of Fig. 3 and Fig. 5, to provide control information to device 310,520.In addition, signal device 701 also can adopt the radial distribution element 434 of the device C420 as Fig. 4 in advance.
According to an embodiment, bus ARAT is dispensed to multiple core clock generator 711, that each core clock generator 711 produces a correspondence and the data strobe timing signal DSCLK of only.Different leads is that the jtag interface 731 by corresponding to data group arranges.Similarly, bus DRAT is dispensed to multiple delay locked loop 733, that each delay locked loop 733 produces a correspondence and the delayed data position signal DDATA of only.Different retardations is that the jtag interface 731 by corresponding to data group arranges.
Therefore, the programmable signal device 701 in advance of Fig. 7 can make system designer compensate the problem of synchronous bus misalignment, and does not need to revise motherboard.
In advance signal device 701 comprises logic, circuit, device or microcode, wherein microcode and micro-order or presumptive instruction, or the combination of logic, circuit, device or microcode, or in order to perform the equivalence element of the function identical with the present invention and computing.The element being used for realizing these computings and function in advance in signal device 701 may share with other circuit or microcodes etc., and other circuit or microcode shift to an earlier date the element being used for performing other functions and/or computing in signal device 701.
More than describe according to the multiple different embodiment of the present invention, wherein various features can single or different combination enforcement.Therefore, embodiment of the present invention be disclosed as the specific embodiment of illustrating principle of the present invention, should be regardless of limit the present invention in disclosed embodiment.Furthermore, above describe and accompanying drawing is only the use of the present invention's demonstration, be not limited.The change of other elements or combination all possibilities, and be not contrary in spirit of the present invention and scope.
The list of references of related application
The application of subject application right of priority is according to following United States Patent (USP) provisional application case, and case number, this case entirety all includes herein by reference in.
Claims (63)
1. shift to an earlier date a synchronous selection pass transmission equipment, in order to compensate the misalignment on synchronous data bus, should comprise by synchronous selection pass transmission equipment in advance:
One testing action united organization interface, in order to receive the control information in a standard testing action united organization bus, this control information indicates a lead, with a synchrodata gating signal relevant with a data group in advance;
One synchronous bus optimizer, in order to receive this control information, and produce gating Advanced information to ratio bus able to programme, this gating Advanced information able to programme indicates this lead;
One core clock generator, is coupled to this ratio bus, in order to by a data strobe timing signal this lead in advance; And
One synchronous gate driver, in order to receive this data strobe timing signal, and produces this synchrodata gating signal according to this data strobe timing signal, and this synchrodata gating signal with this lead in advance.
2. synchronous selection pass transmission equipment in advance as claimed in claim 1, also comprises multiple extra core clock generator, is coupled to this ratio bus, in order to by the data strobe timing signal of multiple correspondence with multiple lead in advance.
3. synchronous selection pass transmission equipment in advance as claimed in claim 2, also comprise multiple extra synchronous selection pass driver, in order to receive these data strobe timing signals, and producing multiple synchrodata gating signal according to these data-strobe signal, these synchrodata gating signals are with these leads in advance.
4. synchronous selection pass transmission equipment in advance as claimed in claim 1, wherein this synchrodata gating signal with this lead in advance, and the scope of this lead is never advanced to the semiperiod of this data strobe timing signal.
5. synchronous selection pass transmission equipment in advance as claimed in claim 1, wherein this core clock generator and this synchronous selection pass driver are arranged in a device, this device is coupled to a motherboard, and this testing action united organization interface enters this device by multiple extra pin.
6. synchronous selection pass transmission equipment in advance as claimed in claim 1, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One frequency divider, in order to receive this data strobe timing signal, and produce one with the output signal of bus timing signal same frequency, make the frequency of these phase-locked loops this data strobe timing signal of element alignment and this bus timing signal forward; And
One delay locked loop, receive this output signal and this ratio bus, this delay locked loop is in order to delay this lead by this output signal.
7. synchronous selection pass transmission equipment in advance as claimed in claim 1, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One delay locked loop, receives this data strobe timing signal and this ratio bus, and produces an output signal, and this output signal comprises this data strobe timing signal delayed with this lead; And
One frequency divider, in order to receive this output signal, and produce a delay reference signal, the frequency of this delay reference signal is equal with the frequency of this bus timing signal, make the frequency of these phase-locked loops this this output signal of element alignment and this bus timing signal forward, make this data strobe timing signal this lead in advance.
8. shift to an earlier date a synchronous selection pass transmission equipment, in order to compensate the misalignment on synchronous data bus, should comprise a microprocessor by synchronous selection pass transmission equipment in advance, this microprocessor comprises:
One testing action united organization interface, in order to receive the control information in a standard testing action united organization bus, this control information indicates a lead, with a synchrodata gating signal relevant with a data group in advance;
One synchronous bus optimizer, in order to receive this control information, and produce gating Advanced information to ratio bus able to programme, this gating Advanced information able to programme indicates this lead;
One core clock generator, is coupled to this ratio bus, in order to by a data strobe timing signal this lead in advance; And
One synchronous gate driver, in order to receive this data strobe timing signal, and produces this synchrodata gating signal according to this data strobe timing signal, and this synchrodata gating signal with this lead in advance.
9. synchronous selection pass transmission equipment in advance as claimed in claim 8, this microprocessor also comprises multiple extra core clock generator, is coupled to this ratio bus, in order to by the data strobe timing signal of multiple correspondence with multiple lead in advance.
10. synchronous selection pass transmission equipment in advance as claimed in claim 9, this microprocessor also comprises multiple extra synchronous selection pass driver, in order to receive these data strobe timing signals, and producing multiple synchrodata gating signal according to these data-strobe signal, these synchrodata gating signals are with these leads in advance.
11. shift to an earlier date synchronous selection pass transmission equipment as claimed in claim 8, and wherein this synchrodata gating signal with this lead in advance, and the scope of this lead is never advanced to the semiperiod of this data strobe timing signal.
12. shift to an earlier date synchronous selection pass transmission equipment as claimed in claim 8, and wherein this microprocessor is coupled to a motherboard, and this testing action united organization interface enters this microprocessor by multiple extra pin.
13. shift to an earlier date synchronous selection pass transmission equipment as claimed in claim 8, and wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One frequency divider, in order to receive this data strobe timing signal, and produce one with the output signal of bus timing signal same frequency, make the frequency of these phase-locked loops this data strobe timing signal of element alignment and this bus timing signal forward; And
One delay locked loop, receive this output signal and this ratio bus, this delay locked loop is in order to delay this lead by this output signal.
14. shift to an earlier date synchronous selection pass transmission equipment as claimed in claim 8, and wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One delay locked loop, receives this data strobe timing signal and this ratio bus, and produces an output signal, and this output signal comprises this data strobe timing signal delayed with this lead; And
One frequency divider, in order to receive this output signal, and produce a delay reference signal, the frequency of this delay reference signal is equal with the frequency of this bus timing signal, make the frequency of these phase-locked loops this this output signal of element alignment and this bus timing signal forward, make this data strobe timing signal this lead in advance.
15. 1 kinds of methods compensating the misalignment on synchronous data bus, comprising:
By the control information in testing action united organization interface one standard testing action united organization bus, this control information indicates a lead, with a synchrodata gating signal relevant with a data group in advance;
Produce gating Advanced information to ratio bus able to programme according to this control information, this gating Advanced information able to programme indicates this lead;
Couple a core clock generator to this ratio bus, this core clock generator is by a data strobe timing signal this lead in advance; And
This data strobe timing signal is sent to a synchronous gate driver, this synchronous selection pass driver produces this synchrodata gating signal according to this data strobe timing signal, and this synchrodata gating signal with this lead in advance.
The method of 16. misalignment compensated on synchronous data bus as claimed in claim 15, also comprises and couples multiple extra core clock generator to this ratio bus, with by the data strobe timing signal of multiple correspondence with multiple lead in advance.
The method of 17. misalignment compensated on synchronous data bus as claimed in claim 16, also comprise and multiple extra synchronous selection pass driver is provided, to receive these data strobe timing signals, and producing multiple synchrodata gating signal according to these data-strobe signal, these synchrodata gating signals are with these leads in advance.
The method of 18. misalignment compensated on synchronous data bus as claimed in claim 16, wherein this synchrodata gating signal with this lead in advance, and the scope of this lead is never advanced to the semiperiod of this data strobe timing signal.
The method of 19. misalignment compensated on synchronous data bus as claimed in claim 15, wherein this core clock generator and this synchronous selection pass driver are arranged in a device, this device is coupled to a motherboard, and this testing action united organization interface enters this device by multiple extra pin.
The method of 20. misalignment compensated on synchronous data bus as claimed in claim 15, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One frequency divider, in order to receive this data strobe timing signal, and produce one with the output signal of bus timing signal same frequency, make the frequency of these phase-locked loops this data strobe timing signal of element alignment and this bus timing signal forward; And
One delay locked loop, receive this output signal and this ratio bus, this delay locked loop is in order to delay this lead by this output signal.
The method of 21. misalignment compensated on synchronous data bus as claimed in claim 15, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One delay locked loop, receives this data strobe timing signal and this ratio bus, and produces an output signal, and this output signal comprises this data strobe timing signal delayed with this lead; And
One frequency divider, in order to receive this output signal, and produce a delay reference signal, the frequency of this delay reference signal is equal with the frequency of this bus timing signal, make the frequency of these phase-locked loops this this output signal of element alignment and this bus timing signal forward, make this data strobe timing signal this lead in advance.
22. 1 kinds of Lag synchronization data transmission sets, in order to compensate the misalignment on synchronous data bus, this Lag synchronization data transmission set comprises:
One testing action united organization interface, in order to receive the control information in a standard testing action united organization bus, this control information indicates a retardation, to postpone a data bit signal relevant with a data group;
One synchronous bus optimizer, in order to receive this control information, and produce programmable data position deferred message to ratio bus, this programmable data position deferred message indicates this retardation; And
One delay locked loop, is coupled to this ratio bus, in order to this retardation is added to this data bit signal, to produce a delayed data position signal.
Whether 23. Lag synchronization data transmission sets as claimed in claim 22, also comprise a synchronous receiver, be coupled to this delayed data position signal and a synchronous selection pass signal, change in order to the state detecting this delayed data position signal.
24. Lag synchronization data transmission sets as claimed in claim 23, wherein this synchronous selection pass signal and this data bit signal are from a gate bus of a transmitting device.
25. Lag synchronization data transmission sets as claimed in claim 22, also comprise multiple extra delay locked loop, be coupled to this ratio bus, these extra delay locked loops are in order to produce multiple delayed data positions signal, these delayed data position signals postpone with multiple retardation, and these retardations are specified in this ratio bus.
26. Lag synchronization data transmission sets as claimed in claim 25, also comprise multiple extra synchronous receiver, be coupled to these delayed data position signals and multiple data-strobe signal, whether these extra synchronous receivers change in order to the state detecting these delayed data position signals.
27. Lag synchronization data transmission sets as claimed in claim 22, wherein this data bit signal postpones with this retardation, and the scope of this retardation is never deferred to the semiperiod of a data-strobe signal.
28. Lag synchronization data transmission sets as claimed in claim 22, wherein this Lag synchronization data transmission set is arranged in a device, and this device is coupled to a motherboard, and this testing action united organization interface enters this device by multiple extra pin.
29. 1 kinds of Lag synchronization data transmission sets, in order to compensate the misalignment on synchronous data bus, this Lag synchronization data transmission set comprises a microprocessor, and this microprocessor comprises:
One testing action united organization interface, in order to receive the control information in a standard testing action united organization bus, this control information indicates a retardation, to postpone a data bit signal relevant with a data group;
One synchronous bus optimizer, in order to receive this control information, and produce programmable data position deferred message to ratio bus, this programmable data position deferred message indicates this retardation; And
One delay locked loop, is coupled to this ratio bus, in order to this retardation is added to this data bit signal, to produce a delayed data position signal.
30. Lag synchronization data transmission sets as claimed in claim 29, whether wherein this microprocessor also comprises a synchronous receiver, be coupled to this delayed data position signal and a synchronous selection pass signal, change in order to the state detecting this delayed data position signal.
31. Lag synchronization data transmission sets as claimed in claim 30, wherein this synchronous selection pass signal and this data bit signal are from a gate bus of a transmitting device.
32. Lag synchronization data transmission sets as claimed in claim 29, wherein this microprocessor also comprises multiple extra delay locked loop, be coupled to this ratio bus, these extra delay locked loops are in order to produce multiple delayed data positions signal, these delayed data position signals postpone with multiple retardation, and these retardations are specified in this ratio bus.
33. Lag synchronization data transmission sets as claimed in claim 32, wherein this microprocessor also comprises multiple extra synchronous receiver, be coupled to these delayed data position signals and multiple data-strobe signal, whether these extra synchronous receivers change in order to the state detecting these delayed data position signals.
34. Lag synchronization data transmission sets as claimed in claim 29, wherein this data bit signal postpones with this retardation, and the scope of this retardation is never deferred to the semiperiod of a data-strobe signal.
35. Lag synchronization data transmission sets as claimed in claim 29, wherein this microprocessor is coupled to a motherboard, and this testing action united organization interface enters this microprocessor by multiple extra pin.
36. 1 kinds of methods compensating the misalignment on synchronous data bus, comprising:
By the control information in a testing action united organization interface one standard testing action united organization bus, this control information indicates a retardation, to postpone a data bit signal relevant with a data group;
Produce programmable data position deferred message to ratio bus according to this control information, this programmable data position deferred message indicates this retardation; And
Couple a delay locked loop to this ratio bus, in order to this retardation is added to this data bit signal, to produce a delayed data position signal.
Whether the method for 37. misalignment compensated on synchronous data bus as claimed in claim 36, also comprise and couple a synchronous receiver to this delayed data position signal and a synchronous selection pass signal, change in order to the state detecting this delayed data position signal.
38. methods compensating as claimed in claim 37 the misalignment on synchronous data bus, wherein this synchronous selection pass signal and this data bit signal are from a gate bus of a transmitting device.
The method of 39. misalignment compensated on synchronous data bus as claimed in claim 36, also comprise and couple multiple extra delay locked loop to this ratio bus, these extra delay locked loops are in order to produce multiple delayed data positions signal, these delayed data position signals postpone with multiple retardation, and these retardations are specified in this ratio bus.
The method of 40. misalignment compensated on synchronous data bus as claimed in claim 39, also comprise and couple multiple extra synchronous receiver to these delayed data position signals and multiple data-strobe signal, whether these extra synchronous receivers change in order to the state detecting these delayed data position signals.
The method of 41. misalignment compensated on synchronous data bus as claimed in claim 36, wherein this data bit signal postpones with this retardation, and the scope of this retardation is never deferred to the semiperiod of a data-strobe signal.
The method of 42. misalignment compensated on synchronous data bus as claimed in claim 36, also comprises, by multiple extra pin, this testing action united organization interface is accessed a motherboard.
43. 1 kinds of synchronous data transmission equipment, in order to compensate the misalignment on synchronous data bus, this synchronous data transmission equipment comprises:
One testing action united organization interface, in order to receive the control information in a standard testing action united organization bus, this control information indicates a lead and a retardation, with a synchrodata gating signal relevant with one first data group in advance, and postpone a data bit signal relevant with one second data group;
One synchronous bus optimizer, in order to receive this control information, gating Advanced information to an one first ratio bus able to programme is produced according to this control information, this gating Advanced information able to programme indicates this lead, and producing programmable data position deferred message to an one second ratio bus, this programmable data position deferred message indicates this retardation;
One core clock generator, is coupled to this first ratio bus, in order to by a data strobe timing signal this lead in advance;
One synchronous gate driver, in order to receive this data strobe timing signal, and produces this synchrodata gating signal according to this data strobe timing signal, and this synchrodata gating signal with this lead in advance; And
One delay locked loop, is coupled to this second ratio bus, in order to this retardation is added to this data bit signal, to produce a delayed data position signal.
44. synchronous data transmission equipment as claimed in claim 43, also comprise multiple extra core clock generator, are coupled to this first ratio bus, in order to by the data strobe timing signal of multiple correspondence with multiple lead in advance.
45. synchronous data transmission equipment as claimed in claim 44, also comprise multiple extra synchronous selection pass driver, in order to receive these data strobe timing signals, and producing multiple synchrodata gating signal according to these data-strobe signal, these synchrodata gating signals are with these leads in advance.
46. synchronous data transmission equipment as claimed in claim 43, wherein this synchrodata gating signal with this lead in advance, and the scope of this lead is never advanced to the semiperiod of this data strobe timing signal.
47. synchronous data transmission equipment as claimed in claim 43, wherein this core clock generator and this synchronous selection pass driver are arranged in a device, this device is coupled to a motherboard, and this testing action united organization interface enters this device by multiple extra pin.
48. synchronous data transmission equipment as claimed in claim 43, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One frequency divider, in order to receive this data strobe timing signal, and produce one with the output signal of bus timing signal same frequency, make the frequency of these phase-locked loops this data strobe timing signal of element alignment and this bus timing signal forward; And
One delay locked loop, receive this output signal and this first ratio bus, this delay locked loop is in order to postpone this lead by this output signal.
49. synchronous data transmission equipment as claimed in claim 43, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One delay locked loop, receives this data strobe timing signal and this ratio bus, and produces an output signal, and this output signal comprises this data strobe timing signal delayed with this lead; And
One frequency divider, in order to receive this output signal, and produce a delay reference signal, the frequency of this delay reference signal is equal with the frequency of this bus timing signal, make the frequency of these phase-locked loops this this output signal of element alignment and this bus timing signal forward, make this data strobe timing signal this lead in advance.
50. 1 kinds of synchronous data transmission equipment, in order to compensate the misalignment on synchronous data bus, this synchronous data transmission equipment comprises a microprocessor, and this microprocessor comprises:
One testing action united organization interface, in order to receive the control information in a standard testing action united organization bus, this control information indicates a lead and a retardation, with a synchrodata gating signal relevant with one first data group in advance, and postpone a data bit signal relevant with one second data group;
One synchronous bus optimizer, in order to receive this control information, gating Advanced information to an one first ratio bus able to programme is produced according to this control information, this gating Advanced information able to programme indicates this lead, and producing programmable data position deferred message to an one second ratio bus, this programmable data position deferred message indicates this retardation;
One core clock generator, is coupled to this first ratio bus, in order to by a data strobe timing signal this lead in advance;
One synchronous gate driver, in order to receive this data strobe timing signal, and produces this synchrodata gating signal according to this data strobe timing signal, and this synchrodata gating signal with this lead in advance; And
One delay locked loop, is coupled to this second ratio bus, in order to this retardation is added to this data bit signal, to produce a delayed data position signal.
51. synchronous data transmission equipment as claimed in claim 50, wherein this microprocessor also comprises multiple extra core clock generator, is coupled to this first ratio bus, in order to by the data strobe timing signal of multiple correspondence with multiple lead in advance.
52. synchronous data transmission equipment as claimed in claim 51, wherein this microprocessor also comprises multiple extra synchronous selection pass driver, in order to receive these data strobe timing signals, and producing multiple synchrodata gating signal according to these data-strobe signal, these synchrodata gating signals are with these leads in advance.
53. synchronous data transmission equipment as claimed in claim 50, wherein this synchrodata gating signal with this lead in advance, and the scope of this lead is never advanced to the semiperiod of this data strobe timing signal.
54. synchronous data transmission equipment as claimed in claim 50, wherein this microprocessor is coupled to a motherboard, and this testing action united organization interface enters this microprocessor by multiple extra pin.
55. synchronous data transmission equipment as claimed in claim 50, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One frequency divider, in order to receive this data strobe timing signal, and produce one with the output signal of bus timing signal same frequency, make the frequency of these phase-locked loops this data strobe timing signal of element alignment and this bus timing signal forward; And
One delay locked loop, receive this output signal and this first ratio bus, this delay locked loop is in order to postpone this lead by this output signal.
56. synchronous data transmission equipment as claimed in claim 50, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One delay locked loop, receives this data strobe timing signal and this ratio bus, and produces an output signal, and this output signal comprises this data strobe timing signal delayed with this lead; And
One frequency divider, in order to receive this output signal, and produce a delay reference signal, the frequency of this delay reference signal is equal with the frequency of this bus timing signal, make the frequency of these phase-locked loops this this output signal of element alignment and this bus timing signal forward, make this data strobe timing signal this lead in advance.
57. 1 kinds of methods compensating the misalignment on synchronous data bus, comprising:
By the control information in a testing action united organization interface one standard testing action united organization bus, this control information indicates a lead and a retardation, with a synchrodata gating signal relevant with one first data group in advance, and postpone a data bit signal relevant with one second data group;
A programmable data position deferred message is produced extremely to one first ratio bus according to this control information, this gating Advanced information able to programme indicates this lead, and producing programmable data position deferred message to an one second ratio bus, this programmable data position deferred message indicates this retardation;
Couple a core clock generator to this first ratio bus, in order to by a data strobe timing signal this lead in advance;
The synchronous gate driver of this data strobe timing signal to, and produce this synchrodata gating signal according to this data strobe timing signal, this synchrodata gating signal is with this lead in advance; And
Couple a delay locked loop to this second ratio bus, in order to this retardation is added to this data bit signal, to produce a delayed data position signal.
The method of 58. misalignment compensated on synchronous data bus as claimed in claim 57, also comprises and couples multiple extra core clock generator to this first ratio bus, in order to by the data strobe timing signal of multiple correspondence with multiple lead in advance.
The method of 59. misalignment compensated on synchronous data bus as claimed in claim 58, also comprise and multiple extra synchronous selection pass driver is provided, in order to receive these data strobe timing signals, and producing multiple synchrodata gating signal according to these data-strobe signal, these synchrodata gating signals are with these leads in advance.
The method of 60. misalignment compensated on synchronous data bus as claimed in claim 57, wherein this synchrodata gating signal with this lead in advance, and the scope of this lead is never advanced to the semiperiod of this data strobe timing signal.
The method of 61. misalignment compensated on synchronous data bus as claimed in claim 60, wherein this core clock generator and this synchronous selection pass driver are arranged in a device, this device is coupled to a motherboard, and this testing action united organization interface enters this device by multiple extra pin.
The method of 62. misalignment compensated on synchronous data bus as claimed in claim 57, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One frequency divider, in order to receive this data strobe timing signal, and produce one with the output signal of bus timing signal same frequency, make the frequency of these phase-locked loops this data strobe timing signal of element alignment and this bus timing signal forward; And
One delay locked loop, receive this output signal and this first ratio bus, this delay locked loop is in order to delay this lead by this output signal.
The method of 63. misalignment compensated on synchronous data bus as claimed in claim 57, wherein this core clock generator comprises a phase-locked loop, and this phase-locked loop comprises:
Multiple phase-locked loop element forward, in order to receive a bus timing signal, and produce this data strobe timing signal, this data strobe timing signal is the frequency multiplication of this bus timing signal;
One delay locked loop, receives this data strobe timing signal and this ratio bus, and produces an output signal, and this output signal comprises this data strobe timing signal delayed with this lead; And
One frequency divider, in order to receive this output signal, and produce a delay reference signal, the frequency of this delay reference signal is equal with the frequency of this bus timing signal, make the frequency of these phase-locked loops this this output signal of element alignment and this bus timing signal forward, make this data strobe timing signal this lead in advance.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610184153.5A CN105808485B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610183496.XA CN105868152B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data bit transmission device and its method |
| CN201610182788.1A CN105808483B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610184151.6A CN105808484B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610183487.0A CN105893310B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182760.8A CN105868150B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data receiver and its method |
| CN201610182769.9A CN105868151B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
Applications Claiming Priority (14)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/165,679 US8839018B2 (en) | 2011-06-21 | 2011-06-21 | Programmable mechanism for optimizing a synchronous data bus |
| US13/165,665 | 2011-06-21 | ||
| US13/165,650 | 2011-06-21 | ||
| US13/165,671 | 2011-06-21 | ||
| US13/165,665 US8751851B2 (en) | 2011-06-21 | 2011-06-21 | Programmable mechanism for synchronous strobe advance |
| US13/165,664 US8751850B2 (en) | 2011-06-21 | 2011-06-21 | Optimized synchronous data reception mechanism |
| US13/165,654 US8683253B2 (en) | 2011-06-21 | 2011-06-21 | Optimized synchronous strobe transmission mechanism |
| US13/165,654 | 2011-06-21 | ||
| US13/165,659 | 2011-06-21 | ||
| US13/165,679 | 2011-06-21 | ||
| US13/165,671 US8751852B2 (en) | 2011-06-21 | 2011-06-21 | Programmable mechanism for delayed synchronous data reception |
| US13/165,664 | 2011-06-21 | ||
| US13/165,659 US8782460B2 (en) | 2011-06-21 | 2011-06-21 | Apparatus and method for delayed synchronous data reception |
| US13/165,650 US8782459B2 (en) | 2011-06-21 | 2011-06-21 | Apparatus and method for advanced synchronous strobe transmission |
Related Child Applications (7)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610183496.XA Division CN105868152B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data bit transmission device and its method |
| CN201610184151.6A Division CN105808484B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610184153.5A Division CN105808485B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182760.8A Division CN105868150B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data receiver and its method |
| CN201610183487.0A Division CN105893310B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182788.1A Division CN105808483B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182769.9A Division CN105868151B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102799551A CN102799551A (en) | 2012-11-28 |
| CN102799551B true CN102799551B (en) | 2016-04-20 |
Family
ID=47198664
Family Applications (8)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610183487.0A Active CN105893310B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182760.8A Active CN105868150B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data receiver and its method |
| CN201610184151.6A Active CN105808484B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182788.1A Active CN105808483B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610183496.XA Active CN105868152B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data bit transmission device and its method |
| CN201610184153.5A Active CN105808485B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182769.9A Active CN105868151B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201210211885.0A Active CN102799551B (en) | 2011-06-21 | 2012-06-21 | The Apparatus for () and method therefor of synchronous selection pass transmission in advance |
Family Applications Before (7)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610183487.0A Active CN105893310B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182760.8A Active CN105868150B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data receiver and its method |
| CN201610184151.6A Active CN105808484B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182788.1A Active CN105808483B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610183496.XA Active CN105868152B (en) | 2011-06-21 | 2012-06-21 | Lag synchronization data bit transmission device and its method |
| CN201610184153.5A Active CN105808485B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
| CN201610182769.9A Active CN105868151B (en) | 2011-06-21 | 2012-06-21 | The device and method thereof of synchronous selection pass transmission in advance |
Country Status (2)
| Country | Link |
|---|---|
| CN (8) | CN105893310B (en) |
| TW (1) | TWI482030B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10158364B1 (en) * | 2017-08-31 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Realignment strength controller for solving loop conflict of realignment phase lock loop |
| KR102455370B1 (en) * | 2018-04-17 | 2022-10-18 | 에스케이하이닉스 주식회사 | Transmitting circuit improving data eye, semiconductor apparatus and semiconductor system including the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1578116A (en) * | 2003-07-30 | 2005-02-09 | 三美电机株式会社 | Voltage generating circuit |
| CN101079018A (en) * | 2007-01-29 | 2007-11-28 | 威盛电子股份有限公司 | Locking source synchronous selection pass receiver device and method |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6748549B1 (en) * | 2000-06-26 | 2004-06-08 | Intel Corporation | Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock |
| JP2002215333A (en) * | 2001-01-15 | 2002-08-02 | Nec Microsystems Ltd | Data transfer system, and computer provided with the same |
| CN1196047C (en) * | 2002-05-21 | 2005-04-06 | 矽统科技股份有限公司 | Clock pulse for producing alignment and circuit structure of document signal |
| KR100500929B1 (en) * | 2002-11-27 | 2005-07-14 | 주식회사 하이닉스반도체 | Delay locked loop circuit |
| KR100543910B1 (en) * | 2003-05-30 | 2006-01-23 | 주식회사 하이닉스반도체 | Digital delay locked loop and method for controlling thereof |
| JP4050303B2 (en) * | 2004-05-17 | 2008-02-20 | 三菱電機株式会社 | Phase locked loop (PLL) circuit, phase synchronization method thereof, and operation analysis method thereof |
| US7171321B2 (en) * | 2004-08-20 | 2007-01-30 | Rambus Inc. | Individual data line strobe-offset control in memory systems |
| FR2882871A1 (en) * | 2005-03-01 | 2006-09-08 | Atmel Corp | LOW VOLTAGE CONTROLLED VOLTAGE CONTROL OSCILLATOR AND ASSOCIATED PHASE LOOP |
| US7593497B2 (en) * | 2005-10-31 | 2009-09-22 | Teradyne, Inc. | Method and apparatus for adjustment of synchronous clock signals |
| US20080046771A1 (en) * | 2006-08-16 | 2008-02-21 | Chi-Chun Hsu | Adjustable delay compensation circuit |
| US20080144405A1 (en) * | 2006-12-18 | 2008-06-19 | Intel Corporation | Data strobe timing compensation |
| US7733711B2 (en) * | 2008-09-08 | 2010-06-08 | Freescale Semiconductor, Inc. | Circuit and method for optimizing memory sense amplifier timing |
-
2012
- 2012-06-20 TW TW101122105A patent/TWI482030B/en active
- 2012-06-21 CN CN201610183487.0A patent/CN105893310B/en active Active
- 2012-06-21 CN CN201610182760.8A patent/CN105868150B/en active Active
- 2012-06-21 CN CN201610184151.6A patent/CN105808484B/en active Active
- 2012-06-21 CN CN201610182788.1A patent/CN105808483B/en active Active
- 2012-06-21 CN CN201610183496.XA patent/CN105868152B/en active Active
- 2012-06-21 CN CN201610184153.5A patent/CN105808485B/en active Active
- 2012-06-21 CN CN201610182769.9A patent/CN105868151B/en active Active
- 2012-06-21 CN CN201210211885.0A patent/CN102799551B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1578116A (en) * | 2003-07-30 | 2005-02-09 | 三美电机株式会社 | Voltage generating circuit |
| CN101079018A (en) * | 2007-01-29 | 2007-11-28 | 威盛电子股份有限公司 | Locking source synchronous selection pass receiver device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201301048A (en) | 2013-01-01 |
| CN105808483A (en) | 2016-07-27 |
| CN105893310B (en) | 2019-04-26 |
| CN105868151B (en) | 2018-11-27 |
| CN105868152A (en) | 2016-08-17 |
| CN105808485B (en) | 2018-11-27 |
| CN105868150B (en) | 2019-02-01 |
| CN105868152B (en) | 2018-11-27 |
| CN105893310A (en) | 2016-08-24 |
| CN105808483B (en) | 2018-11-02 |
| CN105808484A (en) | 2016-07-27 |
| CN102799551A (en) | 2012-11-28 |
| CN105868151A (en) | 2016-08-17 |
| TWI482030B (en) | 2015-04-21 |
| CN105808485A (en) | 2016-07-27 |
| CN105868150A (en) | 2016-08-17 |
| CN105808484B (en) | 2019-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8782459B2 (en) | Apparatus and method for advanced synchronous strobe transmission | |
| US20040222857A1 (en) | Phase detector for a programmable clock synchronizer | |
| US8839018B2 (en) | Programmable mechanism for optimizing a synchronous data bus | |
| US10133700B2 (en) | Source synchronous data strobe misalignment compensation mechanism | |
| CN104283665A (en) | Point to multi-point clock-forwarded signaling for large displays | |
| US8683253B2 (en) | Optimized synchronous strobe transmission mechanism | |
| US8751851B2 (en) | Programmable mechanism for synchronous strobe advance | |
| CN102799551B (en) | The Apparatus for () and method therefor of synchronous selection pass transmission in advance | |
| US8782460B2 (en) | Apparatus and method for delayed synchronous data reception | |
| US8751850B2 (en) | Optimized synchronous data reception mechanism | |
| US8751852B2 (en) | Programmable mechanism for delayed synchronous data reception | |
| Sawyer | Source-synchronous serialization and deserialization (up to 1050 Mb/s) | |
| US20080180145A1 (en) | Apparatus and method for locking out a source synchronous strobe receiver | |
| CN101183995A (en) | Phase aligning method when rearranging main/slave clock and main/slave clock system | |
| US11190331B1 (en) | Data alignment in physical layer device | |
| CN102394808A (en) | Method and apparatus for phase adaption and frame alignment of serial media independent interface of ethernet network | |
| WO2009069094A1 (en) | Method and device for routing data between components | |
| Melo et al. | An inter-FPGA communication bus with error detection and dynamic clock phase adjustment | |
| US8729945B2 (en) | Printed circuit board and method for controlling signal timing sequence thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |