CN102799060B - Dummy pattern and the method for forming dummy pattern - Google Patents
Dummy pattern and the method for forming dummy pattern Download PDFInfo
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- CN102799060B CN102799060B CN201110137642.2A CN201110137642A CN102799060B CN 102799060 B CN102799060 B CN 102799060B CN 201110137642 A CN201110137642 A CN 201110137642A CN 102799060 B CN102799060 B CN 102799060B
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Abstract
The present invention discloses a kind of dummy pattern and the method for forming dummy pattern, and this method provides layout areas first, and layout patterns are included in the layout areas, and the layout patterns have the first density.With after inserting multiple first dummy patterns in the layout patterns, these first dummy patterns have the second density, and second density corresponds to first density.Next split the layout areas to define many sub-regions, these subregions have triple density respectively, exported according to the size of these the first dummy patterns of the triple density Yu the discrepancy adjustment of second density, and by the layout patterns and first dummy pattern to photomask.
Description
Technical field
It is espespecially a kind of for flatening process the present invention relates to a kind of dummy pattern and the method for forming dummy pattern
Dummy pattern and the method for forming dummy pattern.
Background technology
With the progress of semiconductor technology, the size of the distribution of each element and each element of connection constantly contracts in integrated circuit
It is small, and in order to form the fine pattern with pinpoint accuracy, the flatness requirement of substrate surface is also lifted therewith.Known technology
In, often with chemically mechanical polishing (chemical mechanical polishing, hereinafter referred to as CMP) technique as main
Flatening process, and chemically-mechanicapolish polish the grinding result of (CMP) technique, it is very huge on the pattern influence being subsequently formed.In detail
Ground is said, when being chemically-mechanicapolish polished (CMP) technique, and the grinding rate in low pattern density region is higher than high pattern density region
Grinding rate.Therefore, the different region of pattern density obtains different thickness after chemically mechanical polishing (CMP) technique, also
Obtain uneven surface.In addition to thickness is different, uneven substrate surface more causes the pattern dimension being subsequently formed to miss
The problem of difference and serious uniformity (critical dimension uniformity, CDU) bad grade of critical size.And scheme
The different influences for semiconductor technology of case density, are more not limited in chemically mechanical polishing (CMP) technique.The skill as this area
Known to art personnel, the difference of pattern density is also possible to cause etching excessively or erosion in Patternized technique (such as in etch process)
Carve endless congruence negative effect.
In order to solve the above problems, it is known that technology has been developed the random number in low pattern density region and sets dummy pattern
Method.By increasing dummy pattern, more average pattern density can be obtained in substrate, and thus improves chemically mechanical polishing
(CMP) uniformity and flattening effect of technique, and etch process etching result.
It is well known, however, that the dummy pattern set in technology in low pattern density region, to be arranged in array (array),
And the pattern with formed objects and same shape.Although dummy pattern can improve low pattern density region and high pattern density area
The density variation in domain, but with the complication of IC design, more areas with different pattern density are dispersed with chip
Domain so that dummy pattern is limited for the improvement of pattern density difference, even more so that dummy pattern is poor for pattern density
Different improvement declines.Furthermore it is known that dummy pattern still have between different pattern density area in substrate produce
Stress resistance it is not enough, the shortcomings of elongate optical proximity effect amendment (optical proximity correction, OPC).
Therefore, a kind of new dummy pattern and the method for forming dummy pattern are stilled need in semiconductor technology.
The content of the invention
It is therefore an object of the present invention to be to provide a kind of dummy pattern for improving technique uniformity result and formation
The method of dummy pattern.
According to claim provided by the present invention there is provided a kind of method for forming dummy pattern, this method is provided first
Include layout patterns in layout areas, the layout areas, and the layout patterns have the first density.Next in the layout patterns
Multiple first dummy patterns of middle insertion, these first dummy patterns have the second density, and second density correspond to this first
Density.Then, the layout areas is split to define many sub-regions, these subregions have triple density respectively.It is to be obtained to be somebody's turn to do
After triple density, according to the size of these the first dummy patterns of the triple density Yu the discrepancy adjustment of second density.Finally, will
The layout patterns are exported to photomask with these first dummy patterns.
According to claim provided by the present invention, a kind of semiconductor layout with dummy pattern is separately provided.This is partly led
Body layout includes component placement pattern, the dummy pattern of multiple quadrangles first and the dummy pattern of multiple quadrangles second.This
A little first dummy patterns have first size respectively；And these dummy patterns of quadrangle second have different (varied) respectively
Second size.
Method according to dummy pattern provided by the present invention with forming dummy pattern, can according to the layout patterns this
First dummy pattern of one density formation with second density, the difference of height pattern density is homogenized with the first step.Connect down
Come the concept for using subregion to inspect, partitioning layout region is gone back to define these subregions, and obtaining being somebody's turn to do for these subregions
After triple density, being somebody's turn to do in all subregion is adjusted according to the difference of the triple density of all subregion and second density respectively
The size of first dummy pattern, more accurately to adjust the pattern density of each subregion.In other words, by further adjusting
The size of first dummy pattern in each subregion, can distinguish the subregion that script has different pattern density to wisdom
Adjust to substantially the same pattern density.Therefore, after the size for adjusting first dummy pattern, the pattern of all subregion
Density can be homogenized, and be more beneficial for chemically-mechanicapolish polishing the progress of (CMP) technique, and can improve chemically mechanical polishing (CMP) work
The planarization results of skill.
Brief description of the drawings
Fig. 1 is the flow chart of first and second preferred embodiment of the method for formation dummy pattern provided by the present invention.
Fig. 2 to Fig. 8 shows for first and second preferred embodiment of the method for formation dummy pattern provided by the present invention
It is intended to, wherein, Fig. 5 is Fig. 4 enlarged schematic partial view, and Fig. 6 and Fig. 8 is respectively the change type that this preferred embodiment is provided
Schematic diagram.
Fig. 9 and Figure 10 is the schematic diagram of third preferred embodiment provided by the present invention.
Description of reference numerals
10~22 steps
The component placement pattern of 100 layout areas 110
120 first dummy pattern 120a are combined list structure
The dummy pattern of 130 second dummy pattern 140 the 3rd
142nd, the interlayer hole dummy pattern of 144 diagonal 150
1001st, 1002,1003...100n subregions
a1、b1、b2、b3、c1、c2
l1、l2、l3Length w1、w2w3Width
b4、c3Offset distance
Embodiment
Fig. 1 to Fig. 8 is referred to, wherein Fig. 1 is the first preferred reality of the method for formation dummy pattern provided by the present invention
The flow chart of example is applied, Fig. 2 to Fig. 8 is the signal of the first preferred embodiment of the method for formation dummy pattern provided by the present invention
Figure, Fig. 5 is then Fig. 4 enlarged schematic partial view.As shown in Figures 1 and 2, this preferred embodiment is carried out first：
Step 10：There is provided and component placement pattern is formed in layout areas, the layout areas.
Persons skilled in the art are, it should be understood that be the original for being provided circuit design engineer when making integrated circuit
Beginning circuit layout pattern is formed on photomask, then the pattern on photomask is transferred into target film via photoetching and etch process
On layer, the wafer product of coincident circuit design function can be produced.In the preferred embodiment, to be formed in target layer
Region included by the photomask of layout patterns, is the layout areas 100 that this preferred embodiment is provided, and is painted in Fig. 2
Section layout region 100 is shown.Component placement pattern 110 provided in this preferred embodiment may include circuit design engineering
Teacher or the ifq circuit component placement pattern provided, such as intraconnections layout patterns or circuit layout pattern, but not limited to this.
And this ifq circuit layout patterns not only may include efficient circuit pattern, it also may include the void that circuit design engineer is pre-designed
If pattern (not shown).Next, referring again to Fig. 1, Fig. 2 and Fig. 5：
Step 12：In inserting multiple first dummy patterns in the component placement pattern.
It is in multiple first dummy patterns 120 of insertion in component placement pattern 110 according to step 12.It is worth noting that,
First dummy pattern 120 is the dummy pattern of strip (bar-like), and the first dummy pattern 120 is as shown in Fig. 2 may be disposed at
Between component placement pattern 110, can also discontinuous mode spread configuration in the periphery of component placement pattern 110.In addition, this
Preferred embodiment can adjust the dummy pattern of strip first according to the first dummy pattern 120 and the relation of component placement pattern 110
120 length.In other words, the first dummy pattern 120 include first size, and first size can according to itself set location with
The relation of component placement pattern 110 and it is different.In addition as shown in figure 5, the first dummy pattern 120 has with component placement pattern 110
There is spacing a1, in the preferred embodiment, spacing a1Can be 0.2 micron (micrometer, μm), but not limited to this.It is worth noting
, spacing a1Can be the minimum spacing that component placement pattern 110 works as layout layer specification, and spacing a1Maximum can be about 2 μm.
In addition, the first dummy pattern 120 can include single strip (single bar-like) pattern as shown in Figure 2, but in response to double picture
The demand of case technology (double patterning technology, DPT), the first dummy pattern 120 also may include a plurality of
Shape (multiple bar-like) pattern.
Persons skilled in the art, it should be understood that on target layer formed layout patterns when, alienation area of the pattern (iso
Region) with intensive area of the pattern (dense region) boundary, the normal dense graph caused by the difference of two zone map density
Larger stress (stress) is born in case region in process, or even causes serious pattern deformation (pattern
Distortion) the problems such as.Therefore, this preferred embodiment sets in the periphery of each component placement pattern 110 and generally surrounds member
First dummy pattern 120 of part layout patterns 110, to protect (shield) component placement pattern 110, it is to avoid component placement figure
The influence that case 110 is stressed, can more avoid pattern deformation.
In addition Fig. 8, the schematic diagram for the change type that Fig. 8 is provided for this preferred embodiment also be see.In this schematic diagram,
Disclose the first dummy pattern 120 and the relation of component placement pattern 110 to be clear, thus only show the first dummy pattern 120 with
Component placement pattern 110, but persons skilled in the art can also may include that other are empty according to subsequently illustrating have a clear understanding of in Fig. 8
If pattern.As shown in figure 8, the first dummy pattern 120 disclosed by this change type may include closed figure, and the closed figure is complete
The component placement pattern 110 surrounded entirely in a certain region.In addition as also shown in Figure 8, the first dummy pattern 120 can be single strip
Structure, can also need according to technique or product demand includes compound list structure 120a.Next, referring to Fig. 1, Fig. 3 and figure
5：
Step 14：In inserting multiple second dummy patterns in the component placement pattern, the component placement pattern, the plurality of
One dummy pattern has the first density with the plurality of second dummy pattern.
According to step 14, next in multiple second dummy patterns 130 of insertion in component placement pattern 110, second is illusory
Pattern 130 is as shown in Fig. 3 and Fig. 5, in array distribution in layout areas 100.With component placement pattern 110 immediate second
Dummy pattern 130 has spacing b with component placement pattern 1101, with furthest second dummy pattern of component placement pattern 110
130 have spacing b with component placement pattern 1102, and each second dummy pattern 130 to each other then have spacing b3.At this
In preferred embodiment, spacing b1For more than or equal to 0.6 μm, spacing b2Can be then 2.6 μm, and spacing b3Then between 90~210 nanometers
(nanometer, nm).Spacing b1With spacing b2Also it can need to adjust therefore not limited to this according to actual process and product；And second is illusory
The spacing b of pattern 130 to each other3It is premised on without optical proximity effect amendment (OPC).Second dummy pattern 130 is
The dummy pattern of quadrangle (rectangular), and be preferably the dummy pattern of square.As shown in figure 5, the second dummy pattern
130 length l1With width w1All between 240~360nm.It is worth noting that, the shape of the second dummy pattern 130, size are all
It is identical, that is to say, that each second dummy pattern 130 includes the size of identical second.And between each second dummy pattern 130
All there is skew (offset) in X-direction and Y-direction apart from b4, in the preferred embodiment, offset distance b4For between 0~
300nm, but it is also not limited to this.It is otherwise noted that said elements layout patterns 110, the first dummy pattern 120 and second
Dummy pattern 130 can be considered layout patterns, and this layout patterns includes the first density X.
Persons skilled in the art are, it should be understood that on target layer after formation layout patterns, especially form gold to be inserted
It is to insert groove using metal material when being filled technique after the channel patterns for belonging to layer, now alienation area of the pattern and close
The hole speed of filling out at collection area of the pattern edge often fills out hole speed less than intensive area of the pattern.So after fill process, alienation
The unfilled defect of groove often can be observed in the edge of area of the pattern or intensive area of the pattern.Therefore, this preferred embodiment be in
The periphery of each component placement pattern 110 sets the second dummy pattern 130, produces the environment of intensive pattern, increases alienation pattern
The pattern density of region and intensive pattern edges of regions, fills out hole speed, and improve filling out for fill process with lift these regions
Fill result.Next, referring to Fig. 1, Fig. 4 and Fig. 5：
Step 16：Multiple 3rd dummy patterns are inserted, the 3rd dummy pattern has the second density.
According to step 16, next in layout patterns (including component placement pattern 110, the first dummy pattern 120 and second
Dummy pattern 130) interior multiple 3rd dummy patterns 140 of insertion.3rd dummy pattern 140 as shown in figs. 4 and 5, is divided in array
Be distributed in layout areas 100, and with immediate 3rd dummy pattern 140 of component placement pattern 110 and component placement pattern 110
With spacing c1, in the preferred embodiment, spacing c1More than 3 μm, but spacing c1Also it can need to adjust according to actual process and product
It is whole, and not limited to this.3rd dummy pattern 140 is the dummy pattern of quadrangle, and is preferably the dummy pattern of square.As schemed
Shown in 5, the length l of the 3rd dummy pattern 1402With width w2All between 460~740nm.In addition, each 3rd dummy pattern 140 that
Spacing c around here2Between 160~440nm, and each 3rd dummy pattern 140 in Y-direction each other in X-direction with all having
Offset distance c3, in the preferred embodiment, offset distance c3Between 0~600nm, but it is also not limited to this.Such as Fig. 4 and Fig. 5 institutes
Show, the first dummy pattern 120 and the second dummy pattern 130 be all arranged at the 3rd dummy pattern 140 and component placement pattern 110 it
Between；And the first dummy pattern 120 is arranged between the second dummy pattern 130 and component placement pattern 110.
It is worth noting that, when setting three dummy patterns 140, the 3rd dummy pattern 140 has the second density Y, and
Second density Y corresponds to foregoing first density X.As it was previously stated, in the preferred embodiment, the first density X is component placement figure
The density of case 110, the first dummy pattern 120 and the 3rd dummy pattern 130, therefore when setting three dummy patterns 140, can root
The the first density X listed according to following form one class interval obtains the second different density Y：
Form one
| First density X | Second density Y |
| X ＜ 37.4% | 34.8% |
| 37.4%≤X ＜ 42.7% | 40.0% |
| 42.7%≤X ＜ 48.5% | 45.5% |
| 48.5%≤X ＜ 54.4% | 51.3% |
| 54.4%≤X | 57.6% |
For example, when the first density X be more than or equal to 37.4% and less than 42.7% when, judge the second density Y as
40.0%, therefore set using the second density Y as 40.0% when three dummy patterns 140 is set.In addition, in this preferred embodiment
In, the second density Y can also be regarded as adjusting the target density of semiconductor element layout patterns density, to equalize pattern density.So
And it should be noted that, although this preferred embodiment only provides five groups of class intervals to adjust target density, but the present invention also may be used
There is provided more packet levels away from and corresponding target density, to strengthen the equalization degree of pattern density.Fig. 1 and Fig. 5 are referred to,
Followed by：
Step 18：Split the layout areas to define many sub-regions, the plurality of subregion has triple density respectively.
According to step 18, following partitioning layout region 100, with define many sub-regions 1001,1002,
1003...100n etc., and all subregion 1001,1002,1003...100n length and width it is all equal.For example, at this preferably
The length and width of all subregion are all equal to 125 μm, but not limited to this in embodiment.As shown in figure 5, subregion 1001,1002,
1003...100n component placement pattern 110, the first dummy pattern 120 and the second dummy pattern 130 may be included simultaneously, or
The second dummy pattern 130 and the 3rd dummy pattern 140 may be included simultaneously, the 3rd dummy pattern 140 may be only included certainly.
After defining subregion 1001,1002,1003...100n, calculate respectively all subregion 1001,1002, in 1003...100n
Pattern density, and obtain the triple density Z of subregion respectively.As previously described, because all subregion 1001,1002,
1003...100n one to four kind of different pattern is potentially included, therefore the triple density Z variations of subregion are very big.In other words
Say, all subregion 1001,1002,1003...100n are pattern density and the second density Y (i.e. target density) in itself with poor
It is different, and the uneven region of difference.
In addition, referring to Fig. 6, Fig. 6 is the schematic diagram of another change type of this preferred embodiment.It is each during at this, change is formed
Subregion 1001,1002,1003...100n also can be overlapping.Fig. 1 and Fig. 7 are referred to, followed by：
Step 20：According to the triple density and the size of the plurality of 3rd dummy pattern of discrepancy adjustment of second density.
As previously described, because all subregion 1001,1002,1003...100n are pattern density and the second density Y in itself
(i.e. target density) has difference, and the uneven region of difference, therefore in step 20, according to triple density Z and the second density Y
Relation adjustment all subregion 1001,1002, the size of the 3rd dummy pattern 140 in 1003...100n, and pass through adjustment the
The size of three dummy patterns 140 changes all subregion 1001,1002,1003...100n pattern density, complies with second close
Spend Y (i.e. target density) requirement.In the preferred embodiment, the second density Y, triple density Z and the chi of the 3rd dummy pattern 140
Very little relation is as shown in following table lattice two and form three：
Form two
Form three
| Code name | Subregion pattern density V after adjustment | 3rd dummy pattern size (unit：nm) |
| a | 60.80% | 740×740 |
| b | 57.60% | 720×720 |
| c | 54.40% | 700×700 |
| d | 51.30% | 680×680 |
| e | 48.50% | 660×660 |
| f | 45.50% | 640×640 |
| g | 42.70% | 620×620 |
| h | 40.00% | 600×600 |
| i | 37.40% | 580×580 |
| j | 34.80% | 560×560 |
| k | 32.40% | 540×540 |
| l | 30.00% | 520×520 |
| m | 27.70% | 500×500 |
| n | 25.60% | 480×480 |
| o | 23.50% | 460×460 |
For example, when the first density X be more than or equal to 37.4% and less than 42.7% when, you can judge the second density Y as
40.0%, and when the triple density Z of the subregion 1001 obtained by segmentation definition is more than 59.2%, code name is obtained according to form two
o.Then understand that code name o represents the 3rd dummy pattern 140 in subregion 1001 need to be dimensioned so as into length and width according to form three
It is all 460nm, the subregion pattern density V after adjustment is reduced to 23.50%, is homogenized the son for being more than the second density Y originally
The pattern density in region 1001.And when another subregion 100n triple density Z is less than or equal to 24.5%, obtained according to form two
Obtain code name a.Then understand that code name a represents that the size of the 3rd dummy pattern 140 in subregion 100n need to be set according to form three
It is all 740nm for length and width, the subregion pattern density V after adjustment is improved to 60.80%, be more than the second density originally to be homogenized
Y subregion 100n pattern density.The size of the 3rd dummy pattern 140 is adjusted by subregion, reaches adjustment with being homogenized each son
The pattern density in region complies with the purpose of the second density Y (i.e. target density).Therefore the global density in final layout region 100
The second density Y can be essentially equal to, that is, obtains average pattern density.Referring again to Fig. 1, finally carry out：
Step 22：By the component placement pattern, the plurality of first dummy pattern, the plurality of second dummy pattern, many with this
Individual 3rd dummy pattern, which is exported to photomask, forms semiconductor layout's pattern.
According to step 22, semiconductor layout's pattern that this can be had to the good uniformity is formed to photomask, and is carried out
Required subsequent technique.It is worth noting that, in the semiconductor layout's pattern finally obtained, the first dummy pattern 120 and the 3rd
Dummy pattern 140 has different first sizes and the 3rd size；And the second dummy pattern 130 then has the chi of identical second
It is very little, and threeth size of second size less than the 3rd dummy pattern 140 of the second dummy pattern 130.
According to this first preferred embodiment, the first dummy pattern is set with its periphery among component placement pattern 110
120, with protection element layout patterns 110, it is to avoid component placement pattern 110 is by alienation pattern and the pattern density of intensive pattern
The influence of caused stress.This first preferred embodiment is also in setting the second dummy pattern 120 in layout areas 100, to manufacture
Go out the environment of intensive pattern, increase alienation area of the pattern and the pattern density of intensive pattern edges of regions, to lift these regions
Fill out hole speed, and improve the filling result of fill process.Importantly, this first preferred embodiment is to form the 3rd void
If after pattern 140, being also partitioned into subregion 1001,1002,1003...100n.And according to the triple density Z and mesh of subregion
Density Y difference is marked, respectively the size and the 3rd dummy pattern density V of the 3rd dummy pattern 140 in adjustment all subregion, with
Wisdom the subregion with different pattern density is separately adjusted to angularly with substantially the same pattern density, makes layout areas
Global density in 100 is homogenized, semiconductor layout's pattern to acquisition eventually with the good uniformity, and being more beneficial for
The progress of mechanical polishing (CMP) technique is learned, and the planarization results of chemically mechanical polishing (CMP) technique can be improved.
Fig. 1 is please referred to again, and Fig. 1 can be the second preferred embodiment of the method for formation dummy pattern provided by the present invention
Flow chart.It is worth noting that, the most step of the second preferred embodiment is same as first preferred embodiment, therefore adopted in this
Illustrated with identical component symbol, and the relevant drawings of these identical step, i.e. step 10~steps 22 also see Fig. 2 extremely
Fig. 8, is all repeated no more herein.Second preferred embodiment is with first preferred embodiment difference：Second preferred embodiment
In, be with partitioning layout region 100 with define multiple subregions 1001 with different triple density Z, 1002,
1003...100n, and according to this two step of triple density Z and the second density Y size of the 3rd dummy pattern of discrepancy adjustment 140
Carried out for circulating repetition.In other words, the second preferred embodiment repeats step 18 and step 20：Partitioning layout region 100
To define many sub-regions 1001,1002,1003...100n, and these subregions 1001,1002,1003...100n has respectively
There is triple density Z；Then according to the size of these the 3rd dummy patterns 140 of triple density Z and the second density Y discrepancy adjustment.
It is worth noting that, before the size of the subregion redefined in the preferred embodiment in each circulation is different from
The size of subregion defined in one circulation.That is, repeating partitioning layout region 100 to define subregion
The step of in, the subregion 1001 that defines for each time, 1002,1003...100n have different sizes.Therefore in each circulation
In redefine each subregion 1001,1002,1003...100n all may obtain different from previous cycle triple density
Z, and the 3rd chi of the 3rd dummy pattern 140 in all subregion can be adjusted once again by triple density Z and the second density Y difference
It is very little, and thus reach that adjustment complies with the mesh of the second density Y (i.e. target density) with the pattern density in homogenizing all subregion
's.The 3rd size of the 3rd dummy pattern 140 is constantly adjusted by repeatedly circulation, can be by the pattern density of different subregions most
Goodization so that the global density in final layout region 100 can be essentially equal to the second density Y, that is, it is close to obtain average pattern
Degree.
According to this second preferred embodiment, except still setting the first dummy pattern 120, with protection element layout patterns
110, it is to avoid component placement pattern 110 is influenceed by alienation pattern with stress caused by the pattern density of intensive pattern；And
Second dummy pattern 120 is set, to increase the pattern density of alienation area of the pattern and intensive pattern edges of regions, improves filling work
The filling result of skill.Importantly, this preferred embodiment is after the 3rd dummy pattern 140 is formed, also repeat point
Cut out subregion 1001,1002,1003...100n.And the difference of the triple density Z and target density Y according to subregion, respectively
The step of the 3rd size and the 3rd dummy pattern density of the 3rd dummy pattern 140 in adjustment all subregion.As it was previously stated, logical
After the size for repeatedly adjusting the 3rd dummy pattern 140, the 3rd dummy pattern that this preferred embodiment can be optimized after adjustment is close
V is spent, the different subregions with different pattern density are separately adjusted to angularly with substantially the same pattern density, make layout
Global density in region 100 is homogenized, semiconductor layout's pattern to acquisition eventually with the good uniformity, and more favourable
In the progress of chemically mechanical polishing (CMP) technique, and the planarization results of chemically mechanical polishing (CMP) technique can be improved.
Fig. 9 and Figure 10 are referred to, Fig. 9 and Figure 10 is the schematic diagram of third preferred embodiment provided by the present invention.First
It should be noted because third preferred embodiment is only related to the 3rd dummy pattern 140 in first and second preferred embodiment, therefore
The 3rd dummy pattern 140 is also illustrated in Fig. 9 and Figure 10, with clear announcement third preferred embodiment and the 3rd dummy pattern 140
Space configuration relation.According to this third preferred embodiment, when first preferred embodiment and the second preferred embodiment formed half
Conductor layout pattern is intraconnections layout patterns, and this intraconnections layout patterns, which is removed, includes component placement pattern 110, i.e. intraconnections cloth
Groove (trench) pattern in office's pattern, further comprises the dummy pattern that circuit design engineer is pre-designed, and above-mentioned
The first dummy pattern 120, the second dummy pattern 130 and the 3rd dummy pattern 140.Then third preferred embodiment is also in formation
State and corresponding interlayer hole pattern be provided after semiconductor layout's pattern, this interlayer hole pattern except including ifq circuit layout patterns it
Outside, multiple interlayer hole dummy patterns 150 are further comprises, the density to be homogenized interlayer hole pattern is formed while increasing interlayer hole
Film layer, and low dielectric constant material layer support force.As shown in figure 9, interlayer hole dummy pattern 150 is quadrangle patterns, and
Preferably square pattern.In addition, interlayer hole dummy pattern 150 or the dummy pattern with same shape and formed objects,
Its length l3With width w3All between 72~180nm.
Importantly, interlayer hole dummy pattern 150 corresponds to set by the 3rd dummy pattern 140.As shown in figure 9, interlayer
Hole dummy pattern 150 corresponds to set by the central point of the 3rd dummy pattern 140, therefore interlayer hole dummy pattern 150 is arranged at the
Overlapped in the range of three dummy patterns 140.Interlayer hole dummy pattern 150 also can be as shown in Figure 10, along the 3rd illusory figure
The diagonal of case 140 is set, and interlayer hole dummy pattern 150 is arranged in the range of the 3rd dummy pattern 140 and overlapped.
In addition, for the interlayer hole dummy pattern 150 in the different numbers of plies, can also use different set-up modes.For example, odd number layer
Diagonal 142 of the interlayer hole dummy pattern 150 along the 3rd dummy pattern 140 set；And the interlayer hole dummy pattern of even level
150 are set along another diagonal 144 of the 3rd dummy pattern 140, and diagonal 142 and diagonal 144 are interlaced with each other.
According to this third preferred embodiment, there is provided interlayer hole dummy pattern 150.Therefore it is subsequently formed illusory in interlayer hole
Metal material in pattern 150 can strengthen the intensity of low dielectric constant material layer in internal connection-wire structure.Even more noteworthy, originally
Third preferred embodiment intermediary layer hole dummy pattern 150 is all corresponded to set by the 3rd dummy pattern 140, and is arranged at the 3rd
Overlapped in the range of dummy pattern 140.Due to the component placement pattern 110 of the 3rd dummy pattern 140 and efficient circuit
It is distant, therefore the also distancing element layout patterns of interlayer hole dummy pattern 150 set corresponding to the 3rd dummy pattern 140
110 is distant.That is the distance of interlayer hole dummy pattern 150 and component placement pattern 110 and the 3rd dummy pattern 140
With the spacing c of component placement pattern 1101It is substantially the same, all more than 3 μm.
According to this design, when making internal connection-wire structure, if because product or process requirements need adjustment element layout patterns
110th, during the configuration of the first dummy pattern 120, the second dummy pattern 130 and the 3rd dummy pattern 140, with active component layout
The distant interlayer hole dummy pattern 150 of case 110 can not change layout patterns and on the premise of photomask need to being re-formed,
Still avoid overlapping with component placement pattern 110, cause the circuit malfunction being subsequently formed.In other words, it is preferred according to the originally the 3rd
The interlayer hole dummy pattern 150 that embodiment is provided, should be away from because it has feature with distancing element layout patterns 110 farther out
From the buffer area that can avoid changing interlayer hole layout patterns as providing, it is possible to decrease the chance of modification interlayer hole layout patterns,
Reaching reduces the target of cost.
It is otherwise noted that the second dummy pattern 130 between different layout film layers has with the 3rd dummy pattern 140
Fixed relative position, and to be also generally slightly same as the 3rd dummy pattern 140 and interlayer hole in Fig. 9 illusory for the relative position relation
The relative position relation of pattern 150, i.e. the second dummy pattern 130 may be disposed in the range of the 3rd dummy pattern 140 and and its
It is overlapping, but not limited to this.Because the second dummy pattern between different layout film layers has the phase of fixation with the 3rd dummy pattern 140
To position, therefore it can obtain optimized parasitic capacitance reducing effect.
According to the method for formation dummy pattern provided by the present invention, it is preferable to carry out according to above-mentioned first, second with the 3rd
Step disclosed by example can scheme the semiconductor layout on the photomask in forming semiconductor layout's pattern on photomask
Case is transferred on target layer, each processing step needed for then carrying out.Therefore, dummy pattern provided by the present invention includes defeated
The pattern gone out to photomask, also including being transferred to the pattern of target layer.
In summary, the method according to dummy pattern provided by the present invention with forming dummy pattern, can be according to the layout
Threeth dummy pattern of the first density formation with the second density (i.e. target density) of pattern, height pattern is homogenized with the first step
The difference of density.Next the concept inspected using subregion, goes back partitioning layout region to define subregion, and obtaining these
After the triple density of subregion, adjusted respectively in all subregion according to the difference of the triple density of all subregion and the second density
The 3rd dummy pattern size, further to adjust the pattern density of all subregion, and reach and accurately adjust each sub-district
The purpose of the pattern density in domain.In other words, can by further adjusting the size of the 3rd dummy pattern in each subregion
Wisdom the subregion with different pattern density is separately adjusted to angularly with substantially the same pattern density.Therefore, adjust
After the size of first dummy pattern, the pattern density of all subregion can be homogenized, and be more beneficial for chemically-mechanicapolish polishing (CMP) work
The progress of skill, and the planarization results of chemically mechanical polishing (CMP) technique can be improved.In addition, being thrown except chemical machinery can be improved
The planarization of light (CMP) technique and uniformity result, dummy pattern provided by the present invention is with forming the method for dummy pattern also
It is beneficial to the etching result of Patternized technique such as etch process.
The preferred embodiments of the present invention are the foregoing is only, all equivalent variations done according to the claims in the present invention are with repairing
Decorations, should all belong to the covering scope of the present invention.
Claims (18)
1. a kind of method for forming dummy pattern, including：
Layout areas is provided, component placement pattern, multiple first dummy patterns and multiple second illusory are included in the layout areas
Pattern and with the first density；
Multiple 3rd dummy patterns are inserted in the component placement pattern, the plurality of 3rd dummy pattern has the second density, and
Second density corresponds to first density；
Segmentation includes the component placement pattern, the plurality of first dummy pattern, the plurality of second dummy pattern and the plurality of 3rd
The layout areas of dummy pattern is to define many sub-regions, and the plurality of subregion has triple density respectively；
According to the size of the 3rd dummy pattern in the discrepancy adjustment of the triple density and second the density respectively subregion；With
And
Export the component placement pattern and the plurality of first dummy pattern, the plurality of second dummy pattern and the plurality of 3rd are illusory
On pattern to photomask.
2. forming the method for dummy pattern as claimed in claim 1, the wherein component placement pattern includes intraconnections layout
Case or circuit layout pattern.
3. the method for dummy pattern is formed as claimed in claim 1, wherein the plurality of second dummy pattern and the plurality of 3rd
Dummy pattern is sequentially inserted into the component placement pattern before the plurality of first dummy pattern is formed.
4. the method for dummy pattern is formed as claimed in claim 1, wherein the plurality of first dummy pattern is illusory including strip
Pattern, the plurality of 3rd dummy pattern includes quadrangle dummy pattern.
5. the method for dummy pattern is formed as claimed in claim 1, wherein the plurality of second dummy pattern includes different chis
Very little, the plurality of 3rd dummy pattern includes identical size.
6. the method for dummy pattern is formed as claimed in claim 5, wherein the plurality of 3rd dummy pattern is less than the plurality of the
One dummy pattern.
7. the method for dummy pattern is formed as claimed in claim 1, wherein the plurality of subregion overlaps each other.
8. forming the method for dummy pattern as claimed in claim 1, in addition to repeat to split the layout areas to define
Go out the plurality of subregion.
9. the method for dummy pattern is formed as claimed in claim 8, wherein repeating to split the layout areas to define
In the step of the plurality of subregion, the subregion defined for each time has different sizes.
10. the method for dummy pattern is formed as claimed in claim 2, wherein when the component placement pattern is intraconnections layout
During case, multiple interlayer hole dummy patterns are also provided, the plurality of interlayer hole dummy pattern corresponds to the 3rd dummy pattern.
11. a kind of photomask with the dummy pattern being made up of the method described in claim 1, including：
Intraconnections channel patterns, including component placement pattern；
Multiple dummy patterns of quadrangle first, the plurality of first dummy pattern has first size respectively；
Multiple dummy patterns of quadrangle second, wherein the plurality of second dummy pattern has the second different sizes respectively；
Multiple 3rd dummy patterns, the plurality of 3rd dummy pattern has the 3rd different sizes respectively；And
Multiple interlayer hole dummy patterns, are arranged in the range of the plurality of 3rd dummy pattern and overlap.
12. photomask as claimed in claim 11, wherein the plurality of first dummy pattern is arranged at the plurality of second illusory figure
Between case and the intraconnections channel patterns.
13. photomask as claimed in claim 11, the wherein first size are mutually the same, and less than second size.
14. photomask as claimed in claim 11, wherein the plurality of 3rd dummy pattern is quadrangle.
15. photomask as claimed in claim 14, wherein the plurality of 3rd dummy pattern be arranged at first dummy pattern with
Between the intraconnections channel patterns.
16. photomask as claimed in claim 14, wherein the plurality of 3rd dummy pattern is arranged at the intraconnections channel patterns
Between.
17. photomask as claimed in claim 14, wherein the plurality of 3rd dummy pattern surrounds the component placement pattern.
18. photomask as claimed in claim 17, wherein the plurality of 3rd dummy pattern includes closed figure.
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| CN103855044B (en) * | 2014-03-31 | 2016-09-07 | 上海华力微电子有限公司 | A kind of method adding redundant pattern |
| CN105631081B (en) * | 2014-11-27 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of insertion method of FinFET dummy pattern |
| CN105826314B (en) * | 2015-01-04 | 2019-05-03 | 旺宏电子股份有限公司 | Mask and semiconductor structure |
| US9747408B2 (en) * | 2015-08-21 | 2017-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Generating final mask pattern by performing inverse beam technology process |
| CN106898657B (en) * | 2015-12-21 | 2022-02-01 | 联华电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN108957943B (en) * | 2017-05-22 | 2021-02-19 | 联华电子股份有限公司 | Method for forming layout pattern |
| WO2020154862A1 (en) | 2019-01-28 | 2020-08-06 | Yangtze Memory Technologies Co., Ltd. | Systems and methods for designing dummy patterns |
| TWI803262B (en) * | 2022-01-04 | 2023-05-21 | 南亞科技股份有限公司 | Overlay measurement marks and overlay error correction marks |
| US11796924B2 (en) | 2022-01-04 | 2023-10-24 | Nanya Technology Corporation | Method for overlay error correction and method for manufacturing a semiconductor device structure with overlay marks |
| CN114647145B (en) * | 2022-05-23 | 2022-09-13 | 合肥新晶集成电路有限公司 | Photomask and semiconductor structure |
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