CN102789995B - Method of manufacture procedures for manufacturing metal protrusion and fusion welded metal - Google Patents
Method of manufacture procedures for manufacturing metal protrusion and fusion welded metal Download PDFInfo
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- CN102789995B CN102789995B CN201110131307.1A CN201110131307A CN102789995B CN 102789995 B CN102789995 B CN 102789995B CN 201110131307 A CN201110131307 A CN 201110131307A CN 102789995 B CN102789995 B CN 102789995B
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- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
A method of manufacture procedures for improving coplanarity of fusion welded metal on the surface of a metal protrusion structure is applicable to flip chip protrusion fusion welded technology of a semi-conductor chip. When metal protrusions with different sizes are arranged on the surface of a component, height unevenness after high-temperature processing of the fusion welded metal due to different sizes of the protrusions can be eliminated or reduced, and therefore difficulty of downstream testing and packaging is reduced. In order to achieve the purposes, the invention provides a method using two manufacture procedures. Metal protrusion area and fusion welded metal area are controlled respectively, and the coplanarity of the fusion welded metal is improved. The steps include: a first manufacture procedure and a second manufacture procedure. The first manufacture procedure is used for manufacturing the metal protrusion structure on the surface of a semi-conductor component, and the second manufacture procedure is used for manufacturing a fusion welded metal structure with different area on the surface of the metal protrusion.
Description
Technical field
The present invention is about a kind of manufacturing method thereof promoting metal lug surface added metal coplanarity, espespecially a kind of manufacturing method thereof is applicable to the crystal covering type projection fusion techniques of semiconductor wafer, and when element surface has the metal coupling of different size, can eliminate or reduce because of the added metal that causes of bump size difference problem highly uneven after high-temperature process, improve the degree of difficulty of downstream test and encapsulation by this.
Background technology
In recent years, along with the fast development of semiconductor technology, the encapsulation technology of semiconductor wafer is also showing improvement or progress day by day.In gallium arsenide wafer encapsulation, as power amplifier module or radio-frequency (RF) component, connect (wire bond) encapsulation technology based on line traditionally, namely utilize gold thread with the metallic contact of each element in the mutual connecting wafer of the mode of spot welding.In recent years line connect encapsulation technology gradually coating brilliant (flip chip) formula metal coupling welding (bump bond) encapsulation technology replaced.The major advantage of crystal covering type projection fusion techniques is that cost is lower, connect design and have more elasticity, and after encapsulation, size integration is better, therefore becomes the main flow of gallium arsenide wafer encapsulation technology gradually.
Crystal covering type projection fusion techniques replaces traditional gold thread with metal coupling.As shown in Figure 1A to Fig. 1 C, it is the surface metal projection cube structure Making programme schematic diagram being applicable to crystal covering type projection fusion techniques.First be make metal bump structure a2 at semiconductor component surfaces a1 metallic contact place.This step normally defines the size and location of metal coupling with exposure imaging technology conventional in manufacture of semiconductor, then forms projection cube structure by metal coating technology.This projection cube structure a2 can be made up of single metal material, the projection cube structure that also can be stacked by multiple layer metal material.Cost due to copper is lower and conductivity is good, and this metal bump structure is normally metal material with copper.Then in copper bump plated surface last layer added metal a3, be generally with the lower tin of fusing point, indium or the alloying metal layer that is main component based on tin or indium, affect element characteristic to avoid element through the processing procedure of too high-temperature.After high-temperature process, added metal layer can start to melt; Then be welded together with pre-designed circuit board again, reach the connection between each component contacts.But as shown in Fig. 2 A to Fig. 2 C, when copper bump size is different, after high-temperature process, the added metal of lug surface can form the island of differing heights because of surface tension, causes difficulty that is follow-up and circuit board fusion process, thus reduces encapsulation dose rate.
In view of this, be the requirement of the crystal covering type projection fusion techniques in response to wafer, a kind of manufacturing method thereof promoting metal lug surface added metal coplanarity must be developed; Especially the manufacturing method thereof that semiconductor wafer surface has the metal coupling of different size is applicable to, and then eliminate or reduce described because of metal coupling vary in size caused added metal after high-temperature process height problem of non-uniform, improve by this downstream test with encapsulation degree of difficulty.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacturing method thereof promoting metal lug surface added metal coplanarity, be applicable to the metal coupling that semiconductor wafer surface has different size, can eliminate or reduce because of metal coupling vary in size caused added metal after high-temperature process height problem of non-uniform.
For reaching above-mentioned purpose, the present invention proposes a kind of method utilizing twice processing procedure, and control metal coupling area and added metal area respectively, improve added metal Coplanarity Problems, its step comprises:
One first processing procedure, in order to make metal bump structure in semiconductor component surfaces; And a second processing procedure, in order to make the added metal structure of this metal lug surface different area; Wherein first fabrication steps comprises: coating or pressing one first photoresist layer are in semiconductor component surfaces; With the position of exposure imaging method definition metal bump structure and geometry; The metal material of metal bump structure is plated with metal film coating method; And remove the first photoresist layer, form metal bump structure; Wherein second fabrication steps comprises: coating or pressing one second photoresist layer are in semiconductor element and metal lug surface; With the position of exposure imaging method definition added metal layer and geometry; The metal material of added metal layer is plated with metal film coating method; And remove the second photoresist layer, form added metal on metal bump structure.
Compared with prior art, the manufacturing method thereof of making metal coupling of the present invention and added metal, when element surface has the metal coupling of different size, can eliminate or reduce because of the added metal that causes of bump size difference problem highly uneven after high-temperature process, improve the degree of difficulty of downstream test and encapsulation by this.
For having a better understanding for feature of the present invention and interaction energy, after hereby mat embodiment coordinates graphic being specified in.
Accompanying drawing explanation
Figure 1A to Fig. 1 C can be applicable to the metal bump structure of crystal covering type projection welding process and the Making programme schematic diagram of added metal.
Fig. 2 A to Fig. 2 C is that the metal bump structure of different size causes surperficial added metal after high-temperature process, produce the schematic diagram of height uneven phenomenon.
Fig. 3 A to Fig. 3 F is the manufacturing method thereof schematic diagram of the surperficial added metal coplanarity of improvement provided by the present invention.
Description of reference numerals: semiconductor component surfaces-1; Semiconductor component surfaces-a1; Metal coupling-2; Metal bump structure-a2; First photoresist layer-30; Added metal-a3; Second photoresist layer-32; Photoresist layer-a4; Added metal-4.
Embodiment
The surface tension that is different by metal coupling area and added metal that is not both of surface added metal height caused; Therefore, utilize fabrication steps to control to plate added metal area and can improve its Coplanarity Problems.Fig. 3 A to Fig. 3 F is the schematic flow sheet showing lifting metal lug surface added metal coplanarity manufacturing method thereof of the present invention.The present invention proposes with twice exposure imaging processing procedure, controls metal coupling area and added metal area respectively, improves added metal Coplanarity Problems.The object of first processing procedure of the present invention is the metal bump structure making different area in semiconductor component surfaces.In first processing procedure, be first coated with or pressing one first photoresist layer 30 in semiconductor component surfaces 1; Again with exposure imaging method, define position and the size of metal coupling 2; Then metal film coating method is utilized to plate the metal material of projection, as shown in Figure 3A.Metal film coating method is different according to different metal material, can be sputter, evaporation or plating.For copper bump structure, this metal coating step can utilize electroless plating method to reach.Finally, after removing the first photoresist layer 30, copper metal bump structure can be formed in semiconductor wafer surface (as shown in Figure 3 B).In order to avoid bump metal surface makes the contact of itself and added metal be deteriorated in successive process because of oxidation, can in first processing procedure, before removal photoresistance, metal film coating method is utilized to plate an added metal layer as soakage layer (wetting layer).This step effectively can promote the wettability of the Contact of bump metal material and added metal.After first processing procedure completes, can second processing procedure be carried out, added metal layer be directly plated on metal bump structure surface or be plated on soakage layer.In this fabrication steps, as shown in Figure 3 C, first coating or pressing one second photoresist layer 32 are in element and metal bump structure surface 1,2, then via exposure imaging method, define size and the position of added metal; Then as shown in Figure 3 D, an added metal layer 4 is plated.Described added metal layer is generally with the lower tin of fusing point, indium or the alloying metal layer that is main component based on tin or indium, affects element characteristic to avoid element through the processing procedure of too high-temperature.Finally, as shown in Fig. 3 E and Fig. 3 F, after removal second photoresist layer 32, the structure of metal coupling 2 and surperficial added metal 4 can be formed.The object of second processing procedure is the cumulative volume controlling added metal, and make it after heat treatment process, the height of added metal can be close.And the area of added metal layer and thickness, then can utilize numerical simulation in advance, consider that added metal aspect is long-pending, thickness and surface tension, calculate the height that added metal is formed after high-temperature digestion.This process is also by experiment, utilize trial and error pricing (try and error), height after the added metal measuring different area and thickness melts, is finally selecting suitable area and thickness according to projection area, can improve added metal Coplanarity Problems.
In sum, the present invention can reach the object of expection really by the twice fabrication steps controlling metal coupling and surperficial added metal area respectively, improves lug surface added metal Coplanarity Problems.The value that its true tool industry utilizes, whence proposes patent application in accordance with the law.
Again above-mentioned explanation and graphic be only that embodiments of the invention are described, all ripe in the personage of this industry skill, still can do equivalence localized variation and modification, its do not depart from technology of the present invention with spirit.
Claims (6)
1. make a manufacturing method thereof for metal coupling and added metal, it is characterized in that, its step comprises:
One first processing procedure, in order to make multiple metal bump structure in semiconductor element surface; And
One second processing procedure, in order to make the added metal structure of the plurality of metal lug surface different area; Wherein,
Described first processing procedure comprises the following step:
Coating or pressing one first photoresist layer are in this semiconductor component surfaces;
With the position of exposure imaging method definition metal bump structure and geometry;
The metal material of metal bump structure is plated with metal film coating method;
The soakage layer of an added metal is plated with metal film coating method;
And
Remove the first photoresist layer, to form metal bump structure;
Described second processing procedure comprises the following step:
Coating or pressing one second photoresist layer are in semiconductor element and metal bump structure surface;
Determine the height that the plurality of added metal structure reaches after high-temperature digestion, the area of added metal structure on each metal coupling is highly determined according to this, and according to the determined area of added metal structure and the position of metal bump structure and geometry, with the position of exposure imaging method definition added metal and geometry;
The metal material of an added metal layer is plated with metal film coating method; And
Remove the second photoresist layer, form added metal on metal bump structure;
Wherein, the metal material of added metal layer be indium, tin, with tin be Main Ingredients and Appearance alloy or take indium as the alloy of Main Ingredients and Appearance.
2. the as claimed in claim 1 manufacturing method thereof making metal coupling and added metal, is characterized in that, the metal film coating method in described first processing procedure and described second processing procedure is sputter, evaporation or plating.
3. the manufacturing method thereof making metal coupling and added metal as claimed in claim 1, it is characterized in that, the metal material of metal bump structure is copper.
4. the manufacturing method thereof making metal coupling and added metal as claimed in claim 1, is characterized in that, the metal material of metal bump structure is gold.
5. the manufacturing method thereof making metal coupling and added metal as claimed in claim 1, it is characterized in that, the height that the plurality of added metal structure reaches after high-temperature digestion is the surface tension of area according to metal coupling and added metal structure, draws with numerical simulation calculation.
6. the manufacturing method thereof making metal coupling and added metal as claimed in claim 1, it is characterized in that, the height that the plurality of added metal structure reaches after high-temperature digestion is by experiment, and utilizes trial and error pricing to draw.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110131307.1A CN102789995B (en) | 2011-05-20 | 2011-05-20 | Method of manufacture procedures for manufacturing metal protrusion and fusion welded metal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110131307.1A CN102789995B (en) | 2011-05-20 | 2011-05-20 | Method of manufacture procedures for manufacturing metal protrusion and fusion welded metal |
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| Publication Number | Publication Date |
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| CN102789995A CN102789995A (en) | 2012-11-21 |
| CN102789995B true CN102789995B (en) | 2015-07-22 |
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| CN201110131307.1A Expired - Fee Related CN102789995B (en) | 2011-05-20 | 2011-05-20 | Method of manufacture procedures for manufacturing metal protrusion and fusion welded metal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110634755A (en) * | 2018-06-22 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109065459A (en) * | 2018-07-27 | 2018-12-21 | 大连德豪光电科技有限公司 | The production method of pad |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6596618B1 (en) * | 2000-12-08 | 2003-07-22 | Altera Corporation | Increased solder-bump height for improved flip-chip bonding and reliability |
| CN101388376A (en) * | 2007-09-14 | 2009-03-18 | 全懋精密科技股份有限公司 | Semi-conductor package substrate construction |
| CN101587872A (en) * | 2008-05-19 | 2009-11-25 | 夏普株式会社 | Semiconductor device, method for mounting semiconductor device and semiconductor device mounting structure |
| CN101754592A (en) * | 2008-11-28 | 2010-06-23 | 欣兴电子股份有限公司 | Method for manufacturing a conductive projection and a circuit board structure with conductive projection |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI302426B (en) * | 2005-04-28 | 2008-10-21 | Phoenix Prec Technology Corp | Conducting bump structure of circuit board and method for fabricating the same |
| JP5512082B2 (en) * | 2007-12-17 | 2014-06-04 | 株式会社東芝 | Semiconductor device manufacturing method and semiconductor device |
| US8503186B2 (en) * | 2009-07-30 | 2013-08-06 | Megica Corporation | System-in packages |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6596618B1 (en) * | 2000-12-08 | 2003-07-22 | Altera Corporation | Increased solder-bump height for improved flip-chip bonding and reliability |
| CN101388376A (en) * | 2007-09-14 | 2009-03-18 | 全懋精密科技股份有限公司 | Semi-conductor package substrate construction |
| CN101587872A (en) * | 2008-05-19 | 2009-11-25 | 夏普株式会社 | Semiconductor device, method for mounting semiconductor device and semiconductor device mounting structure |
| CN101754592A (en) * | 2008-11-28 | 2010-06-23 | 欣兴电子股份有限公司 | Method for manufacturing a conductive projection and a circuit board structure with conductive projection |
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| CN102789995A (en) | 2012-11-21 |
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