CN102789418B - Functional processor realistic model generating apparatus, method and function verification method - Google Patents
Functional processor realistic model generating apparatus, method and function verification method Download PDFInfo
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Abstract
This application discloses a kind of functional processor realistic model generating apparatus, comprise register configuration module, instruction set configuration module, input processing unit generation module, functional simulation unit generation module, simulation result configuration module, simulation result output unit generation module and command function storehouse.The generating apparatus adopting the application to provide can generate the functional simulation meeting copying needs automatically, avoids the possibility that completely manual exploitation causes a large amount of mistake; Meanwhile, the automatic generation method of the application is adopted also greatly to save the development time of functional simulation.
Description
Technical field
The application relates to integrated circuit (IC) design field, is specifically related to a kind of functional simulation of processor instruction level and the function verification method of automatically generating device and a kind of processor thereof.
Background technology
The logic function of processor hardware design and performance index depend on the code quality that hardware designer utilizes hardware description language to write, and usually need first to verify the correctness of this processor before practical application.With the continuous rising of processor complexity, the complexity of processor checking work and workload present index and rise, more and more higher with requirement to the dependence of checking.As a part for design process, checking plays a part more and more crucial, and the workload of checking is also relatively large, and may occupy about 70% of whole design efforts would, the efficiency of checking and reliability often determine the success or failure of project.
The checking of processor mainly comprises the process such as functional verification and timing verification, and the most basic and most popular method is simulating, verifying in functional verification, plays very important effect in the engineering that simulating, verifying is verified at processor.
In order to ensure the correctness of functional processor, usually need to set up a functional simulation, contrast processor is verified with the Output rusults of functional simulation under identical input stimulus.Usually adopt the mode of a manual exploitation functional simulation completely in prior art, this mode is not only a very hard work, and very easily makes mistakes.In general, not only performance history needs the time spending the several months, also requires a great deal of time the checking carrying out functional simulation correctness.
Summary of the invention
The technical problem underlying that the application will solve is, provides a kind of generating apparatus of the functional processor realistic model that can be configured voluntarily according to demand by user.
For solving the problems of the technologies described above, the application provides a kind of generating apparatus of functional processor realistic model, and this functional processor realistic model comprises data structure statement unit, initialization of register unit, input processing unit, functional simulation unit and simulation result output unit;
Data structure statement unit is connected with initialization of register unit, input processing unit, functional simulation unit, simulation result output unit respectively; Data structure statement unit is used for describe register parameters by effective language with computing machine, the title of statement register and data bit width;
Initialization of register unit states unit with data structure respectively, functional simulation unit is connected; Initialization of register unit is used for describe register initial value by effective language with computing machine;
Input processing unit states unit with data structure respectively, functional simulation unit is connected; Input processing unit is for extracting the information in the instruction machine code of input, according to the type of the instruction type field decision instruction of instruction machine code, and the operand information operand map field in instruction machine code is converted in functional simulation device, and the type of instruction and operand information are stored according to the data structure preset;
Functional simulation unit states that unit, initialization of register unit, input processing unit and simulation result output unit are connected respectively with data structure; Functional simulation unit is used for the function according to the instruction determined in described input processing unit, performs the instruction that input processing unit sends, and changes the value of corresponding registers;
With functional simulation unit, data structure, simulation result output unit states that unit is connected respectively; Simulation result output unit is used for the value of the register of functional simulation cell processing to export according to simulation result output format;
This generating apparatus comprises register configuration module, instruction set configuration module, input processing unit generation module, functional simulation unit generation module, simulation result configuration module, simulation result output unit generation module and command function storehouse;
Register configuration module: and instruction collection configuration module, functional simulation unit generation module and simulation result configuration module connect respectively, for receiving the register parameters of user's input, described register parameters comprises the title of register number and each register, data bit width and reset values, and generates data structure according to the number of register, title and data bit width and state unit; Reset values according to register generates initialization of register unit;
Instruction set configuration module: be connected with register configuration module, input processing unit generation module, functional simulation unit generation module respectively, for receiving the instruction set configuration information of user's input, instruction set configuration information comprises instruction machine code and command function information, and described instruction machine code comprises map field and the operand map field of instruction type; Also for matching the command function of this instruction in command function storehouse according to instruction type;
Input processing unit generation module: and instruction collection configuration module is connected, for the machine code information in the instruction set configuration information that receives according to instruction set configuration module, generates input processing unit;
Functional simulation unit generation module: and instruction collection configuration module, register configuration module are connected respectively, for the function information systematic function simulation unit in the instruction set configuration information that receives according to instruction set configuration module;
Simulation result configuration module: be connected with register configuration module, simulation result output unit generation module respectively, for receiving the simulation result output format of user's input;
Simulation result output unit generation module: the simulation result output format for receiving according to described simulation result configuration module generates simulation result output unit;
Command function storehouse: and instruction collection configuration module, functional simulation unit generation module are connected respectively, for the command function information in the instruction set configuration information that store sets of instructions configuration module receives; Described functional simulation unit generation module is also according to the function information systematic function simulation unit of command function library storage.
Further, the input processing unit of described functional processor realistic model comprises:
Instruction type judgment sub-unit: and instruction operand information process subelement is connected, for the information decision instruction type according to presentation directives's type in instruction machine code;
Instruction operand information process subelement: for the information of presentation directives's operand in instruction machine code being converted to the data structure stated in described data structure statement unit and preserving;
The input processing unit generation module of described generating apparatus comprises:
Instruction type judgment sub-unit generation module: for generating described instruction type judgment sub-unit according to the information of presentation directives's type in machine code information;
Instruction operand information process subelement generation module: for the information according to presentation directives's operand in machine code information, generates described instruction operand information process subelement.
Further, described instruction operand information comprises: operand number and operand array.
Further, described operand array comprises operand type and operand value.
Meanwhile, present invention also provides a kind of generation method of functional processor realistic model, it comprises the following steps:
Configuration register information: the register parameters receiving user's input, described register parameters comprises the title of register number and each register, data bit width and reset values; Generate data structure according to the number of register, title and data bit width and state unit, reset values according to register generates initialization of register unit, data structure statement unit is used for describe register parameters by effective language with computing machine, the title of statement register and data bit width, initialization of register unit is used for describe register initial value by effective language with computing machine;
Configuration-direct collection information: the instruction set configuration information receiving user's input, instruction set configuration information comprises instruction machine code and command function information, and described instruction machine code comprises map field and the operand map field of instruction type; In command function storehouse, the command function of this instruction is matched according to instruction type;
Machine code input processing unit is generated according to instruction machine code, described machine code input processing unit is for extracting the information in the instruction machine code of input, according to the type of the instruction type field decision instruction of instruction machine code, and the operand information operand map field in instruction machine code is converted in functional simulation device, and the type of instruction and operand information are stored according to the data structure preset;
According to command function systematic function simulation unit, described functional simulation unit is used for according to command function, performs the instruction that machine code input processing unit sends, and changes the value of corresponding registers;
Configuration Output rusults: the simulation result output format according to user's input generates simulation result output unit, described simulation result output unit is used for the value of the register of functional simulation cell processing to export according to simulation result output format.
Present invention also provides a kind of processor function verification method, utilize realistic model to carry out functional verification to CPU design, described method comprises:
According to the generation method of above-mentioned functional processor realistic model, receive the register parameters of the processor to be verified of user's input, instruction set information and simulation result output format information, use the generating apparatus of above-mentioned functional processor realistic model, automatically generate above-mentioned processor instruction level functional simulation;
Allow this functional simulation and processor to be verified run one section of identical instruction, after more every bar instruction executes, whether the value of each register that this functional simulation is corresponding with processor to be verified is identical; If the value of all registers is all identical, then think that processor to be verified does not have mistake when performing this section of instruction; Otherwise, then thinking that process to be verified there will be mistake when performing this section of code, needing to treat validation processor and modifying;
Repeating aforesaid operations, ensureing that processor to be verified all can not be made mistakes when performing a lot of code segment, by analyzing the coverage rate of processor to be verified in simulating, verifying process, using the coverage rate of process to be verified as verifying the index whether passed through.
The beneficial effect of the application is: the generating apparatus adopting the application to provide can generate the functional simulation meeting copying needs automatically, avoids the possibility that completely manual exploitation causes a large amount of mistake; Meanwhile, the automatic generation method of the application is adopted also greatly to save the development time of functional simulation.
Accompanying drawing explanation
A kind of functional processor realistic model structural representation that Fig. 1 provides for embodiment;
A kind of structural representation of the input processing unit that Fig. 2 provides for embodiment;
Fig. 3 is that embodiment is held instruction a kind of data structure schematic diagram of information;
The generating apparatus structural representation of the functional processor realistic model that Fig. 4 provides for embodiment;
A kind of structural representation of the input processing unit generation module that Fig. 5 provides for embodiment;
The generation method flow diagram of the functional processor realistic model that Fig. 6 provides for embodiment;
The workflow diagram of the functional processor realistic model that Fig. 7 provides for embodiment.
Embodiment
By reference to the accompanying drawings the application is described in further detail below by embodiment.
The present embodiment first introduces a kind of functional processor realistic model, secondly introduces the generating apparatus generating this functional simulation.(in the application, functional processor realistic model is also called for short functional simulation.)
Refer to Fig. 1, this functional processor realistic model mainly comprises data structure statement unit 10, initialization of register unit 20, input processing unit 30, functional simulation unit 40 and simulation result output unit 50.
Data structure statement unit 10: be connected with initialization of register unit 20, input processing unit 30, functional simulation unit 40, simulation result output unit 50 respectively; For register parameters can be described by effective language with computing machine, the title of statement register and data bit width.
The register (with variable format) that data structure statement unit 10 is stated is for following initialization of register unit 20, functional simulation unit 40 and simulation result output unit 50, and the data structure of the information of holding instruction of statement is for following input processing unit 30 and functional simulation unit 40.
Initialization of register unit 20: state unit with data structure respectively, functional simulation unit is connected; For register initial value can be described by effective language with computing machine, be then supplied to following input processing unit 30 and use.
Above-mentioned data structure states that the register configuration information mentioned in unit 10 and initialization of register unit 20 can be obtained according to the register information of processor to be verified by user.Data structure statement unit 10 is only for stating.Such as: suppose there are two registers, title is configured to r0 and r1 respectively, the data bit width of r0 is configured to 32, the data bit width of r1 is configured to 16, the initial value of two registers is all configured to zero, can c program in effective language for computing machine, first following statement can be carried out in c program:
int r0；short r1；
In the operational process that functional simulation is follow-up, initialization of register unit 20 can utilize above-mentioned configuration initial value of zero to carry out initialization (reset) to register.
Input processing unit 30: state unit 10 with data structure respectively, functional simulation unit 40 is connected; For extracting the information in the instruction machine code of input, according to the type of the instruction type field decision instruction of instruction machine code, and the operand information operand map field in instruction machine code is converted in functional simulation device, and the type of instruction and operand information are stored according to the data structure preset.
" instruction machine code " mentioned in above-mentioned input processing unit 30 derives from user's input.
Refer to Fig. 2, for more specifically describing the application of input processing unit 30, input processing unit 30 is subdivided into following subelement by the present embodiment:
Instruction type judgment sub-unit 31: and instruction operand information process subelement 32 is connected, for the information decision instruction type according to presentation directives's type in instruction machine code, and the information of instruction type is supplied to following instruction operand information process subelement 32.
Instruction operand information process subelement 32: for the information of presentation directives's operand in instruction machine code being converted to the data structure of statement in described data structure statement unit 10 and preserving.
Suppose (pre-configured complete) in certain instruction set, instruction ADD R7, the machine code of R8 is 1000_0000_0111_1000, wherein, the intrinsic machine code that most-significant byte " 1000_0000 " in 16 machine codes is presentation directives's type information, i.e. the most-significant byte machine code of all ADD instructions (operand of ADD instruction in this instruction set is two general-purpose registers) is all 1000_0000.The part that least-significant byte machine code " 0111_1000 " is presentation directives's operand information, high 4 " 0111 " wherein represent that the value of first operand is 7, and namely first operand is R7 (the 7th general-purpose register); Low 4 " 1000 " wherein represent that the value of second operand is 8, and namely second operand is R8 (the 8th general-purpose register).
Therefore, if the machine code of user's input is " 1000_0000_0111_1000 ", first most-significant byte is extracted by instruction type judgment sub-unit 31, obtain 1000_0000, can determine that the type of this instruction is ADD, then least-significant byte is extracted by operand information process subelement 32, obtain 0111_1000, can determine that the operand of this instruction is R7, R8, finally by conversion preservation subelement 33, this command information is converted to data structure state the data structure of statement in unit 10 and preserve, so far just completes the work for the treatment of of input instruction machine code.
Refer to Fig. 3, the data structure of the information of holding instruction in the present embodiment comprises instruction type and operand information.And operand information comprises the number of operand and the information of each operand and operand array.Each element in operand array comprises again the type of this operand and the occurrence of this operand.Fig. 3 is to preserve following command information: ST R5, R6, and 1, namely instruction type is ST, and this instruction comprises 3 operands: the type of first operand is R (i.e. general-purpose register), and value is 5 (i.e. the 5th general-purpose registers); The type of second operand is R (i.e. general-purpose register), and value is 6 (i.e. the 6th general-purpose registers); The type of the 3rd operand is I (i.e. immediate), and value is 1.
Functional simulation unit 40: state that unit 10, initialization of register unit 20, input processing unit 30 and simulation result output unit 50 are connected respectively with data structure; For the function according to the instruction determined in input processing unit 30, perform the instruction that input processing unit sends, change the value of corresponding registers.This simulation process and result use register according to register number, title and the data bit width stated in data structure statement unit 10, meanwhile, use the initialization value of initialization of register unit 20 pairs of registers.
Simulation result output unit 50: state that unit 10 is connected with functional simulation unit 30, data structure respectively; Value for the register processed by functional simulation unit 40 exports according to simulation result output format.Here " certain format " said refers to by the formatted output such as scale-of-eight, sexadecimal, and can only export the simulation result of some register as required as required.The output of this simulation result uses register according to register number, title and the data bit width stated in data structure statement unit 10.
Below introduce the generating apparatus of above-mentioned functional processor realistic model.
Refer to Fig. 4, this generating apparatus mainly comprises: register configuration module 100, instruction set configuration module 200, input processing unit generation module 300, functional simulation unit generation module 400, simulation result configuration module 500, simulation result output unit generation module 600 and command function storehouse 700.
Register configuration module 100: and instruction collection configuration module 200, functional simulation unit generation module 400 and simulation result configuration module 500 connect respectively, for receiving register parameter, register parameters comprises the title of register number and each register, data bit width and reset values, and generates above-mentioned data structure according to the number of register, title and data bit width and state unit 10; Above-mentioned initialization of register unit 20 is generated according to the reset values of register.
Such as, user configures as follows: configure 16 general-purpose registers, name is called R0, R1 ... R14, R15, each general purpose register data bit wide is 16, and initial value is 0x0000; Configure 1 control register, name is called PC, and data bit width is 16, and initial value is 0x0800.According to above-mentioned configuration, register configuration module 100 can statement 17 bit wides be integer variable R0, the R1 of 16 in the data structure statement unit 10 of above-mentioned functions realistic model ... R14, R15 and PC; And by R0, R1 in the initialization of register unit 20 of above-mentioned functions realistic model ... the initial value assignment of R14, R15 is 0x0000, is 0x0800 by the initial value assignment of PC.
Instruction set configuration module 200: be connected with register configuration module 100, input processing unit generation module 300, functional simulation unit generation module 400 respectively, for receiving the instruction set configuration information of user's input, instruction set configuration information comprises instruction machine code information and command function information, and this instruction machine code comprises map field and the operand map field of instruction type; Also for matching the command function of this instruction in command function storehouse according to instruction type.
Such as, instruction set is configured as follows: suppose the following two class instructions now needing configuration-direct to concentrate: MOVL, ADD.First for ADD instruction, first configure the information of presentation directives's type in ADD instruction machine code, the most-significant byte of machine code is fixed as 1000_0000.Then configure the information representing operand in ADD instruction machine code, the operand type of such instruction is all configured to general-purpose register.The value of high 4 bit representations first operand in machine code least-significant byte, even these 4 is 0111, then represent that first operand is R7 (the 7th general-purpose register; Notice that R0 is the 0th general-purpose register, therefore R7 is the 7th general-purpose register); The value of low 4 bit representations second operand in machine code least-significant byte, if these 4 is 1000, then represents that second operand is R8 (the 8th general-purpose register).The machine code information of above-mentioned instruction set will be supplied to input processing unit generation module 300.
The process of configuration-direct function, can describe the function of this instruction with programming language, and add in command function storehouse 700 by this function, during use, query statement function storehouse 700 is called.
Command function storehouse 700: and instruction collection configuration module 200, functional simulation unit generation module 400 are connected respectively, for the function information in the instruction set configuration information that store sets of instructions configuration module 200 receives.
The process of query statement function storehouse 700 configuration-direct function comprises: the function whether comprising ADD instruction in query statement function storehouse 700, suppose that the function of ADD instruction is not included in this command function storehouse 700, then the programming language of regulation can be utilized to describe the function of such instruction and add in command function storehouse 700.The function of ADD instruction is now described by C language:
op1＝op1+op2；
pc＝pc+2；
Wherein, op1 represents first operand, and op2 represents second operand, pc representation program counter.Above-mentioned functions being described adds in command function storehouse 700, and then whether the function of inquiry ADD instruction is included in command function storehouse 700, the function of now ADD instruction in command function storehouse 700, so only need the function configuring this instruction according to command function storehouse 700.This completes the configuration of ADD instruction.The function information of above-mentioned instruction set will be supplied to functional simulation unit generation module 400, and be added in command function storehouse 700 by user-defined ADD command function.
And for example, in above-mentioned instruction set layoutprocedure, the function of MOVL instruction is existing in command function storehouse 700 to be illustrated, then only the function of MOVL need be appointed as corresponding function in command function storehouse 700 and illustrate.
Input processing unit generation module 300: and instruction collection configuration module 200 is connected, for the machine code information in the instruction set configuration information that receives according to instruction set configuration module 200, generates above-mentioned input processing unit 30.
Refer to Fig. 5, for better describing the course of work of above-mentioned input processing unit generation module 300, input processing unit generation module 300 is subdivided into by the present embodiment:
Instruction type judgment sub-unit generation module 310: for generating above-mentioned instruction type judgment sub-unit 31 according to the information of presentation directives's type in machine code information.
Instruction operand information process subelement generation module 320: for the information according to presentation directives's operand in machine code information, generates above-mentioned instruction operand information process subelement 32.
Such as, in above-mentioned instruction set, the machine code most-significant byte of ADD instruction is fixed as 1000_0000 (the machine code most-significant byte of the another kind of command M OVL in this instruction set can not be 1000_0000), then machine code most-significant byte is that the instruction of 1000_0000 is ADD instruction, and instruction type judgment sub-unit generation module 31 is taken this as a foundation and automatically generated above-mentioned instruction type judgment sub-unit 31.The value of high 4 bit representations first operand in the machine code least-significant byte of ADD instruction, even these 4 is 0111, then represent that first operand is R7; The value of low 4 bit representations second operand in machine code least-significant byte, if these 4 is 1000, then represents that second operand is R8.According to above-mentioned information, instruction operand information process subelement generation module 320 can generate above-mentioned instruction operand information process subelement 32.
Functional simulation unit generation module 400: respectively and instruction collection configuration module 200, register configuration module 100 are connected, for function information (function information in command function storehouse 700) the systematic function simulation unit 40 in the instruction set configuration information that receives according to instruction set configuration module 200.
Such as, the function of above-mentioned ADD instruction is selected in command function storehouse 700, then the computer programming language be described this command function in command function storehouse 700, as main body, generates the ADD command function simulated function in above-mentioned functions simulation unit automatically.
Simulation result configuration module 500: be connected with register configuration module 100, simulation result output unit generation module 600 respectively, for receiving the simulation result configuration information of user's input.
Such as, simulation result output format is configured as follows: if be only concerned about the value of 16 general-purpose registers, then only need output format to be configured to the value exporting 16 general-purpose registers after every bar instruction executes by 16 systems, and this information is supplied to simulation result output unit generation module 600.
Simulation result output unit generation module 600: be connected with simulation result configuration module, the simulation result output format for receiving according to simulation result configuration module 500 generates above-mentioned simulation result output unit 50.
Below introduce the generation method of above-mentioned processor simulation functional mode, please refer to Fig. 6, comprise the following steps:
S100, configuration register information: the register parameters receiving user's input, this register parameters comprises the title of register number and each register, data bit width and reset values.Generate data structure according to the number of register, title and data bit width and state unit 10, the reset values according to register generates initialization of register unit 20.
S200, configuration-direct collection information: the instruction set configuration information receiving user's input, instruction set configuration information comprises instruction machine code, and this instruction machine code comprises map field and the operand map field of instruction type; In command function storehouse, the command function of this instruction is matched according to instruction type; Machine code input processing unit 30 is generated according to instruction machine code; According to command function systematic function simulation unit 40.
Input processing unit 30 is subdivided into following subelement by the present embodiment:
Instruction type judgment sub-unit 31: and instruction operand information process subelement 32 is connected, for the information decision instruction type according to presentation directives's type in instruction machine code, and the information of instruction type is supplied to following instruction operand information process subelement 32.
Instruction operand information process subelement 32: for the information of presentation directives's operand in instruction machine code being converted to the data structure of statement in described data structure statement unit 10 and preserving.
The step of input processing unit 30 is generated according to instruction machine code, be specially: first generate above-mentioned instruction type judgment sub-unit 31 according to the information of presentation directives's type in machine code information, again according to the information of presentation directives's operand in machine code information, generate above-mentioned instruction operand information process subelement 32.
Namely the function of the title of every bar instruction, machine code and every bar instruction is configured; And generate input processing unit 30, according to configuration-direct title and function systematic function simulation unit 40 according to the instruction name configured and machine code.
S300, configuration Output rusults, the simulation result output format according to user's input generates simulation result output unit 50.
For better describing the process of configuration register information in step S100, be subdivided into following steps:
S110: the number of configuration register and the title of each register, as the data structure statement unit statement number of register and the foundation of name variable.
S120: the data bit width configuring each register, as the foundation of data structure statement unit statement register data bit wide.
S130: configuration register reset values, as the foundation of initialization of register unit initialization register.
For better describing the process of configuration-direct collection in step S200, be subdivided into following steps:
S210: configuration-direct title, as the foundation of input processing unit 30, functional simulation unit 40 recognition instruction; General employing memonic symbol, as MOV, ADD etc.
S220: the information of presentation directives's type in configuration-direct machine code, as the foundation of input processing unit 30 (instruction type judgment sub-unit 31) decision instruction type.
S230: the information representing operand in configuration-direct machine code, extracts the foundation of operand information in command information as input processing unit 30 (instruction operand information process subelement), when operand is different, machine code makes corresponding change.
S260: the function of configuration-direct, carries out the foundation of functional simulation as functional simulation unit.
The function configuring every bar instruction comprises: the function according to this instruction in command function storehouse is configured.
Configure in above-mentioned steps S260 the function of every bar instruction before can first query statement function storehouse, that is:
S240: the function whether comprising this instruction in query statement function storehouse; If so, the function of this instruction is then configured according to command function storehouse; If not, then perform:
S250: describe the function of this instruction with programming language and added in command function storehouse.
When user needs to verify the design of processor, checking flow process is as follows:
According to the generation method of described functional processor realistic model, receive the register parameters of the processor to be verified of user's input, instruction set information and simulation result output format information, use the generating apparatus of described functional processor realistic model, automatically generate described processor instruction level functional simulation;
Allow this functional simulation and processor to be verified run one section of identical instruction, after more every bar instruction executes, whether the value of each register that this functional simulation is corresponding with processor to be verified is identical; If the value of all registers is all identical, then think that processor to be verified does not have mistake when performing this section of instruction; Otherwise, then thinking that process to be verified there will be mistake when performing this section of code, needing to treat validation processor and modifying;
Repeating aforesaid operations, ensureing that processor to be verified all can not be made mistakes when performing a lot of code segment, by analyzing the coverage rate of processor to be verified in simulating, verifying process, using the coverage rate of process to be verified as verifying the index whether passed through.
Fig. 7 is the process flow diagram of a working example of functional processor realistic model, mainly comprises:
1, first by initialization of register unit 20 initialization register, namely initialization is carried out according to the register of reset values to statement of register.
2, then whether decision instruction executes, if execute, then emulates end; If do not execute, then continue following operation:
3, by input processing unit 30 reading command from virtual memory, and process the instruction machine code of user's input, command information is saved in the data structure described in Fig. 3.Specifically comprise: extract the information in instruction machine code, according to the type of the instruction type field decision instruction of instruction machine code, and the operand information operand map field in instruction machine code be converted in functional simulation device, and instruction is stored as default data structure according to type and operand information.
4, complete the functional simulation of this instruction by function simulation unit 40, namely according to command function, perform instruction, change the value of corresponding registers.
5, by simulation result output unit 50 Output simulation result, be generally and export the value of each register after executing this instruction.
Such as, if certain processor functional simulation performs following instruction machine code:
0010010001000100
0011010001000000
0010001001100110
0011001010100000
1000000001000010
Corresponding following instruction:
MOVL R4,0x44
MOVH R4,0x40
MOVL R2,0x66
MOVH R2,0xa0
ADD R4,R2
First, according to the register configuration information of this functional processor realistic model, the initialization of each register is completed by initialization of register unit 20.(as in this functional processor realistic model, the register except programmable counter PC is all initialized as 0.)
Secondly, by the command memory of above-mentioned 5 instructions all stored in functional processor realistic model, namely stored in piece virtual store of in functional simulation (if this functional simulation C language realizes, being namely claimed as the integer array of 16bits).
Then, judge whether to perform 5 instructions, if performed 5 instructions, then emulate end.If also do not execute 5 instructions, then first being processed the instruction machine code of input by input processing unit 30, as just started to perform Article 1 instruction now, first processing the machine code of this instruction, it can thus be appreciated that Article 1 instruction is MOVL R4,0x44;
Again, complete emulation by functional simulation unit 40 according to the function of command M OVL R4,0x44, by 0x44 assignment to the least-significant byte of R4, in addition do not affect other register.
Finally, the simulation result of this instruction is exported by simulation result output unit 50.Suppose that output format is the value exporting 16 general-purpose registers by 16 systems, then the simulation result exported is: 0x00000x0000 0x0000 0x0000 0x0044 0x0000 0x0000 0x0000 0x0000 0x00000x0000 0x0000 0x0000 0x0000 0x0000 0x0000.
Suppose that output format is set to export by 16 systems after every bar instruction executes the value of 16 general-purpose registers, following result can be obtained:
0x0000 0x0000 0x0000 0x0000 0x0044 0x0000 0x0000 0x0000 0x00000x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
0x0000 0x0000 0x0000 0x0000 0x4044 0x0000 0x0000 0x0000 0x00000x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
0x0000 0x0000 0x0066 0x0000 0x4044 0x0000 0x0000 0x0000 0x00000x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
0x0000 0x0000 0xa066 0x0000 0x4044 0x0000 0x0000 0x0000 0x00000x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
0x0000 0x0000 0xa066 0x0000 0xe0aa 0x0000 0x0000 0x0000 0x00000x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
Above content is the further description done the application in conjunction with concrete embodiment, can not assert that the concrete enforcement of the application is confined to these explanations.For the application person of an ordinary skill in the technical field, under the prerequisite not departing from the application's design, some simple deduction or replace can also be made, all should be considered as the protection domain belonging to the application.
Claims (6)
1. a generating apparatus for functional processor realistic model, is characterized in that, this functional processor realistic model comprises data structure statement unit, initialization of register unit, input processing unit, functional simulation unit and simulation result output unit;
Data structure statement unit is connected with initialization of register unit, input processing unit, functional simulation unit, simulation result output unit respectively; Data structure statement unit is used for describe register parameters by effective language with computing machine, the title of statement register and data bit width;
Initialization of register unit states unit with data structure respectively, functional simulation unit is connected; Initialization of register unit is used for describe register initial value by effective language with computing machine;
Input processing unit states unit with data structure respectively, functional simulation unit is connected; Input processing unit is for extracting the information in the instruction machine code of input, according to the type of the instruction type field decision instruction of instruction machine code, and the operand information operand map field in instruction machine code is converted in functional simulation device, and the type of instruction and operand information are stored according to the data structure preset;
Functional simulation unit states that unit, initialization of register unit, input processing unit and simulation result output unit are connected respectively with data structure; Functional simulation unit is used for the function according to the instruction determined in described input processing unit, performs the instruction that input processing unit sends, and changes the value of corresponding registers;
With functional simulation unit, data structure, simulation result output unit states that unit is connected respectively; Simulation result output unit is used for the value of the register of functional simulation cell processing to export according to simulation result output format;
This generating apparatus comprises register configuration module, instruction set configuration module, input processing unit generation module, functional simulation unit generation module, simulation result configuration module and simulation result output unit generation module and command function storehouse;
Register configuration module: and instruction collection configuration module, functional simulation unit generation module and simulation result configuration module connect respectively, for receiving the register parameters of user's input, described register parameters comprises the title of register number and each register, data bit width and reset values, and generates data structure according to the number of register, title and data bit width and state unit; Reset values according to register generates initialization of register unit;
Instruction set configuration module: be connected with register configuration module, input processing unit generation module, functional simulation unit generation module respectively, for receiving the instruction set configuration information of user's input, instruction set configuration information comprises instruction machine code and command function information, and described instruction machine code comprises map field and the operand map field of instruction type; Also for matching the command function of this instruction in command function storehouse according to instruction type;
Input processing unit generation module: and instruction collection configuration module is connected, for the machine code information in the instruction set configuration information that receives according to instruction set configuration module, generates input processing unit;
Functional simulation unit generation module: and instruction collection configuration module, register configuration module are connected respectively, for the function information systematic function simulation unit in the instruction set configuration information that receives according to instruction set configuration module;
Simulation result configuration module: be connected with register configuration module, simulation result output unit generation module respectively, for receiving the simulation result output format of user's input;
Simulation result output unit generation module: the simulation result output format for receiving according to described simulation result configuration module generates simulation result output unit;
Command function storehouse: and instruction collection configuration module, functional simulation unit generation module are connected respectively, for the command function information in the instruction set configuration information that store sets of instructions configuration module receives.
2. generating apparatus as claimed in claim 1, it is characterized in that, the input processing unit of described functional processor realistic model comprises:
Instruction type judgment sub-unit: and instruction operand information process subelement is connected, for the information decision instruction type according to presentation directives's type in instruction machine code;
Instruction operand information process subelement: for the information of presentation directives's operand in instruction machine code being converted to the data structure stated in described data structure statement unit and preserving;
The input processing unit generation module of described generating apparatus comprises:
Instruction type judgment sub-unit generation module: for generating described instruction type judgment sub-unit according to the information of presentation directives's type in machine code information;
Instruction operand information process subelement generation module: for the information according to presentation directives's operand in machine code information, generates described instruction operand information process subelement.
3. generating apparatus as claimed in claim 2, it is characterized in that, described instruction operand information comprises: operand number and operand array.
4. generating apparatus as claimed in claim 3, it is characterized in that, described operand array comprises operand type and operand value.
5. a generation method for functional processor realistic model, is characterized in that, comprise the following steps:
Configuration register information: the register parameters receiving user's input, described register parameters comprises the title of register number and each register, data bit width and reset values; Generate data structure according to the number of register, title and data bit width and state unit, reset values according to register generates initialization of register unit, data structure statement unit is used for describe register parameters by effective language with computing machine, the title of statement register and data bit width, initialization of register unit is used for describe register initial value by effective language with computing machine;
Configuration-direct collection information: the instruction set configuration information receiving user's input, instruction set configuration information comprises instruction machine code and command function information, and described instruction machine code comprises map field and the operand map field of instruction type; In command function storehouse, the command function of this instruction is matched according to instruction type;
Input processing unit is generated according to instruction machine code, described input processing unit is for extracting the information in the instruction machine code of input, according to the type of the instruction type field decision instruction of instruction machine code, and the operand information operand map field in instruction machine code is converted in functional simulation device, and the type of instruction and operand information are stored according to the data structure preset;
According to command function systematic function simulation unit, described functional simulation unit is used for according to command function, performs the instruction that input processing unit sends, and changes the value of corresponding registers;
Configuration Output rusults: the simulation result output format according to user's input generates simulation result output unit, described simulation result output unit is used for the value of the register of functional simulation cell processing to export according to simulation result output format.
6. a processor function verification method, utilize realistic model to carry out functional verification to CPU design, it is characterized in that, described method comprises:
The generation method of functional processor realistic model according to claim 5, receive the register parameters of the processor to be verified of user's input, instruction set information and simulation result output format information, use the generating apparatus of the arbitrary described functional processor realistic model of Claims 1-4, automatic generating process device functional simulation;
Allow this functional simulation and processor to be verified run one section of identical instruction, after more every bar instruction executes, whether the value of each register that this functional simulation is corresponding with processor to be verified is identical; If the value of all registers is all identical, then think that processor to be verified does not have mistake when performing this section of instruction; Otherwise, then thinking that process to be verified there will be mistake when performing this section of instruction, needing to treat validation processor and modifying.
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| CN110597554A (en) * | 2019-08-01 | 2019-12-20 | 浙江大学 | Automatic generation optimization method for instruction function of instruction set simulator |
| CN111985179A (en) * | 2020-08-26 | 2020-11-24 | 上海磐启微电子有限公司 | Design verification system and method for wireless communication chip |
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