CN102789256B - Low pressure difference linear voltage regulator - Google Patents
Low pressure difference linear voltage regulator Download PDFInfo
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- CN102789256B CN102789256B CN201210312751.8A CN201210312751A CN102789256B CN 102789256 B CN102789256 B CN 102789256B CN 201210312751 A CN201210312751 A CN 201210312751A CN 102789256 B CN102789256 B CN 102789256B
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Abstract
A kind of low pressure difference linear voltage regulator comprises: error amplifier, impact damper, the first bypass N-type MOS transistor, the first resistor, the second resistor, resistors in series, series capacitor and voltage conversioning rate promote circuit.The output terminal of error amplifier is connected to the input end of impact damper BF, and the output terminal of impact damper BF is connected to the grid of the first bypass N-type MOS transistor, and the drain electrode of the first bypass N-type MOS transistor is as the output terminal of low pressure difference linear voltage regulator.Voltage conversioning rate promotes circuit and comprises: the second bypass N-type MOS transistor, the first additional nmos pass transistor, the second additional PMOS transistor, the 3rd additional PMOS transistor, the 3rd additional nmos pass transistor, the second additional nmos pass transistor and the second current source.Effectively can improve voltage conversioning rate according to low pressure difference linear voltage regulator of the present invention and not increase power consumption, thus, low pressure difference linear voltage regulator according to the present invention is particularly useful for the application of the requirement fast current load response of low-power consumption.
Description
Technical field
The present invention relates to semiconductor circuit design field, more particularly, the present invention relates to a kind of low pressure difference linear voltage regulator.
Background technology
Low pressure difference linear voltage regulator LDO (lowdropoutregulator) is relative to a kind of power conversion chip traditional linear voltage regulator.Traditional linear voltage regulator all requires that input voltage wants specific output voltage to exceed 2v ~ more than 3V, otherwise with regard to cisco unity malfunction.But in some cases, cannot meet input voltage and want specific output voltage to exceed the such requirement of 2v ~ more than 3V, the input of such as 5v turns the situation of the output of 3.3v, and the pressure reduction of constrained input only has 1.7v, does not obviously satisfy condition.For this situation, propose the power conversion chip of low pressure difference linear voltage regulator LDO class.
Fig. 1 schematically shows the block diagram of the low pressure difference linear voltage regulator according to prior art.
As shown in Figure 1, comprise according to the low pressure difference linear voltage regulator of prior art: error amplifier EA, impact damper BF, the first bypass N-type MOS transistor Mp1, the first resistor R1, the second resistor R2, resistors in series ESR and series capacitor CL.
Wherein, the output terminal of described error amplifier EA is connected to the input end of described impact damper BF, the output terminal of described impact damper BF is connected to the grid of described first bypass N-type MOS transistor Mp1, the source electrode of described first bypass N-type MOS transistor Mp1 is connected to supply voltage, the drain electrode of described first bypass N-type MOS transistor Mp1 is as the output terminal VOUT of described low pressure difference linear voltage regulator, and the drain electrode of described first bypass N-type MOS transistor Mp1 is connected to the first end of described first resistor R1 and is connected to the first end of described resistors in series ESR, second end of described first resistor R1 is connected to the first end of described second resistor R2 and is connected to the input end of described error amplifier EA, second end of described resistors in series ESR is connected to the first end of described series capacitor CL, second end of described second resistor R2 and the equal ground connection of the second end of the second resistor R2.
Wherein, described error amplifier EA comprises: the first current source A1, the first PMOS transistor M1, the second PMOS transistor M2, the 3rd nmos pass transistor M3 and the 4th nmos pass transistor M4.Wherein, the output terminal of described first current source A1 is connected to the source electrode of described first PMOS transistor M1 and the source electrode of described second PMOS transistor M2, the grid of described first PMOS transistor M1 is as the input end of described error amplifier EA, the grid input reference voltage VREF of described second PMOS transistor M2, the drain electrode of described first PMOS transistor M1 is connected to the source electrode of described 3rd nmos pass transistor M3, the drain electrode of described second PMOS transistor M2 is connected to the source electrode of described 4th nmos pass transistor M4, the grid being connected to described 3rd nmos pass transistor M3 of described first PMOS transistor M1 and the grid of described 4th nmos pass transistor M4.The source electrode of described 3rd nmos pass transistor M3 and the source ground of described 4th nmos pass transistor M4.
For traditional low pressure difference linear voltage regulator, due to power consumption, the voltage conversioning rate of impact damper BF is not high.According to for traditional low pressure difference linear voltage regulator, if larger voltage conversioning rate will be realized, the electric current of impact damper must be increased, thus cause larger power consumption.Wherein voltage conversioning rate (SlewRate is abbreviated as SR) is called for short slew rate, and its definition is the amplitude that voltage raises in 1 microsecond or 1 nanosecond equal time, is in other words that square-wave voltage is raised to crest required time by trough.
And, along with the requirement of the higher voltage conversioning rate to low pressure difference linear voltage regulator, expect to provide a kind of low pressure difference linear voltage regulator improving voltage conversioning rate when not increasing power consumption.
Summary of the invention
Technical matters to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of low pressure difference linear voltage regulator that can improve voltage conversioning rate when not increasing power consumption.
In order to realize above-mentioned technical purpose, the present invention proposes a kind of low pressure difference linear voltage regulator, and it comprises: error amplifier, impact damper, the first bypass N-type MOS transistor, the first resistor, the second resistor, resistors in series, series capacitor and voltage conversioning rate promote circuit, wherein, the output terminal of described error amplifier is connected to the input end of described impact damper, the output terminal of described impact damper is connected to the grid of described first bypass N-type MOS transistor, the source electrode of described first bypass N-type MOS transistor is connected to supply voltage, the drain electrode of described first bypass N-type MOS transistor is as the output terminal of described low pressure difference linear voltage regulator, and the drain electrode of described first bypass N-type MOS transistor is connected to the first end of described first resistor and is connected to the first end of described resistors in series, second end of described first resistor is connected to the first end of described second resistor and is connected to an input end of described error amplifier, another input termination reference voltage of error amplifier, second end of described resistors in series is connected to the first end of described series capacitor, second end of described second resistor and the equal ground connection of the second end of described series capacitor, wherein, described voltage conversioning rate lifting circuit comprises: the second bypass N-type MOS transistor, the first additional nmos pass transistor, the second additional nmos pass transistor, the 3rd additional PMOS transistor, the 3rd additional nmos pass transistor and the second current source, wherein, the source electrode of described second bypass N-type MOS transistor and the drain source electrode that is connected respectively to described first bypass N-type MOS transistor and drain electrode, the grid of the described first additional nmos pass transistor is connected to the output terminal of described error amplifier, the source electrode of the described 3rd additional PMOS transistor and grid are connected respectively source electrode to described second bypass N-type MOS transistor and grid, the drain electrode of the described 3rd additional PMOS transistor is connected to the drain electrode of the described 3rd additional nmos pass transistor, and the grid of the described 3rd additional PMOS transistor connects its drain electrode, the grid of the described 3rd additional nmos pass transistor is connected to the output terminal of described second current source and the drain electrode of the described first additional nmos pass transistor, the source electrode of the described 3rd additional nmos pass transistor is connected to the drain electrode of the described second additional nmos pass transistor, the grid of the described second additional nmos pass transistor connects bias voltage, the source electrode of the described first additional nmos pass transistor and the source ground of the described second additional nmos pass transistor.
Preferably, described error amplifier comprises: the first current source, the first PMOS transistor, the second PMOS transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor, wherein, the output terminal of described first current source is connected to the source electrode of described first PMOS transistor and the source electrode of described second PMOS transistor, the grid of described first PMOS transistor is as an input end of described error amplifier, the grid input reference voltage of described second PMOS transistor, the drain electrode of described first PMOS transistor is connected to the grid of described 3rd nmos pass transistor, the drain electrode of described second PMOS transistor is connected to the drain electrode of described 4th nmos pass transistor, the drain electrode of described first PMOS transistor is connected to the drain electrode of described 3rd nmos pass transistor and the grid of described 4th nmos pass transistor, the source electrode of described 3rd nmos pass transistor and the source ground of described 4th nmos pass transistor.
Preferably, described low pressure difference linear voltage regulator is used for low-power consumption application.
Preferably, the incoming level of expectation of circuit applied according to the low pressure difference linear voltage regulator of the described embodiment of the present invention of described reference voltage and the difference of output level are arranged.
Preferably, described bias voltage is arranged according to the physical features of the described second additional nmos pass transistor Ms2.
Effectively can improve voltage conversioning rate according to low pressure difference linear voltage regulator of the present invention and not increase power consumption, thus, low pressure difference linear voltage regulator according to the present invention is particularly useful for the application of the requirement fast current load response of low-power consumption.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the block diagram of the low pressure difference linear voltage regulator according to prior art.
Fig. 2 schematically shows the block diagram of the low pressure difference linear voltage regulator according to the embodiment of the present invention.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 2 schematically shows the block diagram of the low pressure difference linear voltage regulator according to the embodiment of the present invention.
As shown in Figure 2, comprise according to the low pressure difference linear voltage regulator of the embodiment of the present invention: error amplifier EA, impact damper BF, the first bypass N-type MOS transistor Mp1, the first resistor R1, the second resistor R2, resistors in series ESR, series capacitor CL and voltage conversioning rate promote circuit (as shown in the dotted line frame of Fig. 2).
Wherein, the output terminal of described error amplifier EA is connected to the input end of described impact damper BF, the output terminal of described impact damper BF is connected to the grid of described first bypass N-type MOS transistor Mp1, the source electrode of described first bypass N-type MOS transistor Mp1 is connected to supply voltage, the drain electrode of described first bypass N-type MOS transistor Mp1 is as the output terminal VOUT of described low pressure difference linear voltage regulator, and the drain electrode of described first bypass N-type MOS transistor Mp1 is connected to the first end of described first resistor R1 and is connected to the first end of described resistors in series ESR, second end of described first resistor R1 is connected to the first end of described second resistor R2 and is connected to the input end of described error amplifier EA, another input termination reference voltage of error amplifier EA, second end of described resistors in series ESR is connected to the first end of described series capacitor CL, second end of described second resistor R2 and the equal ground connection of the second end of the second resistor R2.
Wherein, described voltage conversioning rate lifting circuit comprises: the second bypass N-type MOS transistor Mp2, the first additional nmos pass transistor Ms1, the second additional nmos pass transistor Ms2, the 3rd additional PMOS transistor Ms3, the 3rd additional nmos pass transistor Msw and the second current source A2.Wherein, the source electrode of described second bypass N-type MOS transistor Mp2 and the drain source electrode that is connected respectively to described first bypass N-type MOS transistor Mp1 and drain electrode, the grid of the described first additional nmos pass transistor Ms1 is connected to the output terminal of described error amplifier, the source electrode of the described 3rd additional PMOS transistor Ms3 and grid are connected respectively source electrode to described second bypass N-type MOS transistor Mp2 and grid, the drain electrode of the described 3rd additional PMOS transistor Ms3 is connected to the drain electrode of the described 3rd additional nmos pass transistor Msw, and the grid of the described 3rd additional PMOS transistor Ms3 connects its drain electrode, the grid of the described 3rd additional nmos pass transistor Msw is connected to the output terminal of described second current source A2 and the drain electrode of the described first additional nmos pass transistor Ms1, the source electrode of the described 3rd additional nmos pass transistor Msw is connected to the drain electrode of the described second additional nmos pass transistor Ms2, the grid of the described second additional nmos pass transistor Ms2 meets bias voltage vb (such as, bias voltage vb can be set according to the physical features of the described second additional PMOS transistor Ms2, such as, bias voltage vb can be set to the threshold voltage of the described second additional PMOS transistor Ms2, such as 0.7V), the source electrode of the described first additional nmos pass transistor Ms1 and the source ground of the described second additional nmos pass transistor Ms2.
Wherein, described error amplifier EA comprises: the first current source A1, the first PMOS transistor M1, the second PMOS transistor M2, the 3rd nmos pass transistor M3 and the 4th nmos pass transistor M4.Wherein, the output terminal of described first current source A1 is connected to the source electrode of described first PMOS transistor M1 and the source electrode of described second PMOS transistor M2, the grid of described first PMOS transistor M1 is as an input end of described error amplifier EA, the grid input reference voltage VREF of described second PMOS transistor M2 (such as, the incoming level of expectation and the extent of output level of the circuit can applied according to the low pressure difference linear voltage regulator of the embodiment of the present invention arrange reference voltage VREF, the incoming level of expectation of the circuit that the low pressure difference linear voltage regulator that such as can be set to the embodiment of the present invention with reference to voltage VREF is applied and the difference of output level, such as 2-3V), the drain electrode of described first PMOS transistor M1 is connected to the grid of described 3rd nmos pass transistor M3, the drain electrode of described second PMOS transistor M2 is connected to the drain electrode of described 4th nmos pass transistor M4, the drain electrode of described first PMOS transistor M1 is connected to the drain electrode of described 3rd nmos pass transistor M3 and the grid of described 4th nmos pass transistor M4.The source electrode of described 3rd nmos pass transistor M3 and the source ground of described 4th nmos pass transistor M4.
Operation according to the low pressure difference linear voltage regulator of the embodiment of the present invention will be described below.
If current load current is lower, under being then in normal voltage level according to the output terminal VOUT of the low pressure difference linear voltage regulator of the embodiment of the present invention, the level of node A can not be too low, described 3rd additional nmos pass transistor Msw ends (not conducting), thus the described 3rd additional PMOS transistor Ms3 and described second bypass N-type MOS transistor Mp2 ends (not conducting), only described first bypass N-type MOS transistor Mp1 works.
But, when load current increases suddenly, become level according to the output terminal VOUT of the low pressure difference linear voltage regulator of the embodiment of the present invention lower.Generally, the response of error amplifier EA is very fast, thus the quick step-down of the level of node A.Lower node A makes the described 3rd additional nmos pass transistor Msw conducting, thus the described 3rd additional PMOS transistor Ms3 and described second bypass N-type MOS transistor Mp2 conducting.Thus, the low pressure difference linear voltage regulator according to the embodiment of the present invention can provide more electric current, and can not be too low according to the level of the output terminal VOUT of the low pressure difference linear voltage regulator of the embodiment of the present invention.After experience a period of time, as error amplifier EA, after impact damper BF and described first bypass N-type MOS transistor Mp1 has carried out responding, level according to the output terminal VOUT of the low pressure difference linear voltage regulator of the embodiment of the present invention gets back to normal voltage level, node A level uprises, described 3rd additional nmos pass transistor Msw ends (not conducting) subsequently, thus the described 3rd additional PMOS transistor Ms3 and described second bypass N-type MOS transistor Mp2 ends (not conducting), make to enter low power consumpting state according to the low pressure difference linear voltage regulator of the embodiment of the present invention.
Effectively can improve voltage conversioning rate according to the low pressure difference linear voltage regulator of the embodiment of the present invention and not increase power consumption, thus, being particularly useful for the application of the requirement fast current load response of low-power consumption according to the low pressure difference linear voltage regulator of the embodiment of the present invention.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (5)
1. a low pressure difference linear voltage regulator, is characterized in that comprising: error amplifier, impact damper, the first bypass N-type MOS transistor, the first resistor, the second resistor, resistors in series, series capacitor and voltage conversioning rate promote circuit;
Wherein, the output terminal of described error amplifier is connected to the input end of described impact damper, the output terminal of described impact damper is connected to the grid of described first bypass N-type MOS transistor, the source electrode of described first bypass N-type MOS transistor is connected to supply voltage, the drain electrode of described first bypass N-type MOS transistor is as the output terminal of described low pressure difference linear voltage regulator, and the drain electrode of described first bypass N-type MOS transistor is connected to the first end of described first resistor and is connected to the first end of described resistors in series, second end of described first resistor is connected to the first end of described second resistor and is connected to an input end of described error amplifier, another input termination reference voltage of error amplifier, second end of described resistors in series is connected to the first end of described series capacitor, second end of described second resistor and the equal ground connection of the second end of described series capacitor,
Wherein, described voltage conversioning rate lifting circuit comprises: the second bypass N-type MOS transistor, the first additional nmos pass transistor, the second additional nmos pass transistor, the 3rd additional PMOS transistor, the 3rd additional nmos pass transistor and the second current source; Wherein, the source electrode of described second bypass N-type MOS transistor and the drain source electrode that is connected respectively to described first bypass N-type MOS transistor and drain electrode; The grid of the described first additional nmos pass transistor is connected to the output terminal of described error amplifier; The source electrode of the described 3rd additional PMOS transistor and grid are connected respectively source electrode to described second bypass N-type MOS transistor and grid; The drain electrode of the described 3rd additional PMOS transistor is connected to the drain electrode of the described 3rd additional nmos pass transistor, and the grid of the described 3rd additional PMOS transistor connects its drain electrode; The grid of the described 3rd additional nmos pass transistor is connected to the output terminal of described second current source and the drain electrode of the described first additional nmos pass transistor, the source electrode of the described 3rd additional nmos pass transistor is connected to the drain electrode of the described second additional nmos pass transistor, the grid of the described second additional nmos pass transistor connects bias voltage, the source electrode of the described first additional nmos pass transistor and the source ground of the described second additional nmos pass transistor.
2. low pressure difference linear voltage regulator as claimed in claim 1, it is characterized in that, described error amplifier comprises: the first current source, the first PMOS transistor, the second PMOS transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor, wherein, the output terminal of described first current source is connected to the source electrode of described first PMOS transistor and the source electrode of described second PMOS transistor, the grid of described first PMOS transistor is as an input end of described error amplifier, the grid input reference voltage of described second PMOS transistor, the drain electrode of described first PMOS transistor is connected to the grid of described 3rd nmos pass transistor, the drain electrode of described second PMOS transistor is connected to the drain electrode of described 4th nmos pass transistor, the drain electrode of described first PMOS transistor is connected to the drain electrode of described 3rd nmos pass transistor and the grid of described 4th nmos pass transistor, the source electrode of described 3rd nmos pass transistor and the source ground of described 4th nmos pass transistor.
3. low pressure difference linear voltage regulator as claimed in claim 1 or 2, is characterized in that, described low pressure difference linear voltage regulator is used for low-power consumption application.
4. low pressure difference linear voltage regulator as claimed in claim 2, it is characterized in that, the incoming level of expectation and the difference of output level of the circuit that described reference voltage is applied according to described low pressure difference linear voltage regulator are arranged.
5. low pressure difference linear voltage regulator as claimed in claim 1 or 2, is characterized in that, described bias voltage is arranged according to the physical features of the described second additional nmos pass transistor.
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| CN201210312751.8A CN102789256B (en) | 2012-08-29 | 2012-08-29 | Low pressure difference linear voltage regulator |
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| CN201210312751.8A CN102789256B (en) | 2012-08-29 | 2012-08-29 | Low pressure difference linear voltage regulator |
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| CN102789256A CN102789256A (en) | 2012-11-21 |
| CN102789256B true CN102789256B (en) | 2016-03-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI595745B (en) * | 2016-03-28 | 2017-08-11 | 立積電子股份有限公司 | Amplifier |
| CN114460994A (en) * | 2020-11-09 | 2022-05-10 | 扬智科技股份有限公司 | Voltage regulator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2120123A1 (en) * | 2008-05-12 | 2009-11-18 | Stmicroelectronics SA | Slew rate control |
| CN102279612A (en) * | 2011-05-11 | 2011-12-14 | 电子科技大学 | Low dropout linear regulator |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
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2012
- 2012-08-29 CN CN201210312751.8A patent/CN102789256B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2120123A1 (en) * | 2008-05-12 | 2009-11-18 | Stmicroelectronics SA | Slew rate control |
| CN102279612A (en) * | 2011-05-11 | 2011-12-14 | 电子科技大学 | Low dropout linear regulator |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
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