CN102789133B - After develop inspection method - Google Patents
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- CN102789133B CN102789133B CN201110126372.5A CN201110126372A CN102789133B CN 102789133 B CN102789133 B CN 102789133B CN 201110126372 A CN201110126372 A CN 201110126372A CN 102789133 B CN102789133 B CN 102789133B
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Abstract
The invention relates to an after develop inspection method, which comprises: providing a substrate, and adopting a development process to form a patterned photoresist on the surface of the substrate; acquiring size data of the photoresist; establishing a database for describing a photoetching process environment, wherein the database at least comprises the size data of the photoresist and parameter data of the photoetching process; adopting the database to establish a photoetching process model; based on the photoetching process model, carrying out simulation calculation on a critical size of a substrate pattern formed correspondingly to the photoresist pattern by fitting the data of the database and empirical data, and inspecting the critical size. According to the present invention, the database at least comprising photoresist size data is established, the database is adopted to establish the photoetching process model, and simulation calculation and inspection are performed on the subsequent etching effect to inspect unqualified chips before an etching stage so as to prevent unqualified chips from entering the etching stage and improve chip qualification rate.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of rear inspection method of developing.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor devices is in order to reach arithmetic speed faster, larger data storage amount and more function, and semi-conductor chip is to high integration future development more; And the integrated level of semi-conductor chip is higher, the critical dimension of semiconductor devices (CD, Critical Dimension) is less.
Process manufacturing technology is at present all to adopt stepper to carry out the transfer of photoengraving pattern, to obtain preferably resolution and preferably particulate tolerance.But the topmost problem of this mode is a slice chip need to be adopted to regional exposure mode, complete the making of simple layer patterning, therefore need to carry out the exposure of tens of times, just can complete the processing procedure of the single photoresist layer on a wafer, therefore in order to allow the stacking of pattern between each layer photoetching can be accurate, after must developing to chip, check (after develop inspection after developing manufacture process completes, ADI), to guarantee the developing manufacture process in this photoetching stage demand that meets the specification.
Particularly, on chip, form after the photoresistance of patterning, described photoresistance is checked, comprise photoresistance covering, aligning, exposure, development etc. are checked one by one, and judge whether photoresistance performance meets the code requirement of technique.
The same with any manufacturing process, the target of photoetching process is no defective product.But not checking or stay in photoresistance defect will be catastrophic problem.After developing, inspection can be found wrong and correct on the spot, and this is one of the rare several steps that can correct in chip manufacturing proces.Be sent to once be formed with the chip of defect photoresistance the step (as etching) that next figure forms, the chance of just not correcting a mistake.If a chip is by wrong etching, it has just had fatal defect, is considered to waste product, will lose serious.So check after developing that data are extremely important for description and raising photoresistance operational characteristic.
Wherein, the rear inspection of the development of prior art can only reach photoresistance shape, i.e. the live width size of post-develop resistance detects, and can not further the critical size that is undertaken forming after etching by this photoresistance shape be estimated and be detected.If critical size is estimated in the step that can check afterwards in development, can check out underproof chip in advance, to avoid larger generation loss, improve chip yield.
Summary of the invention
The problem that the present invention solves is to provide a kind of rear inspection method of developing, with the stage checking afterwards in development, follow-up etching effect is carried out to analog computation and inspection, to check out underproof chip before etch stages, avoid defective chip to enter etch stages, improve chip yield.
For addressing the above problem, the invention provides a kind of rear inspection method of developing, comprising:
Substrate is provided, adopts developing process, form the photoresistance of patterning at described substrate surface;
Obtain the dimensional data of described photoresistance;
Building database, for describing photoetching process environment, described database at least includes the dimensional data of described photoresistance, and photoetching process supplemental characteristic;
Utilize described Database photoetching process model;
According to described photoetching process model, and by data and the empirical data in fitting data storehouse, the critical size of the corresponding base pattern forming of pattern of photoresistance described in analog computation, and described critical size is checked.
Optionally, also comprise: technological requirement is provided, if described critical size meets technological requirement, corresponding photoresistance is qualified photoresistance.
Optionally, also comprise: technological requirement is provided, if described critical size does not meet technological requirement, corresponding photoresistance has defect.
Optionally, if described photoresistance has defect, remove the defective photoresistance of described tool, and described substrate is entered to the flow process of doing over again.
Optionally, described photoresistance be shaped as rectangle or trapezoidal.
Optionally, the dimensional data of described photoresistance includes described photoresistance thickness, top dimension, bottom size, middle part size are with one of sidewall slope angle or combination.
Optionally, described photoetching process parameter at least comprises that time shutter, exposure wavelength, exposure energy distribute.
Optionally, after described development, inspection method also comprises the covering, aligning, exposure, the development effect that check photoresistance.
Optionally, the photoresistance that obtains described patterning comprises: the photomask board of patterning is provided, develops according to the pattern of photomask board, obtain the photoresistance of patterning.
Compared with prior art, the present invention has the following advantages:
By setting up the database that at least includes photoresistance dimensional data, and utilize described Database photoetching process model, follow-up etching effect is carried out to analog computation and inspection, to check out underproof chip before etch stages, avoid defective chip to enter etch stages, improve chip yield.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of inspection method after the development of one embodiment of the invention.
Fig. 2 to Fig. 4 is the structural representation of inspection method after the development of one embodiment of the invention.
Embodiment
The rear inspection of development of prior art can only reach photoresistance shape, i.e. the live width size of post-develop resistance detects, and can not further the critical size that is undertaken forming after etching by this photoresistance shape be estimated and be detected.
For critical size being estimated in the step that can check afterwards in development, check out in advance underproof chip, to avoid larger generation loss, improve chip yield, the invention provides a kind of rear inspection method of developing, comprise: substrate is provided, adopts developing process, form the photoresistance of patterning at described substrate surface; Obtain the dimensional data of described photoresistance; Building database, for describing photoetching process environment, described database at least includes the dimensional data of described photoresistance, and photoetching process supplemental characteristic; Utilize described Database photoetching process model; According to described photoetching process model, and by data and the empirical data in fitting data storehouse, the critical size of the corresponding base pattern forming of pattern of photoresistance described in analog computation, and described critical size is checked.
By setting up the database that at least includes photoresistance dimensional data, and utilize described Database photoetching process model, follow-up etching effect is carried out to analog computation and inspection, to check out underproof chip before etch stages, avoid defective chip to enter etch stages, improve chip yield.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
As shown in Figure 1, be the schematic flow sheet of inspection method after the development of one embodiment of the invention, comprising:
Execution step S1, provides and forms figuratum photomask board, is developed and is formed the photoresistance of patterning by described photomask board in substrate;
Execution step S2, measures described photoresistance, and obtains the dimensional data of described photoresistance;
Execution step S3, building database, to describe photoetching process environment, described database at least includes the dimensional data of described photoresistance;
Execution step S4, utilizes described Database photoetching process model;
Execution step S5, according to described photoetching process model, the critical size of the corresponding base pattern forming of pattern of photoresistance described in analog computation, and described critical size is checked.
Execution step S6, provides technological requirement, if described critical size meets technological requirement, corresponding photoresistance is qualified photoresistance; Otherwise there is defect for corresponding photoresistance.
Execution step S7, if described photoresistance has defect, removes the defective photoresistance of described tool, and described substrate is entered to the flow process of doing over again.
Fig. 2 to Fig. 4 is the structural representation of inspection method after the development of one embodiment of the invention.
The photoresistance size that after developing, inspection method is mainly used in forming after developing checks, to estimate acquisition etching effect corresponding to photoresistance size.In the present embodiment, provide respectively three kinds of difform photoresistances, and obtain the dimensional data of three groups of photoresistances, the photomask board that described three groups of photoresistances are same pattern forms by developing process.By actual developing process, the photomask board of same pattern may correspondingly form difform photoresistance.Described three groups of photoresistances can form three groups of photoresistances for developing process once, can be also multidevelopment technique corresponding formation respectively.As other embodiment, it can also be the photoresistance of other numbers.
As shown in Figure 2, provide three substrates, be respectively the first substrate 100, the second substrate 200 and the 3rd substrate 300, above-mentioned substrate respectively correspondence is formed with non-patterned the first original photoresistance 110, the second original photoresistance 210 and the 3rd original photoresistance 310.
Continue with reference to figure 2, also provide the photomask board 001 that is formed with fixed pattern, by developing process, by original the design transfer of described photomask board 001 photoresistance.Specifically comprise: the photomask board of patterning is provided, develops according to the pattern of photomask board, obtain the photoresistance of patterning.
As shown in Figure 3, corresponding to the photomask board 001 of same shape, because the difference of developing process may can be formed with difform photoresistance through development.The present embodiment, is also that etching effect corresponding to difform photoresistance estimated, etching effect checked at development after-stage and to assess.
The present embodiment, only illustrates the wherein photoresistance of three difform patternings (hereinafter to be referred as " photoresistance "), is respectively the first photoresistance 111, the second photoresistance 211 and the 3rd photoresistance 311.Wherein, the bottom of described the first photoresistance 111 and top, for flushing, are rectangle, and the top of the second photoresistance 211 is less than bottom, and the bottom of the 3rd photoresistance 311 is less than top, and described the second photoresistance 211 and the 3rd photoresistance 311 are trapezoidal.
With reference to figure 3, measure the first photoresistance 111, the second photoresistance 211 and the 3rd photoresistance 311, and obtain the dimensional data of described the first photoresistance 111, the second photoresistance 211 and the 3rd photoresistance 311.The dimensional data of described photoresistance includes the thickness, top dimension, bottom size, middle part size of described photoresistance with one of sidewall slope angle or combination.
Described dimensional data can also include other for describing the dimensional data of described photoresistance shape, as the form parameter at interface, photoresistance top, other form parameters such as the form parameter on inclined-plane.
In the present embodiment, the rear inspection of described development also comprises the covering, aligning, exposure, the developing process that check photoresistance.
For the first photoresistance 111, the second photoresistance 211 and the 3rd photoresistance 311 in the present embodiment, the covering of described photoresistance, aligning, exposure, developing process all meet the requirements.Follow-up will, to simulating etching with described the first photoresistance 111, the second photoresistance 211 and the 3rd photoresistance 311 respectively, obtain the critical size of base pattern.
Then, building database, to describe photoetching process environment, described database at least includes the dimensional data of described photoresistance.
Described database also includes photoetching process parameter, and described photoetching process parameter at least comprises that time shutter, exposure wavelength, exposure energy distribute.Described database can also include the material parameter of substrate, as the size in substrate region to be etched.By the data in described database, comprise dimensional parameters and the photoetching process parameter of photoresistance, to describe photoetching process environment in detail.
Set up after described database, utilize described Database photoetching process model.Wherein, process modeling carries out modeling to the behavior of one or more semiconductor fabrication process (as photoetching process) that is usually directed to complicated physics or chemical interaction, and by kernel parameter and empirical data matching or calibration being determined to process modeling and corresponding simulated data.
First, by being applied to one or more test layouts, the semiconductor fabrication process that needs modeling generates empirical data, in the present embodiment, what need modeling is photoetching process model, first on chip, print test layouts, by apply described test layouts in actual photoetching process environment, obtain the empirical data corresponding with actual light carving technology, the empirical data of described actual light carving technology comprises the chip critical size after the photoetching of the size of photoresistance, photoetching process parameter and acquisition.Finally, by unregulated process modeling and empirical data matching, to obtain photoetching process model and corresponding simulated data.Be the critical size that analog computation goes out the corresponding base pattern forming of pattern of described photoresistance, and described critical size is checked.
In the present embodiment, the kernel parameter of described photoetching process model comprises the database that the present embodiment provides, described database at least includes the dimensional data of described photoresistance, described database also includes photoetching process parameter, and described photoetching process parameter at least comprises that time shutter, exposure wavelength, exposure energy distribute.Described database can also include the material parameter of substrate, as the size in substrate region to be etched.
Described photoetching process model includes the arithmetic section of photoresistance size and the arithmetic section of photoetching process environmental parameter.Being shown below, is the arithmetic section about photoresistance size in described photoetching process model, and wherein, described photoresistance size includes thickness K1, middle part size K2 and the sidewall slope angle K3 of photoresistance:
The thickness K1, the middle part size K2 that are photoresistance carry out convolution between two with sidewall slope angle K3.On the basis of described photoresistance size arithmetic section, add photoetching process environmental parameter, as time shutter T, exposure wavelength L, exposure energy distribution W.Accordingly, between the parameter in described photoetching process environmental parameter, carry out convolution, also comprise each parameter in photoresistance size will with photoetching process environment in parameter carry out convolution.As follows:
Be illustrated in figure 4 the critical size going out according to described analog computation, the simulation etching pattern obtaining respectively, comprises the first simulation etching pattern 130, the second simulation etching pattern 230 and the 3rd simulation etching pattern 330.
With reference to figure 4 and Fig. 3, provide technological requirement, the process requirement that critical size of the base pattern of formation corresponding to photoresistance should meet.If described critical size meets technological requirement, corresponding photoresistance is qualified photoresistance, otherwise has defect for corresponding photoresistance.
In the present embodiment, by the analog computation of photoetching process model, the critical size of described the first simulation etching pattern 130 and the second simulation etching pattern 230 correspondences meets technological requirement, and accordingly, described the first photoresistance 111 and the second photoresistance 211 are qualified photoresistance; And the critical size of described the 3rd simulation etching pattern 330 correspondences does not meet technological requirement, described the 3rd photoresistance 311 has defect.Accordingly, remove defective the 3rd photoresistance 311 of described tool, and described the 3rd substrate 300 is entered to the flow process of doing over again.
Compared with prior art, the present invention has the following advantages:
By setting up the database that at least includes photoresistance dimensional data, and utilize described Database photoetching process model, follow-up etching effect is carried out to analog computation and inspection, to check out underproof chip before etch stages, avoid defective chip to enter etch stages, improve chip yield.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, therefore protection scope of the present invention should be as the criterion with the scope that the claims in the present invention were defined.
Claims (8)
1. an inspection method after development, comprising:
Substrate is provided, adopts developing process, form the photoresistance of patterning at described substrate surface;
Obtain the dimensional data of described photoresistance, the dimensional data of described photoresistance includes one of the thickness of described photoresistance, top dimension, bottom size, middle part size and sidewall slope angle or combination;
Building database, for describing photoetching process environment, described database at least includes the dimensional data of described photoresistance, and photoetching process supplemental characteristic;
Utilize described Database photoetching process model;
According to described photoetching process model, and by data and the empirical data in fitting data storehouse, the critical size of the corresponding base pattern forming of pattern of photoresistance described in analog computation, and described critical size is checked.
2. inspection method after development as claimed in claim 1, is characterized in that, also comprises: technological requirement is provided, if described critical size meets technological requirement, corresponding photoresistance is qualified photoresistance.
3. inspection method after development as claimed in claim 1, is characterized in that, also comprises: technological requirement is provided, if described critical size does not meet technological requirement, corresponding photoresistance has defect.
4. inspection method after development as claimed in claim 3, is characterized in that, if described photoresistance has defect, removes the defective photoresistance of described tool, and described substrate is entered to the flow process of doing over again.
5. inspection method after development as claimed in claim 1, is characterized in that, described photoresistance be shaped as rectangle or trapezoidal.
6. inspection method after development as claimed in claim 1, is characterized in that, described photoetching process parameter at least comprises that time shutter, exposure wavelength, exposure energy distribute.
7. inspection method after development as claimed in claim 1, is characterized in that, after described development, inspection method also comprises the covering, aligning, exposure, the development effect that check photoresistance.
8. inspection method after development as claimed in claim 1, is characterized in that, the photoresistance that obtains described patterning comprises: the photomask board of patterning is provided, develops according to the pattern of photomask board, obtain the photoresistance of patterning.
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| CN201110126372.5A CN102789133B (en) | 2011-05-16 | 2011-05-16 | After develop inspection method |
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| US9612541B2 (en) * | 2013-08-20 | 2017-04-04 | Kla-Tencor Corporation | Qualifying patterns for microlithography |
| CN111650820B (en) * | 2020-06-28 | 2022-06-17 | 上海华虹宏力半导体制造有限公司 | Method for determining applicable condition of light resistance and used mask plate |
| CN112038249B (en) * | 2020-08-27 | 2022-08-09 | 上海华力集成电路制造有限公司 | Method for detecting abnormal process of photoetching process |
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| CN1498418A (en) * | 2001-03-20 | 2004-05-19 | 数字技术股份有限公司 | System and method of providing mask defect printablity analysis |
| CN101493655A (en) * | 2008-01-21 | 2009-07-29 | 联华电子股份有限公司 | Exposure method |
| JP4422000B2 (en) * | 2004-11-16 | 2010-02-24 | 東京エレクトロン株式会社 | Substrate processing method, control program, and computer storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6620563B2 (en) * | 2001-03-08 | 2003-09-16 | Motorola, Inc. | Lithography method for forming semiconductor devices on a wafer utilizing atomic force microscopy |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1498418A (en) * | 2001-03-20 | 2004-05-19 | 数字技术股份有限公司 | System and method of providing mask defect printablity analysis |
| JP4422000B2 (en) * | 2004-11-16 | 2010-02-24 | 東京エレクトロン株式会社 | Substrate processing method, control program, and computer storage medium |
| CN101493655A (en) * | 2008-01-21 | 2009-07-29 | 联华电子股份有限公司 | Exposure method |
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| JP特许第4422000号B2 2010.02.24 |
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