CN102780472A - Method for realizing brand new synchronizing pulse measurement of vector network analyzer by utilizing field programmable gate array (FPGA) - Google Patents
Method for realizing brand new synchronizing pulse measurement of vector network analyzer by utilizing field programmable gate array (FPGA) Download PDFInfo
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Abstract
The invention belongs to the technical field of test, and discloses a method for completely synchronizing data processing and pulse generating in a pulse state by synchronizing a data acquisition time of an analyzer with an external pulse signal or an internal synchronization signal by controlling a data processing program of the vector network analyzer by utilizing a field programmable gate array (FPGA) chip. According to the method, by utilizing the programmable characteristic of a programmable logic array, a pulse synchronization signal input by a specified port and a synchronization signal generated by the internal of a system are detected according to user settings under the trigger of the same clock according to the programmable features of a programmable logic array; and when the synchronization signal is valid, the pulse output and the data processing programs are started, so that the data acquisition of the vector network analyzer is ensured to be started at the time specified by a user; and therefore, the synchronous measurement in the pulse state is realized.
Description
Technical field
The invention belongs to technical field of measurement and test, relate to the method that a kind of FPGA of utilization realizes that the brand-new lock-out pulse of vector network analyzer is measured.
Background technology
Traditional pulse vector network analyzer only provides the lock-out pulse metering system; It utilizes the counter of the ADC transducer of internal system to produce inner synchronousing signal; Can't be external the synchronizing signal of user's input, only can guarantee that the modulation of data processing and clock is synchronous.The program capability that utilizes fpga chip of novelty of the present invention; Judgement of synchronous source and detection module, synchronous triggering pulse generating module, pulse generating module and data acquisition module have been write; Base when these several modules adopt same height steady; Guarantee the correlation of the signal that several modules produce; Thereby realized under the pulse condition data acquisition and pulse signal fully synchronously, satisfy the moment that the user comes synchronous vector network analyzer output clock signal according to the signal of own appointment, the appearance of control analysis is simultaneously gathered the requirement that the user specifies spectrum information constantly.
Traditional pulse vector network analyzer; Can only produce fixing synchronous triggering signal according to internal system mechanism; This synchronizing signal only can guarantee to realize the broadband synchro measure function of pulse; Neither allow to utilize external signal to come synchronously, can not synchronous data collection be set constantly by user's own.The present invention then utilizes the programmable features of fpga chip; Make the pulse network analyzer both can independently produce pulse synchronous signal; Can also detect the synchronizing signal of user's input; User's control and analyzer data acquisition, the complete synchronization onwards of processing are come, when height is steady, in the base resolution, synchronizing relay, sampling instant etc. can be set flexibly.
Summary of the invention
The present invention is directed to above-mentioned technical problem provides a kind of FPGA of utilization to realize the method that the brand-new lock-out pulse of vector network analyzer is measured.
For solving the problems of the technologies described above; The technical scheme that the present invention adopts is: provide a kind of FPGA of utilization to realize the method that the brand-new lock-out pulse of vector network analyzer is measured; Utilize one synchronously the source judge and detection module is analyzed the synchronizing signal source, if external sync mode, then detect the state of designated port according to the polar requirement of user input signal; Detect signal input polarity when consistent, then produce a synchronous enabled signal with customer requirements; If internal synchronization mode then is provided with synchronous enabled signal is enabled, and synchronous enabled signal is finally sent into the synchronous triggering pulse generating module; During internal synchronization mode, the synchronous triggering pulse generating module produces the synchronization pulse that pulsewidth is 1 clock according to the pulse repetition period that the user is provided with; During external sync mode, the pulsewidth of the synchronous triggering pulse signal of system output is the maximum that time-delay adds pulsewidth among the pulse 1～N that will produce of system, if the edge triggering mode, the cycle of start pulse signal is consistent with the external synchronization signal cycle; If level triggering mode, exported a string start pulse signal after, if synchronizing signal is kept effectively, then continue output and descend a string trigger impulse; The triggering signal that last synchronous triggering pulse generating module produces gets into pulse generating module and data acquisition module; Pulse generating module produces the N road pulse signal of appointment; Said N is not more than 4; Time-delay, the width of pulse signal are specified by the user, and the cycle then equates with the cycle of synchronous triggering pulse signal, and the pulse output time is the rising edge of trigger impulse; Whether data acquisition module can be provided with synchronous with the synchronous triggering pulse signal by the user; In the time of synchronously; After receiving the lock-out pulse triggering signal, start digital filter program after the time of time-delay appointment, if asynchronous sampling instant is by pulse vector network analyzer Autonomous Control.
Said edge triggering mode is rising edge or trailing edge, and said level triggering mode is high level or low level.
The invention has the beneficial effects as follows:
Inner, outside two kinds of synchronous triggering modes that the present invention provides; Triggering time-delay and sampling instant can be provided with flexibly; Support multiple triggering mode (edge triggering, level triggers) outward when synchronous; Control impuls time of origin and data acquisition time that can be convenient when making the user utilize the pulse vector network analyzer to measure guarantee the controllability of analyser output signal, thereby protect unit under test.
Description of drawings
Fig. 1 is principle of the invention figure;
Fig. 2: each signal relation figure during the inner method of synchronization;
Each signal relation figure when Fig. 3 is external sync mode.
Embodiment
Set forth in detail in the face of preferred embodiment of the present invention down, thereby protection scope of the present invention is made more explicit defining so that advantage of the present invention and characteristic can be easier to it will be appreciated by those skilled in the art that.
The embodiment of the invention comprises:
At first utilize a source judgement synchronously and detection module to analyze the synchronizing signal source; If external sync mode; Then detect the state of designated port, detect signal input polarity when consistent, then produce a synchronous enabled signal with customer requirements according to the polar requirement of user input signal; If internal synchronization mode then is provided with synchronous enabled signal is enabled, and synchronous enabled signal is finally sent into the synchronous triggering pulse generating module.During internal synchronization mode, the synchronous triggering pulse generating module produces the synchronization pulse that pulsewidth is 1 clock according to the pulse repetition period that the user is provided with; During external sync mode; The pulsewidth of the synchronous triggering pulse signal of system output is the maximum that time-delay adds pulsewidth among the pulse 1～N that will produce of system; If edge triggering mode (rising edge, trailing edge), the cycle of start pulse signal is consistent with the external synchronization signal cycle; If level triggering mode (high level, low level), exported a string start pulse signal after, if synchronizing signal is kept effectively, then continue output and descend a string trigger impulse.The triggering signal that last synchronous triggering pulse generating module produces gets into pulse generating module and data acquisition module; Pulse generating module produces the N road pulse signal (N is not more than 4) of appointment; Time-delay, the width of pulse signal are specified by the user; Cycle then equates with the cycle of synchronous triggering pulse signal, and the pulse output time is the rising edge of trigger impulse; Whether data acquisition module can be provided with synchronous with the synchronous triggering pulse signal by the user; In the time of synchronously; After receiving the lock-out pulse triggering signal, start digital filter program after the time of time-delay appointment, if asynchronous sampling instant is by pulse vector network analyzer Autonomous Control.
Be each the signal relation sketch map under two kinds of synchronous modes below, wherein D1 and Dn represent pulse delay, the pulse output signals of not going the same way, and time-delay and width can be provided with respectively, and the cycle then must be consistent.
Can find out among Fig. 2 that during the inner method of synchronization, the synchronous triggering pulse signal is produced by system automatically, its cycle equals the cycle that the user is provided with, the time-delay that note every road signal and width and can not be greater than the pulse period.Among the last figure signal be data acquisition module and inter-sync signal Synchronization the time state, this moment sampling time-delay is set by the user, if data acquisition module does not adopt the method for synchronization, sampling instant is independently definite by analyzer so.Whole signals among Fig. 2 all are based on same height among Fig. 1 base when steady in addition, that is to say that the resolution of signal is all consistent, and the benefit of doing like this is the relevant fully and strict synchronism that can guarantee between each signal.
Each signal relation sketch map when following Fig. 3 is external sync mode for synchronisation source, time-delay and the pulsewidth and the maximum on hypothesis pulse n road among the figure, the width of start pulse signal equals this maximum; The cycle of each road signal is identical with the cycle of external synchronization signal.Outer synchronous triggering mode is the rising edge method of synchronization.Among the figure all the resolution of signals the same with Fig. 2 also to be based on same height among Fig. 1 basic when steady.
The above is merely embodiments of the invention; Be not so limit claim of the present invention; Every equivalent structure or equivalent flow process conversion that utilizes description of the present invention to do; Or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (2)
1. one kind is utilized FPGA to realize the method that the brand-new lock-out pulse of vector network analyzer is measured; It is characterized in that; Utilize one synchronously the source judge and detection module is analyzed the synchronizing signal source, if external sync mode, then detect the state of designated port according to the polar requirement of user input signal; Detect signal input polarity when consistent, then produce a synchronous enabled signal with customer requirements; If internal synchronization mode then is provided with synchronous enabled signal is enabled, and synchronous enabled signal is finally sent into the synchronous triggering pulse generating module; During internal synchronization mode, the synchronous triggering pulse generating module produces the synchronization pulse that pulsewidth is 1 clock according to the pulse repetition period that the user is provided with; During external sync mode, the pulsewidth of the synchronous triggering pulse signal of system output is the maximum that time-delay adds pulsewidth among the pulse 1～N that will produce of system, if the edge triggering mode, the cycle of start pulse signal is consistent with the external synchronization signal cycle; If level triggering mode, exported a string start pulse signal after, if synchronizing signal is kept effectively, then continue output and descend a string trigger impulse; The triggering signal that last synchronous triggering pulse generating module produces gets into pulse generating module and data acquisition module; Pulse generating module produces the N road pulse signal of appointment; Said N is not more than 4; Time-delay, the width of pulse signal are specified by the user, and the cycle then equates with the cycle of synchronous triggering pulse signal, and the pulse output time is the rising edge of trigger impulse; Whether data acquisition module can be provided with synchronous with the synchronous triggering pulse signal by the user; In the time of synchronously; After receiving the lock-out pulse triggering signal, start digital filter program after the time of time-delay appointment, if asynchronous sampling instant is by pulse vector network analyzer Autonomous Control.
2. the method for claim 1, said edge triggering mode is rising edge or trailing edge, said level triggering mode is high level or low level.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103592637A (en) * | 2013-11-07 | 2014-02-19 | 中国电子科技集团公司第四十一研究所 | Method and device for testing digital array module transmitting channel phase congruency |
| CN103595580A (en) * | 2013-11-07 | 2014-02-19 | 中国电子科技集团公司第四十一研究所 | Method and device for testing digital array module receiving delay |
| CN106771651A (en) * | 2016-11-15 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | The synchronous method of data acquisition in a kind of pulse network analyzer pulse |
| CN117348949A (en) * | 2023-12-05 | 2024-01-05 | 成都玖锦科技有限公司 | Multi-channel measurement method and system based on vector network analyzer |
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| DE102009018778A1 (en) * | 2009-04-24 | 2010-10-28 | Rohde & Schwarz Gmbh & Co. Kg | Measuring device and measuring method with dynamic channel assignment |
| CN102170345A (en) * | 2011-04-27 | 2011-08-31 | 浙江大华技术股份有限公司 | High definition camera self-adaption digitization external synchronization method |
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| DE102009018778A1 (en) * | 2009-04-24 | 2010-10-28 | Rohde & Schwarz Gmbh & Co. Kg | Measuring device and measuring method with dynamic channel assignment |
| CN101834714A (en) * | 2010-05-10 | 2010-09-15 | 淮阴工学院 | Synchronous dynamic tester capable of cascading with great amount of channels |
| CN102170345A (en) * | 2011-04-27 | 2011-08-31 | 浙江大华技术股份有限公司 | High definition camera self-adaption digitization external synchronization method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103592637A (en) * | 2013-11-07 | 2014-02-19 | 中国电子科技集团公司第四十一研究所 | Method and device for testing digital array module transmitting channel phase congruency |
| CN103595580A (en) * | 2013-11-07 | 2014-02-19 | 中国电子科技集团公司第四十一研究所 | Method and device for testing digital array module receiving delay |
| CN103595580B (en) * | 2013-11-07 | 2016-08-17 | 中国电子科技集团公司第四十一研究所 | A kind of digital array module reception delay method of testing and device |
| CN106771651A (en) * | 2016-11-15 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | The synchronous method of data acquisition in a kind of pulse network analyzer pulse |
| CN106771651B (en) * | 2016-11-15 | 2019-07-05 | 中国电子科技集团公司第四十一研究所 | The synchronous method of data acquisition in a kind of pulse network analyzer pulse |
| CN117348949A (en) * | 2023-12-05 | 2024-01-05 | 成都玖锦科技有限公司 | Multi-channel measurement method and system based on vector network analyzer |
| CN117348949B (en) * | 2023-12-05 | 2024-03-12 | 成都玖锦科技有限公司 | Multi-channel measurement method and system based on vector network analyzer |
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Address after: No. 726 Changzheng Road, Bengbu, Anhui Province Patentee after: The 41st Institute of CETC Address before: 266000 Qingdao economic and Technological Development Zone, Shandong Xiangjiang Road, No. 98 Patentee before: The 41st Institute of CETC |
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Effective date of registration: 20190315 Address after: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: China Electronics Technology Instrument and Meter Co., Ltd. Address before: No. 726 Changzheng Road, Bengbu, Anhui Province Patentee before: The 41st Institute of CETC |
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Address after: 266555 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: CLP kesiyi Technology Co.,Ltd. Address before: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |