CN102769430B - Clock generation method, no-reference frequency receiver and no-crystal oscillator system - Google Patents
Clock generation method, no-reference frequency receiver and no-crystal oscillator system Download PDFInfo
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Abstract
The invention provides a clock generation method used for generating a clock signal for a receiver, a transceiver, a receiving system, and a transceiving system. The clock generation method comprises the following steps that at least one input signal is subjected to a data and pattern detection so as to generate recovery data; at least one synchronous pattern in the input signal is detected according to a synchronous pattern rule so as to generate a synchronous signal corresponding to the synchronous pattern; and the synchronous signal is subjected to a frequency locking so as to generate the clock signal, wherein the step for data/pattern detection also comprises: performing digital operation to the input signal so as to detect the logic values which are represented by the input signal at a plurality of time points, performing bit rotation state detection so as to generate bit rotation state detection results, analyzing at least one part of the logic values so as to dynamically judging/updating unit bit length, and converting the logic values to recovery data. The invention also provides a relative no-reference frequency receiver and a relative no-crystal oscillator system.
Description
Technical field
The invention relates to universal serial bus (Universal Serial Bus, USB) communication is espespecially a kind of clock generation method, relevant without reference frequency (Reference-less) receiver and relevant non-crystal oscillator (Crystal-less) system.
Background technology
Typical traditional receiver needs an external crystal oscillator usually, therefore its framework is comparatively complicated.Especially, external crystal oscillator is adopted can to produce many problems as the source with reference to frequency.Such as: when traditional receiver adopts external crystal oscillator as during with reference to the source of frequency; need extra terminal and relevant static discharge (Electrostatic Discharge; ESD) protective circuit, these all can cause extra cost.In addition, correlation technique does not have adequate solution scheme for the problem such as power consumption and switching noise of external crystal oscillator.In addition, the application of some kind has the restriction of thickness; The thickness of such as, chip in chip card is no more than 800 microns (Micrometer) usually, and this numerical value is far below the representative width of the shell of external crystal oscillator, therefore external crystal oscillator is not suitable for the application of this class.
In response to above-mentioned problem, correlation technique proposes some solutions; But these schemes can cause some side effects.Such as: correlation technique needs conductance-capacitor oscillator (Inductance-Capacitance Oscillator usually, LC OSC), resistor-capacitor oscillator (Resistance-Capacitance Oscillator, RC OSC), energy gap with reference to (Band-gapReference) circuit and/or passive device, make processing procedure complicated and cost increases.Therefore, need a kind of method of novelty to produce clock, not need external crystal oscillator and the situation not producing above-mentioned side effect is issued to best receiver usefulness.
Summary of the invention
Therefore an object of the present invention is to provide a kind of clock generation method, relevant without reference frequency (Reference-less) receiver and relevant non-crystal oscillator (Crystal-less) system, to solve the problem.
Another object of the present invention is to provide a kind of clock generation method, relevant without reference frequency receiver and relevant non-crystal oscillator system, not need external crystal oscillator and the situation not producing above-mentioned side effect is issued to best receiver/transceiver usefulness.
Another object of the present invention is to provide a kind of clock generation method, relevant without reference frequency receiver and relevant non-crystal oscillator system, to promote transmission usefulness.Even if under the situation that the initial frequency errors at transmission channel two ends is very large, the framework realized according to the present invention still properly can carry out reception running.
There is provided a kind of clock generation method in preferred embodiment of the present invention, wherein this clock generation method is used for generation one clock signal for one receiver/transceiver/receiving system/receive-transmit system use.This clock generation method includes: carry out data/type sample (Pattern) at least one input signal and detect to produce restored data; Then detect at least one sync pattern in this input signal according to a synchronized model control gauge, and produce the synchronizing signal corresponding to this sync pattern; And frequency locking is carried out to produce this clock signal to this synchronizing signal; Wherein carry out data/type sample detection to this at least one input signal also to comprise with the step producing this restored data: carry out digitlization running to this input signal, to detect this input signal respectively at the logical value representated by multiple time point, the length between the wantonly two adjacent time points wherein in the plurality of time point equals a predetermined amount of delay; Carry out a transition according to those logical values and detect running, to produce a transition testing result; By utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade a unit bit length, wherein this unit bit length is multiple measured in units of this predetermined amount of delay; And according to this unit bit length, those logical values are converted to this restored data.
There is provided a kind of without reference frequency receiver in preferred embodiment of the present invention, be used for that data/type sample is carried out at least one input signal and detect to produce restored data.This includes without reference frequency receiver: a digitizer, a transition detect (Bit Transition Detection) unit, unit interval detection (Unit-time Detection) unit and an one data/type sample decoder (Data/PatternDecoder).This digitizer is used for carrying out digitlization running to this input signal, and to detect this input signal respectively at the logical value representated by multiple time point, the length between the wantonly two adjacent time points wherein in the plurality of time point equals a predetermined amount of delay.This transition detecting unit is used for carrying out a transition according to those logical values and detects running, to produce a transition testing result.In addition, this unit interval detecting unit by utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade a unit bit length, wherein this unit bit length is multiple measured in units of this predetermined amount of delay.In addition, these data/type sample decoder is used for, according to this unit bit length, those logical values are converted to this restored data.
The present invention, while providing said method, also provides a kind of non-crystal oscillator system accordingly, is used for generation one clock signal for one receiver/transceiver/receiving system/receive-transmit system use.This non-crystal oscillator system includes: one data/type sample detection module, a sync pattern detection module and a frequency locking device, wherein this frequency locking device comprises at least one hardware circuit.These data/type sample detection module is used for carrying out data/type sample at least one input signal and detects to produce restored data.In addition, this sync pattern detection module is used for then detecting at least one sync pattern in this input signal according to a synchronized model control gauge, and produces the synchronizing signal corresponding to this sync pattern.In addition, this frequency locking device is used for carrying out frequency locking to produce this clock signal to this synchronizing signal.Wherein these data/type sample detection module includes: a digitizer, transition detecting unit, an a unit interval detecting unit and one data/type sample decoder.This digitizer is used for carrying out digitlization running to this input signal, and to detect this input signal respectively at the logical value representated by multiple time point, the length between the wantonly two adjacent time points wherein in the plurality of time point equals a predetermined amount of delay.In addition, this transition detecting unit is used for carrying out a transition according to those logical values and detects running, to produce a transition testing result.In addition, this unit interval detecting unit is used for by utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade a unit bit length, wherein this unit bit length is multiple measured in units of this predetermined amount of delay.In addition, these data/type sample decoder is used for, according to this unit bit length, those logical values are converted to this restored data.
Accompanying drawing explanation
Figure 1A is the schematic diagram of a kind of non-crystal oscillator (Crystal-less) system according to the present invention one first embodiment.
Figure 1B is the implementation detail of the clock-generating device shown in Figure 1A in an embodiment.
Fig. 1 C is the data shown in Figure 1B/implementation detail of type sample (Pattern) detection module in an embodiment.
Fig. 2 is the flow chart of a kind of clock generation method according to one embodiment of the invention.
Fig. 3 A to Fig. 3 C is the implementation detail of the clock generation method shown in Fig. 2 in an embodiment.
Fig. 4 A to Fig. 4 B is the implementation detail of the clock generation method shown in Fig. 2 in different embodiments.
Fig. 5 A to Fig. 5 E is the implementation detail of the frequency locking device shown in Figure 1B in different embodiments.
[main element label declaration]
Embodiment
Please refer to Figure 1A, Figure 1A is the schematic diagram of a kind of non-crystal oscillator (Crystal-less) system 100 according to the present invention one first embodiment.According to the present embodiment, non-crystal oscillator system 100 can be applicable to the various devices meeting universal serial bus (Universal Serial Bus, USB) 1.0,1.1,2.0 editions standards, such as various portable electronic devices.As shown in Figure 1A, non-crystal oscillator system 100 comprises clock-generating device 103 and a receiver 105.Clock-generating device 103 is not needing external crystal oscillator and under not producing the situation of above-mentioned side effect, very accurate clock signal clk can be produced according at least one input signal such as input signal D+ and D-(it is one group of differential wave in the present embodiment), use for receiver 105.So, the receiver usefulness that non-crystal oscillator system 100 can reach best by utilizing clock signal clk.
In the present embodiment, the element using clock signal clk to reach best efficiency illustrates for receiver 105.This is not limitation of the present invention just for illustrative purposes.According to the different change case of the present embodiment, it is a transceiver 105-2, a receiving system 105-3 or a receive-transmit system 105-4 that above-mentioned receiver 105 can replace.
Figure 1B is the implementation detail of clock-generating device 103 in an embodiment shown in Figure 1A.As shown in Figure 1B, clock-generating device 103 in non-crystal oscillator system 100 comprises one data/type sample (Pattern) detection module 110, sync pattern detection module 120 and a frequency locking device 130, and wherein frequency locking device 130 comprises at least one hardware circuit.Data/type sample detection module 110 is used for carrying out data/type sample at least one input signal such as input signal D+ and D-and detects to produce restored data RData.In addition, sync pattern detection module 120 is used for then detecting at least one sync pattern in this input signal according to a synchronized model control gauge, and produce the synchronizing signal FREF corresponding to this sync pattern, and frequency locking device 130 is used for carrying out frequency locking with clocking CLK to synchronizing signal FREF, wherein the regular synchronizing signal corresponding to universal series bus standard of this sync pattern of the present embodiment defines.This is not limitation of the present invention just for illustrative purposes.According to the different change case of the present embodiment, above-mentioned sync pattern rule can be changed.Such as: the synchronizing signal according to certain (a bit) standard defines, every T in above-mentioned input signal
sYNC0there is a synchronous package in microsecond (Microsecond), it comprises a sync pattern, and sync pattern detection module 120 detects at least one synchronous package in this input signal according to corresponding sync pattern rule, and produce the synchronizing signal FREF corresponding to this synchronous package, wherein the cycle of synchronizing signal FREF is T
sYNC0microsecond.Again such as: the synchronizing signal according to certain (a bit) standard defines, every T in above-mentioned input signal
sYNC1there is a certain sync pattern in microsecond, and sync pattern detection module 120 detects the sync pattern in this input signal according to corresponding sync pattern rule, and produce the synchronizing signal FREF corresponding to this sync pattern, and wherein the cycle of synchronizing signal FREF is T
sYNC1microsecond.
Fig. 1 C is the data shown in Figure 1B/implementation detail of type sample detection module 110 in an embodiment.As shown in Figure 1 C, data/type sample detection module 110 comprises a digitizer 112, transition and detects (Bit Transition Detection) unit 114, unit interval detection (Unit-timeDetection) unit 116 and one data/type sample decoder (Data/Pattern Decoder) 118, and wherein the present embodiment digitizer 112 comprises multiple D flip-flop (D-Flip-Flop).For brevity, those D flip-flops are denoted as symbol " D " in Fig. 1 C.In addition, symbol Data_In represents above-mentioned at least one input signal (such as: input signal D+ and D-), and symbol Data_Out represents above-mentioned restored data RData.
According to the present embodiment, digitizer 112 is used for carrying out digitlization running to input signal Data_In, to detect this input signal respectively at the logical value representated by multiple time point.Position transition detecting unit 114 is used for carrying out a transition according to those logical values and detects running, to produce a transition testing result.In addition, unit interval detecting unit 116 by utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade a unit bit length.In addition, data/type sample decoder 118 is used for, according to this unit bit length, those logical values are converted to restored data Data_Out (or restored data RData).
According to some embodiment of the present invention, the data shown in Fig. 1 C/type sample detection module 110 can be used as one without reference frequency (Reference-less) receiver, and wherein restored data RData is used as this output without reference frequency receiver.Under this situation, it is a reflector or emission system that the receiver 105 (or above-mentioned transceiver 105-2, receiving system 105-3 or receive-transmit system 105-4) shown in Figure 1A can replace.Although note that the accuracy without reference frequency receiver in these embodiments may lower than the accuracy of the receiver 105 in Figure 1A illustrated embodiment, the framework shown in Fig. 1 C can save cost, this is because its framework is comparatively succinct.Therefore, the framework shown in Fig. 1 C is specially adapted to product such as mouse, keyboard and the toy to cost sensitivity (Cost-sensitive).
Fig. 2 is the flow chart of a kind of clock generation method 900 according to one embodiment of the invention.Clock generation method 900 can be applicable to the non-crystal oscillator system 100 in the middle of any one in each embodiment (and relevant change case) shown in Figure 1A to Fig. 1 C.In addition, clock generation method 900 is by utilizing the clock-generating device 103 shown in the non-crystal oscillator system 100 shown in Figure 1A, Figure 1B, implementing with any one of data/type sample detection module 110 shown in Fig. 1 C.Clock generation method 900 is described as follows:
In step 910, data/type sample detection module 110 carries out data/type sample to above-mentioned at least one input signal such as input signal D+ and D-and detects to produce restored data RData.In implementation, data/type sample detection module 110 can be used on time shaft and carry out data/type sample detection to the digitlization running of this input signal, especially be carried out at high-resolution sampling running on time shaft, such as oversampling (Oversampling) operates and/or utilizes the sampling of multiphase clock to operate.
In step 920, sync pattern detection module 120 according to a synchronized model control gauge then regular at least one sync pattern detected in this input signal of all sync pattern described above, and produces the synchronizing signal FREF corresponding to this sync pattern.In implementation, this sync pattern rule defines corresponding to the synchronizing signal of certain (a bit) communication standard such as universal serial bus 1.0,1.1,2.0 editions standards.
In step 930, frequency locking device 130 couples of synchronizing signal FREF carry out frequency locking with clocking CLK.Especially, frequency locking device 130 can utilize the initial version of a numerically-controlled oscillator (Digitally ControlledOscillator, DCO) clocking CLK.Such as: frequency locking device 130 can utilize the output of this numerically-controlled oscillator as clock signal clk.Again such as: frequency locking device 130 can utilize the derivative signal of the output of this numerically-controlled oscillator as clock signal clk.According to the present embodiment, no matter frequency locking device 130 utilizes the output of this numerically-controlled oscillator as clock signal clk or utilizes the derivative signal of output of this numerically-controlled oscillator as clock signal clk, frequency locking device 130 can detect the difference on the frequency/phase difference between clock signal clk and synchronizing signal FREF, and dynamically adjust the frequency of clock signal clk according to this difference on the frequency/phase difference, with by the integral multiple of the frequency locker of clock signal clk to the frequency of synchronizing signal FREF or the multiple of a rational.
In implementation, step 910, step 920, with each can simultaneously the carrying out at least partially of operate disclosed by step 930, to reach the usefulness of the best.Such as: after a part is carried out in the running of step 910, sync pattern detection module 120 can start the running carrying out step 920.Again such as: after a part is carried out in the running of step 920, frequency locking device 130 can start the running carrying out step 930.In addition, step 910, step 920, can repeatedly carry out with each running disclosed by step 930.
Fig. 3 A to Fig. 3 C is the implementation detail of clock generation method 900 in an embodiment shown in Fig. 2.
Please refer to Fig. 3 A, in step 912, digitizer 112 carries out digitlization running to above-mentioned at least one input signal Data_In, to detect input signal Data_In respectively at the logical value of multiple time point such as representated by above-mentioned multiple time point, the length between the wantonly two adjacent time points wherein in those time points equals a predetermined amount of delay.In implementation, this predetermined amount of delay is less than the contained length of the data of arbitrary on time shaft of input signal Data_In.
In step 914, position transition detecting unit 114 carries out a transition according to those logical values and detects running, and to produce a transition testing result, wherein those transition testing results represent the logical value change between some adjacent bit.
In step 916, unit interval detecting unit 116 and data/type sample decoder 118 carry out data/type sample and decode and operate.As shown in Figure 3A, step 916 comprises the running of step 916A and step 916B.According to the present embodiment, what each disclosed by the step 916A and step 916B operated can carry out, at least partially to reach the usefulness of the best simultaneously.Especially, step 916A and step 916B can carry out abreast.
In step 916A, unit interval detecting unit 116 is by utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade above-mentioned unit bit length, wherein this unit bit length is multiple measured in units of this predetermined amount of delay.Especially, unit interval detecting unit 116 find be consecutively detected in the middle of those logical values non-transition logical value (such as: the logical value that is consecutively detected 0,0 ..., 0}; Again such as: the logical value that is consecutively detected 1,1 ..., 1}) the minimum value of quantity, and utilize this minimum value as the last look of this unit bit length.
In step 916B, those logical values are converted to restored data Data_Out (the restored data RData namely shown in Figure 1B) according to this unit bit length by data/type sample decoder 118.Especially, in the middle of those logical values, data/type sample decoder 118 dynamically judges to correspond to one group of logical value be consecutively detected of a position according to this unit bit length, and retains a logical value in the logical value that this group the is consecutively detected logical value as this in restored data Data_Out.Such as: this logical value can be any one of the logical value that this group is consecutively detected, and wherein data/type sample decoder 118 is consecutively detected a group and identical logical value is judged to be the logical value that this group is consecutively detected.Again such as: this logical value can be the mode of the logical value that this group is consecutively detected, wherein data/type sample decoder 118 can get rid of the abnormal logic value that noise causes, single reverse logic value between the such as two groups non-transition logical values be consecutively detected (such as: logical value 0,0 ... 0}, 1, { 0,0,, the single reverse logic value 1 in 0}}; Again such as: logical value 1,1 ..., 1}, 0,1,1 ..., the single reverse logic value 0 in 1}}).
In implementation, step 912, step 914, with each can simultaneously the carrying out at least partially of operate disclosed by step 916, to reach the usefulness of the best.Such as: after a part is carried out in the running of step 912, position transition detecting unit 114 can start the running carrying out step 914.Again such as: after a part is carried out in the running of step 914, unit interval detecting unit 116 and data/type sample decoder 118 can start the running carrying out step 916, carry out the running of step 916A and step 916B especially respectively.In addition, step 912, step 914, can repeatedly carry out with each running disclosed by step 916.
Synchronizing signal according to certain (a bit) standard defines, and in above-mentioned input signal Data_In, transfer of data all can comprise a certain sync pattern.The unit interval detecting unit 116 of the present embodiment can upgrade above-mentioned unit bit length according to this sync pattern, and its correlative detail please refer to further illustrating of Fig. 3 B.
In step 917, unit interval detecting unit 116 checks whether and this sync pattern detected.When this sync pattern being detected, enter step 918; Otherwise, reenter step 917.
In step 918, unit interval detecting unit 116 upgrades this unit bit length.Especially, unit interval detecting unit 116 is by utilizing those transition testing results described in step 914, { Sync} dynamically to judge unit bit length, and upgrades this unit bit length stored in a buffer to analyze the position corresponding to sync pattern in the middle of those logical values.For example, under a situation sync pattern 010 being detected, unit interval detecting unit 116 can analyze sync pattern 010 each position 0,1,0}, and find correspond respectively to each position { quantity { N of the logical value of 0,1,0}
syncminimum value N
sync_Min, and utilize minimum value N
sync_Minas the last look of this unit bit length.According to different embodiments, all embodiments as shown in Figure 3 B or its change case, this buffer can be arranged within unit interval detecting unit 116, within data/type sample detection module 110 or within clock-generating device 103.
In step 919, the last look of this unit bit length provides and gives data/type sample decoder 118 by unit interval detecting unit 116.
In implementation, step 917, step 918, with each can simultaneously the carrying out at least partially of operate disclosed by step 919, to reach the usefulness of the best.Such as: after a part is carried out in the running of step 917, as long as data/type sample decoder 118 needs this unit bit length, unit interval detecting unit 116 can start the running carrying out step 919.Again such as: when entering step 918, before this unit bit length of renewal, as long as data/type sample decoder 118 needs this unit bit length, unit interval detecting unit 116 can start the running carrying out step 919.
As shown in Figure 3 C, by utilizing the data of step 916/type sample decoding running, data/type sample detection module 110 can by data D1 contained for input signal Data_In, D2, D3, be decoded as its each position { D1-1 with D4 respectively, D1-2, D1-3}, { D2-1, D2-2, D2-3}, D3-1, D3-2}, with { D4-1}, wherein { D1-1, D1-2, D1-3, D2-1, D2-2, D2-3, D3-1, each in D3-2, D4-1} is the data of a position.Such as: unit interval detecting unit 116 carries out analysis running disclosed by step 916A to judge that this unit bit length is 8 times of this predetermined amount of delay, and this representation unit time detecting unit 116 judges that { length of Sync} on time shaft is 8 times of this predetermined amount of delay for each position of sync pattern.Under data/type sample decoder 118 judges that the length of data D1 on time shaft is the situation of 25 times of this predetermined amount of delay, the logical value corresponding to data D1 is converted to 3 position { D1-1 of data D1 by data/type sample decoder 118, D1-2, D1-3}, this is because 25 divided by 8 gained quotient be 3 closest to integer.Similarly, data/type sample decoder 118 can by corresponding to data D2, D3, be converted to 3 positions of data D2 with the logical value of D4 { 2 positions of D2-1, D2-2, D2-3}, data D3 { D3-1, D3-2}, 1 position { D4-1} with data D4.So those logical values are converted to restored data Data_Out according to this unit bit length by data/type sample decoder 118.
Fig. 4 A to Fig. 4 B is the implementation detail about running disclosed in step 910 in the middle of different embodiments of the clock generation method 900 shown in Fig. 2.
According to the embodiment shown in Fig. 4 A, digitizer 112 is according to the combination of one group of multi-phase clock signal, an oversampling clock signal, maybe this group multi-phase clock signal and this oversampling clock signal, carry out those digitlization runnings to above-mentioned at least one input signal Data_In, the spacing of wantonly two neighbor finger on time shaft wherein shown in Fig. 4 A represents this predetermined amount of delay.In implementation, digitizer 112 can utilize at least one group of delay cell to produce this group multi-phase clock signal and/or this oversampling clock signal.Such as: this predetermined amount of delay equals the retardation of a delay cell.Again such as: this predetermined amount of delay equals the retardation of the delay cell of a certain predetermined quantity.
According to the embodiment shown in Fig. 4 B, digitizer 112 comprises a time-to-digit converter (Time-to-Digital Converter, TDC) 400, and wherein time-to-digit converter 400 comprises time gate 410 and a Mixed Delay line 420.Time-to-digit converter 400 is used for carrying out time figure conversion to above-mentioned at least one input signal Data_In, to carry out those digitlization runnings.Especially, time-to-digit converter 400 can measure the time interval between two edges of at least one echo signal.For example, the pretreatment unit in digitizer 112 can utilize two rising edges in echo signal (such as a part of input signal Data_In) to trigger commencing signal S respectively
sTARTwith end signal S
sTOP, make commencing signal S
sTARTtime point in first rising edge rises to high level, and makes end signal S
sTOPtime point in second rising edge rises to high level.So digitizer 112 utilizes time gate 410 and Mixed Delay line 420 that the time interval between these two rising edges is converted to digital code { D
1, D
2..., D
16.Under typical situation, numerical digit code { D
1, D
2..., D
16in certain one digit number such as D
xthe logical value of (X represents a certain positive integer of 1 to 16) equals 1, and the logical value of all the other figure places is 0.Size due to X corresponds to the length of this time interval, therefore digital code { D
1, D
2..., D
16this detected time interval can be represented.Note that digitizer 112 can utilize replacement (Reset) signal S
rESETreset Mixed Delay line 420, to re-start the measurement running of above exposure.
Fig. 5 A to Fig. 5 E is the implementation detail of the frequency locking device 130 shown in Figure 1B in different embodiments.
According to the embodiment shown in Fig. 5 A, frequency locking device 130 comprise frequency detector 512, low pass filter 514L, with numerically-controlled oscillator 516, wherein frequency locking device 130 utilizes the output of numerically-controlled oscillator 516 as clock signal clk.Frequency detector 512 detects the difference on the frequency between clock signal clk and synchronizing signal FREF, and exports corresponding frequency difference signal, and low pass filter 514L carries out low-pass filtering to produce the input of numerically-controlled oscillator 516 to this frequency difference signal.So, frequency locking device 130 by the frequency locker of clock signal clk to the frequency of synchronizing signal FREF.
According to the embodiment shown in Fig. 5 B, frequency locking device 130 comprise frequency detector 512, binary search unit 514S, with numerically-controlled oscillator 516, wherein binary search unit 514S implements by utilizing continuous approximation buffer (Successive Approximation Register, SAR) or other element.The present embodiment is the change case of Fig. 5 A illustrated embodiment.Binary search unit 514S can carry out binary search running with the input producing numerically-controlled oscillator 516 to this frequency difference signal.It is no longer repeated for the present embodiment and the similar part of previous embodiment.
According to the embodiment shown in Fig. 5 C, frequency locking device 130 comprise time-to-digit converter 522, decoder 524, multiplexer 526M, multiple buffer stage 526R, with reverser 526V, wherein frequency locking device 130 possesses at least one circular type shaker (Ring-based Oscillator), its comprise buffer stage 526R at least partially, multiplexer 526M, with reverser 526V.Frequency locking device 130 utilizes time-to-digit converter 522 to carry out time figure conversion to produce at least one digital code according to the output of buffer stage 526R to synchronizing signal FREF, and decoder 524 decodes to produce a selection signal to this digital code, and multiplexer 526M carries out multiplex's selection, dynamically to adjust the frequency of clock signal clk according to the outgoing route of this selection signal to multiple buffer stages of above-mentioned at least one circular type shaker.It is no longer repeated for the present embodiment and the similar part of foregoing individual embodiments/change case.
According to the change case of the present embodiment, the leftmost side input of the somewhere such as buffer stage 526R of this circular type shaker can arrange at least one electric capacity, to finely tune the frequency of clock signal clk.It is no longer repeated with the similar part of foregoing individual embodiments/change case for this change case.
According to the embodiment shown in Fig. 5 D, except above-mentioned decoder 524, multiplexer 526M, buffer stage 526R, with reverser 526V, frequency locking device 130 also comprises multiplexer 521M and 522M, phase detectors 532 and low pass filter 534, wherein frequency locking device 130 possesses at least one circular type shaker, its comprise buffer stage 526R at least partially, multiplexer 521M and 526M and reverser 526V.Phase detectors 532 detect the phase difference between the output of multiplexer 522M and synchronizing signal FREF, and export corresponding phase signal, and low pass filter 534 carries out low-pass filtering to produce the selection signal of multiplexer 522M to this phase signal, the outgoing route at least partially of multiplexer 522M to buffer stage 526R is made to carry out multiplex's selection.In addition, the selection signal that decoder 524 pairs of low pass filters 534 produce decodes to produce the selection signal of multiplexer 526M.So frequency locking device 130 utilizes the outgoing route of multiplexer 526M to multiple buffer stages of above-mentioned at least one circular type shaker to carry out multiplex's selection, dynamically to adjust the frequency of clock signal clk.It is no longer repeated for the present embodiment and the similar part of foregoing individual embodiments/change case.
According to the change case of the present embodiment, the leftmost side input of the somewhere such as buffer stage 526R of this circular type shaker can arrange at least one electric capacity, to finely tune the frequency of clock signal clk.It is no longer repeated with the similar part of foregoing individual embodiments/change case for this change case.
According to the embodiment shown in Fig. 5 E, frequency locking device 130 comprise numerically-controlled oscillator 542D, counter 542C, arithmetical unit 542A, decoder 544, programmable divider (ProgrammableDivider) 546, with phase interpolation unit 548, wherein arithmetical unit 542A can utilize subtracter to implement, and the frequency of the output of numerically-controlled oscillator 542D can far above the frequency of synchronizing signal FREF.Frequency locking device 130 utilizes the activation terminal EN of synchronizing signal FREF control counter 542C, operates the counting of the output of numerically-controlled oscillator 542D with optionally activation counter 542C.Frequency locking device 130 utilizes arithmetical unit 542A to compare the count results of counter 542C and a referential data Vref to produce comparative result, and decoder 544 compared result carries out decoding to produce decoded result.In addition, programmable divider 546 carries out frequency elimination to produce frequency elimination result according to the same output of decoded result to numerically-controlled oscillator 542D, and wherein the parameter of the programmable divider 546 of the present embodiment can be adjusted, to finely tune frequency elimination result.In addition, frequency locking device 130 can utilize phase interpolation unit 548 pairs of frequency elimination results to finely tune with clocking CLK.It is no longer repeated for the present embodiment and the similar part of foregoing individual embodiments/change case.
According to the change case of the present embodiment, do not need to arrange phase interpolation unit 548 in frequency locking device 130, wherein frequency locking device 130 utilizes above-mentioned frequency elimination result as clock signal clk.It is no longer repeated with the similar part of foregoing individual embodiments/change case for this change case.
According to some embodiment (such as: some change case of Fig. 5 E illustrated embodiment), above-mentioned numerically-controlled oscillator (such as: the numerically-controlled oscillator 542D shown in Fig. 5 E) replaceable is general oscillator.It is no longer repeated for these embodiments and the similar part of foregoing individual embodiments/change case.
One of benefit of the present invention is, clock generation method of the present invention, without reference frequency receiver, can not need external crystal oscillator and the situation not producing above-mentioned side effect is issued to best receiver usefulness with non-crystal oscillator system.Even if under the situation that the initial frequency errors at transmission channel two ends is very large, the framework realized according to the present invention still properly can carry out reception running.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the claims in the present invention scope change and modify, and all should belong to covering scope of the present invention.
Claims (18)
1. a clock generation method, be used for generation one clock signal for one receiver/transceiver/receiving system/receive-transmit system use, this clock generation method includes:
Carry out data/type sample at least one input signal to detect to produce restored data;
Then detect at least one sync pattern in this input signal according to a synchronized model control gauge, and produce the synchronizing signal corresponding to this sync pattern; And
Frequency locking is carried out to produce this clock signal to this synchronizing signal;
Wherein carry out data/type sample detection to this at least one input signal also to comprise with the step producing this restored data:
Carry out digitlization running to this input signal, to detect this input signal respectively at the logical value representated by multiple time point, the length between the wantonly two adjacent time points wherein in the plurality of time point equals a predetermined amount of delay;
Carry out a transition according to those logical values and detect running, to produce a transition testing result;
By utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade a unit bit length, wherein this unit bit length is multiple measured in units of this predetermined amount of delay; And
According to this unit bit length, those logical values are converted to this restored data.
2. clock generation method according to claim 1, wherein this predetermined amount of delay is less than the contained length of the data of arbitrary on time shaft of this input signal.
3. clock generation method according to claim 2, wherein carries out data/type sample detection to this at least one input signal and also comprises with the step producing this restored data:
According to the combination of one group of multi-phase clock signal, an oversampling clock signal, maybe this group multi-phase clock signal and this oversampling clock signal, digitlization running is carried out to this at least one input signal.
4. clock generation method according to claim 2, wherein carries out data/type sample detection to this at least one input signal and also comprises with the step producing this restored data:
A time-to-digit converter is utilized to carry out time figure conversion to this at least one input signal, to carry out digitlization running.
5. clock generation method according to claim 1, this wherein analyzing those logical values is at least partially dynamically to judge/to upgrade that the step of this unit bit length also comprises:
Find the minimum value of the quantity of the non-transition logical value be consecutively detected in the middle of those logical values, and utilize this minimum value as the last look of this unit bit length.
6. clock generation method according to claim 1, wherein also comprises the step that those logical values are converted to this restored data according to this unit bit length:
In the middle of those logical values, dynamically judge to correspond to one group of logical value be consecutively detected of a position according to this unit bit length, and retain the logical value of the logical value in the logical value that this group is consecutively detected as this in this restored data.
7. clock generation method according to claim 6, wherein this logical value is the mode of the logical value that this group is consecutively detected.
8. clock generation method according to claim 1, wherein carries out frequency locking to this synchronizing signal and also comprises with the step producing this clock signal:
Detect the difference on the frequency/phase difference between this clock signal and this synchronizing signal, and dynamically adjust the frequency of this clock signal according to this difference on the frequency/phase difference.
9. clock generation method according to claim 1, wherein carries out frequency locking to this synchronizing signal and also comprises with the step producing this clock signal:
A numerically-controlled oscillator is utilized to produce the initial version of this clock signal.
10. clock generation method according to claim 1, wherein carries out frequency locking to this synchronizing signal and also comprises with the step producing this clock signal:
A time-to-digit converter is utilized to carry out time figure conversion to produce at least one digital code to this synchronizing signal;
Decode to produce a selection signal to this digital code; And
Multiplex's selection is carried out, dynamically to adjust the frequency of this clock signal according to the outgoing route of this selection signal to multiple buffer stages of a circular type shaker.
11. 1 kinds without reference frequency receiver, be used for carrying out data/type sample at least one input signal and detect to produce restored data, this includes without reference frequency receiver:
One digitizer, is used for carrying out digitlization running to this input signal, and to detect this input signal respectively at the logical value representated by multiple time point, the length between the wantonly two adjacent time points wherein in the plurality of time point equals a predetermined amount of delay;
A transition detecting unit, is used for carrying out a transition according to those logical values and detects running, to produce a transition testing result;
One unit interval detecting unit, is used for by utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade a unit bit length, wherein this unit bit length is multiple measured in units of this predetermined amount of delay; And
One data/type sample decoder, is used for, according to this unit bit length, those logical values are converted to this restored data.
12. is according to claim 11 without reference frequency receiver, and wherein this predetermined amount of delay is less than the contained length of the data of arbitrary on time shaft of this input signal.
13. is according to claim 12 without reference frequency receiver, wherein this digitizer is according to the combination of one group of multi-phase clock signal, an oversampling clock signal, maybe this group multi-phase clock signal and this oversampling clock signal, carries out those digitlization runnings to this at least one input signal.
14. is according to claim 12 without reference frequency receiver, and wherein this digitizer includes:
One time-to-digit converter, is used for carrying out time figure conversion to this at least one input signal, to carry out those digitlization runnings.
15. is according to claim 11 without reference frequency receiver, and wherein this unit interval detecting unit finds the minimum value of the quantity of the non-transition logical value be consecutively detected in the middle of those logical values, and utilizes this minimum value as the last look of this unit bit length.
16. is according to claim 11 without reference frequency receiver, wherein in the middle of those logical values, these data/type sample decoder dynamically judges to correspond to one group of logical value be consecutively detected of a position according to this unit bit length, and retains the logical value of the logical value in the logical value that this group is consecutively detected as this in this restored data.
17. 1 kinds of non-crystal oscillator systems, be used for generation one clock signal for one receiver/transceiver/receiving system/receive-transmit system use, this non-crystal oscillator system includes:
One data/type sample detection module, is used for carrying out data/type sample at least one input signal and detects to produce restored data;
One sync pattern detection module, is used for then detecting at least one sync pattern in this input signal according to a synchronized model control gauge, and produces the synchronizing signal corresponding to this sync pattern; And
One frequency locking device, be used for carrying out frequency locking to produce this clock signal to this synchronizing signal, wherein this frequency locking device comprises at least one hardware circuit;
Wherein these data/type sample detection module includes:
One digitizer, is used for carrying out digitlization running to this input signal, and to detect this input signal respectively at the logical value representated by multiple time point, the length between the wantonly two adjacent time points wherein in the plurality of time point equals a predetermined amount of delay;
A transition detecting unit, is used for carrying out a transition according to those logical values and detects running, to produce a transition testing result;
One unit interval detecting unit, is used for by utilizing those transition testing results, analyze those logical values at least partially dynamically to judge/to upgrade a unit bit length, wherein this unit bit length is multiple measured in units of this predetermined amount of delay; And
One data/type sample decoder, is used for, according to this unit bit length, those logical values are converted to this restored data.
18. non-crystal oscillator systems according to claim 17, wherein this predetermined amount of delay is less than the contained length of the data of arbitrary on time shaft of this input signal.
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| DE102015104672A1 (en) * | 2015-03-26 | 2016-09-29 | Intel IP Corporation | An apparatus and method for providing oscillator signals |
| US10097190B2 (en) * | 2016-12-19 | 2018-10-09 | Futurewei Technologies, Inc. | Wide capture range reference-less frequency detector |
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