CN102760759B - A kind of semiconductor power device - Google Patents
A kind of semiconductor power device Download PDFInfo
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- CN102760759B CN102760759B CN201210073789.4A CN201210073789A CN102760759B CN 102760759 B CN102760759 B CN 102760759B CN 201210073789 A CN201210073789 A CN 201210073789A CN 102760759 B CN102760759 B CN 102760759B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 173
- 230000004888 barrier function Effects 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 7
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims description 3
- ILRRQNADMUWWFW-UHFFFAOYSA-K aluminium phosphate Chemical compound O1[Al]2OP1(=O)O2 ILRRQNADMUWWFW-UHFFFAOYSA-K 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 2
- 238000005036 potential barrier Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910003811 SiGeC Inorganic materials 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 206010011469 Crying Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
The invention provides a kind of semiconductor power device, comprise first conduction type second semiconductor layer on the first conduction type first semiconductor layer and surface thereof, be arranged at the second conduction type first well region in the first conduction type second semiconductor layer and the second well region; Be arranged at the first conduction type first source region in first, second well region subregion and the second source region respectively; Part covers the first insulating barrier of source region and well region, be arranged at the polysilicon layer on the first insulating barrier, cover the second insulating barrier of polysilicon layer and fractional source regions, cover the first metal layer of source region, well region and the second insulating barrier, be arranged at the second conduction type the 3rd semiconductor layer at the first conduction type first semiconductor layer back side and second metal level at the back side thereof, the energy gap of described first conduction type second semiconductor layer is greater than the energy gap of the first conduction type first semiconductor layer.Semiconductor power device of the present invention, can effectively suppress on-state loss and withstand voltage between contradiction.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of semiconductor power device.
Background technology
High frequency, height is withstand voltage, low-loss is semiconductor power device always important performance are pursued, and semiconductor power device combines ambipolar and advantage that is MOS type power device, achieve well compromise between in frequency, withstand voltage, loss etc.The development of power electronics industry is also more and more higher to the performance requirement of semiconductor power device.In order to reduce the on-state voltage drop of semiconductor power device, thus reduction on-state loss, introduce a kind of structure of crying barrier layer, n raceway groove IGBT as shown in Figure 1, comprise barrier layer 103, drift region 104, well region 102 and 112, the doping content on described barrier layer 103 is higher than the doping content of drift region 104, due to the difference of doping content, many sons between barrier layer 103 and drift region 104 diffuse to form a potential barrier, this potential barrier has barrier effect to the few son stored in barrier layer 103, thus few son is not easy to be collected by reverse-biased trap-drift region knot, improve the carrier concentration near device surface, enhance the conductance modulation effect of near surface, effectively reduce on-state voltage drop, thus reduction on-state loss.The way on this few sub-barrier layer is generally at whole device surface or impurity that selectively regional diffusion is identical with drift layer, forms the doped region of certain thickness higher concentration.
But, the method existing defects on this traditional fabrication barrier layer.Particularly, because this barrier layer is that the doped region utilizing near surface relatively high is formed, when device is in cut-off state, reverse-biased trap-drift region knot depletion layer extends, and theoretical according to pn knot, doping content is higher, more be unfavorable for the extension of depletion layer, thus reduce the withstand voltage of device.A kind of existing solution is adopt the spacing reducing unit's bag, thus the distance reducing well region is withstand voltage to ensure, then concerning whole device, will certainly increase the quantity of unit's bag, thus bring the negative effect of two aspects: on the one hand, first bag quantity increases, mean that the ratio that well region area accounts for increases, thus the area collecting minority carrier increases, and reduces conductance modulation effect, weakens the effect on barrier layer; On the other hand, the increase of first bag quantity causes gully density to increase, and the size of gully density is directly proportional to short circuit current size, increases gully density and means that short circuit current increases, and the self-current limiting capacity of such device weakens, and reduces the robustness of device.
Summary of the invention
The present invention is the technical problem solving contradiction between device on-state loss and device withstand voltage in prior art, provides a kind of novel semi-conductor power device.
The object of the invention is to be achieved through the following technical solutions:
A kind of semiconductor power device, comprise the first conduction type first semiconductor layer, be positioned at the first conduction type second semiconductor layer of the first conduction type first semiconductor layer surface, be arranged at the second conduction type first well region in the first conduction type second semiconductor layer, and the second conduction type second well region separated with described second conduction type first well region, be arranged at the first conduction type first source region in described second conduction type first well region subregion, and be arranged at the first conduction type second source region in described second conduction type second well region subregion, to be arranged on the first conduction type second semiconductor layer and part covers the first source region, second source region, first insulating barrier of the first well region and the second well region, be arranged at the polysilicon layer on the first insulating barrier, to be arranged on the first conduction type second semiconductor layer and to cover second insulating barrier in polysilicon layer and part first source region and the second source region, to be arranged on the first conduction type second semiconductor layer and to cover the first source region, second source region, first well region, the first metal layer of the second well region and the second insulating barrier, be arranged at the second conduction type the 3rd semiconductor layer at the first conduction type first semiconductor layer back side, and cover second metal level at the second conduction type the 3rd semiconductor layer back side, the energy gap of described first conduction type second semiconductor layer is greater than the energy gap of the first conduction type first semiconductor layer.
Semiconductor power device provided by the invention, the energy gap of described first conduction type second semiconductor layer is greater than the energy gap of the first conduction type first semiconductor layer, like this, in doping content identical or the second semiconductor layer doped concentration is smaller time, the energy level of many sons almost maintains an equal level, and the energy level of few son exists bending, this is bent to form the potential barrier of a few son, when semiconductor power device conducting, this potential barrier has inhibition to the few son spread near trap from drift region, thus can effectively suppress trap-drift region to become a partner the collection of few son, improve the carrier concentration of semiconductor power device near surface, reduce on-state loss, in turn ensure that the withstand voltage unaffected of device simultaneously.
Accompanying drawing explanation
Fig. 1 is the n raceway groove IGBT structure schematic diagram that prior art provides.
Fig. 2 is the n raceway groove IGBT structure schematic diagram that first embodiment of the invention provides.
Fig. 3 is the n raceway groove IGBT structure schematic diagram that second embodiment of the invention provides.
Fig. 4 is n raceway groove IGBT barrier layer and drift region first band structure schematic diagram in the embodiment of the present invention.
Fig. 5 is n raceway groove IGBT barrier layer and drift region second band structure schematic diagram in the embodiment of the present invention.
Fig. 6 is p raceway groove IGBT barrier layer and drift region first band structure schematic diagram in the embodiment of the present invention.
Fig. 7 is p raceway groove IGBT barrier layer and drift region second band structure schematic diagram in the embodiment of the present invention.
Embodiment
In order to make technical problem solved by the invention, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
A kind of semiconductor power device, comprise the first conduction type first semiconductor layer, be positioned at the first conduction type second semiconductor layer of the first conduction type first semiconductor layer surface, be arranged at the second conduction type first well region in the first conduction type second semiconductor layer, and the second conduction type second well region separated with described second conduction type first well region, be arranged at the first conduction type first source region in described second conduction type first well region subregion, and be arranged at the first conduction type second source region in described second conduction type second well region subregion, to be arranged on the first conduction type second semiconductor layer and part covers the first source region, second source region, first insulating barrier of the first well region and the second well region, be arranged at the polysilicon layer on the first insulating barrier, to be arranged on the first conduction type second semiconductor layer and to cover second insulating barrier in polysilicon layer and part first source region and the second source region, to be arranged on the first conduction type second semiconductor layer and to cover the first source region, second source region, first well region, the first metal layer of the second well region and the second insulating barrier, be arranged at the second conduction type the 3rd semiconductor layer at the first conduction type first semiconductor layer back side, and cover second metal level at the second conduction type the 3rd semiconductor layer back side, the energy gap of described first conduction type second semiconductor layer is greater than the energy gap of the first conduction type first semiconductor layer.
Semiconductor power device provided by the invention, the energy gap of described first conduction type second semiconductor layer is greater than the energy gap of the first conduction type first semiconductor layer, like this, in doping content identical or the second semiconductor layer doped concentration is smaller time, the energy level of many sons almost maintains an equal level, and the energy level of few son exists bending, this is bent to form the potential barrier of a few son, when semiconductor power device conducting, this potential barrier has inhibition to the few son spread near trap from drift region, thus can effectively suppress trap-drift region to become a partner the collection of few son, improve the carrier concentration of semiconductor power device near surface, reduce on-state loss, in turn ensure that the withstand voltage unaffected of device simultaneously.
As the semiconductor power device embodiment that the first is concrete, please refer to shown in Fig. 2, this semiconductor power device comprises the first conduction type first semiconductor layer 204, be positioned at first conduction type second semiconductor layer 203 on the first conduction type first semiconductor layer 204 surface, be arranged at the second conduction type first well region 2021 in the first conduction type second semiconductor layer 203, and the second conduction type second well region 2022 separated with described second conduction type first well region 2021, be arranged at the first conduction type first source region 2011 in described second conduction type first well region 2021 subregion, and be arranged at the first conduction type second source region 2012 in described second conduction type second well region 2022 subregion, to be arranged on the first conduction type second semiconductor layer 203 and part covers the first source region 2011, second source region 2012, first insulating barrier 207 of the first well region 2021 and the second well region 2022, described first conduction type second semiconductor layer 203 is surrounded on the first well region 2021 and the second well region 2022, and the first conduction type first semiconductor layer 204 is contacted with the first insulating barrier 207, namely the first conduction type second semiconductor layer 203 is separated into two parts by the first conduction type first semiconductor layer 204, first well region 2021 is arranged in a part of the first conduction type second semiconductor layer 203, second well region 2022 is arranged in another part of the first conduction type second semiconductor layer 203, be arranged at the polysilicon layer 209 on the first insulating barrier 207, to be arranged on the first conduction type second semiconductor layer 203 and to cover second insulating barrier 211 in polysilicon layer 209 and part first source region 2011 and the second source region 2012, to be arranged on the first conduction type second semiconductor layer 203 and to cover the first source region 2011, second source region 2012, first well region 2021, the first metal layer 208 of the second well region 2022 and the second insulating barrier 211, be arranged at the second conduction type the 3rd semiconductor layer 206 at first conduction type first semiconductor layer 204 back side, and cover second metal level 210 at the second conduction type the 3rd semiconductor layer 206 back side, the energy gap of described first conduction type second semiconductor layer 203 is greater than the energy gap of the first conduction type first semiconductor layer 204.Wherein, described second conduction type the 3rd semiconductor layer 206 is as the collector electrode of semiconductor power device in the present embodiment, described first conduction type first semiconductor layer 204 is as drift region, described first conduction type second semiconductor layer 203 is as barrier layer, described the first metal layer 208 is as emitter, and described polysilicon layer 209 is as gate pole.
As the semiconductor power device embodiment that the second is concrete, please refer to shown in Fig. 3, this semiconductor power device comprises the first conduction type first semiconductor layer 304, be positioned at first conduction type second semiconductor layer 303 on the first conduction type first semiconductor layer 304 surface, be arranged at the second conduction type first well region 3021 in the first conduction type second semiconductor layer 303, and the second conduction type second well region 3022 separated with described second conduction type first well region 3021, be arranged at the first conduction type first source region 3011 in described second conduction type first well region 3021 subregion, and be arranged at the first conduction type second source region 3012 in described second conduction type second well region 3022 subregion, to be arranged on the first conduction type second semiconductor layer 303 and part covers the first insulating barrier 307 of the first source region 3012, first, source region 3011, second well region 3021 and the second well region 3022, described first conduction type second semiconductor layer 303 is surrounded on the first well region 3021 and the second well region 3022, and the first conduction type first semiconductor layer 304 and the first insulating barrier 307 is separated, be arranged at the polysilicon layer 309 on the first insulating barrier 307, to be arranged on the first conduction type second semiconductor layer 303 and to cover second insulating barrier 311 in polysilicon layer 309 and part first source region 3011 and the second source region 3012, to be arranged on the first conduction type second semiconductor layer 303 and to cover the first source region 3011, second source region 3012, first well region 3021, the first metal layer 308 of the second well region 3022 and the second insulating barrier 311, be arranged at the second conduction type the 3rd semiconductor layer 306 at first conduction type first semiconductor layer 304 back side, and cover second metal level 310 at the second conduction type the 3rd semiconductor layer 306 back side, the energy gap of described first conduction type second semiconductor layer 303 is greater than the energy gap of the first conduction type first semiconductor layer 304.Wherein, described second conduction type the 3rd semiconductor layer 306 is as the collector electrode of semiconductor power device in the present embodiment, described first conduction type first semiconductor layer 304 is as drift region, described first conduction type second semiconductor layer 303 is as barrier layer, described the first metal layer 308 is as emitter, and described polysilicon layer 309 is as gate pole.
As concrete execution mode, the doping content of described first conduction type second semiconductor layer is less than or equal to the doping content of the first conduction type first semiconductor layer; As specific embodiment, the material of described doping is phosphorus.Particularly, when the first conduction type second semiconductor layer (barrier layer) is identical with the first conduction type first semiconductor layer (drift region) both sides doping content:
For n raceway groove IGBT, please refer to formation band structure schematic diagram as shown in Figure 4 and Figure 5; Wherein, described Ev is valence band, and Ef is Fermi level, and Ec is conduction band.In the situation shown in Fig. 4, the conduction band of described barrier layer and drift region almost maintains an equal level, the top of valence band on barrier layer is then lower than drift region, like this, the electronics of conduction band can flow to drift region from barrier layer easily, and the few sub-hole of drift region must pass over a potential barrier just can enter in barrier layer, therefore this hole blocking layer can flow to the first conduction type second semiconductor layer (barrier layer) from the first conduction type first semiconductor layer (drift region) by blocking hole, thus restrained effectively less sub-hole by well region-drift region knot collection, enhance the minority carrier density of IGBT near surface, reduce conduction voltage drop, thus reduce the on-state loss of semiconductor power device.For the situation shown in Fig. 5, higher than at the bottom of the conduction band of drift region at the bottom of the conduction band on barrier layer, Fermi level maintains an equal level, but electronics still has the trend trended towards to drift region diffusion, is conducive to strengthening electronic current during conducting; Simultaneously, the top of valence band on barrier layer is equally lower than drift region, form the potential barrier in hole, few sub-hole is suppressed to be collected by well region-drift region knot from drift region to barrier layer diffusion, effectively improve the minority carrier density of IGBT near surface, reduce conduction voltage drop, thus reduce the on-state loss of semiconductor power device.This potential barrier due to hole causes due to the difference that energy gap is inconsistent, energy level itself exists, be not that the carrier diffusion caused due to doped in concentrations profiled produces, therefore, do not need the doping content of hole blocking layer higher than drift region, thus the withstand voltage of device can not be reduced; On the contrary, because the semi-conducting material energy gap of this hole blocking layer is larger than the semi-conducting material energy gap of drift region, its breakdown electric field is corresponding also large, thus withstand voltage high all the better.For the situation shown in Fig. 5, the doping content of hole blocking layer also can be lower than drift region, thus be also conducive to improving the withstand voltage of device.
For p raceway groove IGBT, please refer to formation band structure schematic diagram as shown in Figure 6 and Figure 7; Wherein, described Ev is valence band, and Ef is Fermi level, and Ec is conduction band.The same with n raceway groove IGBT, in the situation shown in Fig. 6, because barrier layer is relative with the valence band on both sides, drift region fair, hole can be easy to move to drift region from sub-barrier layer less.For electronics, higher than drift region at the bottom of the conduction band on few sub-barrier layer, therefore the electronics of drift region must pass over certain potential barrier and just can enter less sub-barrier layer, namely the electron affinity energy of described first conduction type second semiconductor layer is less than the electron affinity energy of the first conduction type first semiconductor layer, electronics is not allowed to change places from the first conduction type first semiconductor layer (drift region) and is flowed to the first conduction type second semiconductor layer (barrier layer), the effective like this carrier concentration enhancing device surface, thus the forward voltage drop and the loss that reduce device.For the situation shown in Fig. 7, the top of valence band on few sub-barrier layer is lower than drift region top of valence band, higher than at the bottom of the conduction band of drift region at the bottom of conduction band, but hole still has from sub-barrier layer diffusion less to the trend of drift region, be more conducive to flowing through of hole current, and electronics flows to less sub-barrier layer from drift region need to cross certain potential barrier, effectively enhance the carrier concentration of IGBT near surface, reduce on-state voltage drop and loss.Equally, the energy gap due to sub-barrier layer is less greater than the energy gap of drift region or doping content can be lower, thus ensures that the withstand voltage of device can not decline.
As concrete execution mode, the doping content of described first conduction type second semiconductor layer is 5e12/cm
3-1e15/cm
3, the doping content of described first conduction type first semiconductor layer is 5e12/cm
3-1e15/cm
3.Particularly, in the semiconductor power device embodiment that the first is concrete, the doping content of described first conduction type second semiconductor layer 203 is 1e14/cm
3, the doping content of described first conduction type first semiconductor layer 204 is 1e14/cm
3; Meanwhile, the doping content in described first source region 2011 and the second source region 2012 is 2e19/cm
3, the doping content in described first well region 2021 and the second source region 2022 is 1e18/cm
3, the doping content of described second conduction type the 3rd semiconductor layer 206 is 5e
17/ cm
3.Particularly, in the semiconductor power device embodiment that the second is concrete, the doping content of described first conduction type second semiconductor layer 303 is 6e13/cm
3, the doping content of described first conduction type first semiconductor layer 304 is 8e13/cm
3; Meanwhile, the doping content in described first source region 3011 and the second source region 3012 is 2e19/cm
3, the doping content in described first well region 3021 and the second source region 3022 is 1e18/cm
3, the doping content of described second conduction type the 3rd semiconductor layer 306 is 5e17/cm
3.
As concrete execution mode, the energy gap of described first conduction type second semiconductor layer is 1-5eV, the energy gap of described first conduction type first semiconductor layer is 0.1-3eV, thus suitable semi-conducting material can be selected easily, ensure that barrier layer energy gap is greater than drift region energy gap, the few son of effective stop is collected by trap-drift region knot, better realizes technique effect of the present invention.
As concrete execution mode, the material of described first conduction type second semiconductor layer is selected from the one in silicon (Si), carborundum (SiC), aluminum phosphate (AlP), indium phosphide (InP), aluminium arsenide (AlAs) or the semi-conducting material that other energy gap is larger.
As concrete execution mode, the material of described first conduction type first semiconductor layer is selected from germanium (Ge), SiGe (Si
1-xge
x), one in carbon SiGe (SiGeC), or the semi-conducting material that other energy gap is less.
As specific embodiment, in the first semiconductor power device, the material of described first conduction type first semiconductor layer 204 and the second conduction type the 3rd semiconductor layer 206 is Si
1-xge
x, the material in described first source region, conduction type second semiconductor layer 203, first well region 3021, second source region 3022, first 3011 and the second source region 3012 is Si.
As concrete execution mode, in semiconductor power device provided by the invention, described first conduction type is N-type, and the second conduction type is P type, specifically please refer to the first semiconductor power device shown in Fig. 2 and Fig. 3 and the second semiconductor power device; Certainly, those skilled in the art are on the basis of aforementioned IGBT structure, and the first conduction type and the second conduction type can also be exchanged, namely described first conduction type is P type, and the second conduction type is N-type.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a semiconductor power device, it is characterized in that, comprise the first conduction type first semiconductor layer, be positioned at the first conduction type second semiconductor layer of the first conduction type first semiconductor layer surface, be arranged at the second conduction type first well region in the first conduction type second semiconductor layer, and the second conduction type second well region separated with described second conduction type first well region, be arranged at the first conduction type first source region in described second conduction type first well region subregion, and be arranged at the first conduction type second source region in described second conduction type second well region subregion, to be arranged on the first conduction type second semiconductor layer and part covers the first source region, second source region, first insulating barrier of the first well region and the second well region, be arranged at the polysilicon layer on the first insulating barrier, to be arranged on the first conduction type second semiconductor layer and to cover second insulating barrier in polysilicon layer and part first source region and the second source region, to be arranged on the first conduction type second semiconductor layer and to cover the first source region, second source region, first well region, the first metal layer of the second well region and the second insulating barrier, be arranged at the second conduction type the 3rd semiconductor layer at the first conduction type first semiconductor layer back side, and cover second metal level at the second conduction type the 3rd semiconductor layer back side, the energy gap of described first conduction type second semiconductor layer is greater than the energy gap of the first conduction type first semiconductor layer, the doping content of described first conduction type second semiconductor layer is less than or equal to the doping content of the first conduction type first semiconductor layer.
2. semiconductor power device according to claim 1, is characterized in that, described first conduction type second semiconductor layer is surrounded on the first well region and the second well region, and the first conduction type first semiconductor layer is contacted with the first insulating barrier.
3. semiconductor power device according to claim 1, is characterized in that, described first conduction type second semiconductor layer is surrounded on the first well region and the second well region, and the first conduction type first semiconductor layer and the first insulating barrier is separated.
4. semiconductor power device according to claim 1, is characterized in that, the doping content of described first conduction type second semiconductor layer is 5e12/cm
3-1e15/cm
3, the doping content of described first conduction type first semiconductor layer is 5e12/cm
3-1e15/cm
3.
5. semiconductor power device according to claim 1, is characterized in that, the electron affinity energy of described first conduction type second semiconductor layer is less than the electron affinity energy of the first conduction type first semiconductor layer.
6. semiconductor power device according to claim 1, is characterized in that, the energy gap of described first conduction type second semiconductor layer is 1-5eV, and the energy gap of described first conduction type first semiconductor layer is 0.1-3eV.
7. semiconductor power device according to claim 1, is characterized in that, the material of described first conduction type second semiconductor layer is selected from the one in silicon, carborundum, aluminum phosphate, indium phosphide, aluminium arsenide.
8. semiconductor power device according to claim 1, is characterized in that, the material of described first conduction type first semiconductor layer is selected from the one in germanium, SiGe, carbon SiGe.
9. the semiconductor power device according to any one of claim 1-8, is characterized in that, described first conduction type is N-type, and the second conduction type is P type; Or described first conduction type is P type, the second conduction type is N-type.
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| CN201210073789.4A CN102760759B (en) | 2011-04-29 | 2012-03-20 | A kind of semiconductor power device |
| PCT/CN2012/074782 WO2012146190A1 (en) | 2011-04-29 | 2012-04-26 | Semiconductor power device |
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| CN102760759B true CN102760759B (en) | 2016-02-03 |
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| CN103500763B (en) * | 2013-10-15 | 2017-03-15 | 苏州晶湛半导体有限公司 | III nitride semiconductor devices and its manufacture method |
| TWI557878B (en) * | 2013-12-16 | 2016-11-11 | 旺宏電子股份有限公司 | Semiconductor device and method of fabricating the same |
| CN107516670B (en) * | 2017-08-17 | 2019-12-10 | 电子科技大学 | Grid-controlled thyristor with high current rise rate |
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| EP0837508A2 (en) * | 1996-10-18 | 1998-04-22 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| DE10117483A1 (en) * | 2001-04-07 | 2002-10-17 | Bosch Gmbh Robert | Semiconductor power component and corresponding manufacturing process |
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| CN101501859A (en) * | 2006-08-17 | 2009-08-05 | 克里公司 | High power insulated gate bipolar transistors |
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| JPS63157478A (en) * | 1986-12-22 | 1988-06-30 | Nissan Motor Co Ltd | Conductivity modulating mosfet |
| JP3198766B2 (en) * | 1993-12-27 | 2001-08-13 | 日産自動車株式会社 | Conductivity modulation type transistor |
| JP2002184986A (en) * | 2000-12-13 | 2002-06-28 | Mitsubishi Electric Corp | Field-effect semiconductor device |
| JP2007005723A (en) * | 2005-06-27 | 2007-01-11 | Toshiba Corp | Semiconductor device |
| US7687825B2 (en) * | 2007-09-18 | 2010-03-30 | Cree, Inc. | Insulated gate bipolar conduction transistors (IBCTS) and related methods of fabrication |
| CN102263127B (en) * | 2010-05-29 | 2013-06-19 | 比亚迪股份有限公司 | MOS (Metal Oxide Semiconductor) type power device and manufacturing method thereof |
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- 2012-04-26 WO PCT/CN2012/074782 patent/WO2012146190A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0837508A2 (en) * | 1996-10-18 | 1998-04-22 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| DE10117483A1 (en) * | 2001-04-07 | 2002-10-17 | Bosch Gmbh Robert | Semiconductor power component and corresponding manufacturing process |
| CN101101923A (en) * | 2006-07-07 | 2008-01-09 | 三菱电机株式会社 | Semiconductor device |
| CN101501859A (en) * | 2006-08-17 | 2009-08-05 | 克里公司 | High power insulated gate bipolar transistors |
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| CN102760759A (en) | 2012-10-31 |
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