CN102751974A

CN102751974A - Output buffer

Info

Publication number: CN102751974A
Application number: CN2011101029003A
Authority: CN
Inventors: 李建锡; 辛东橙
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2011-04-22
Filing date: 2011-04-22
Publication date: 2012-10-24
Anticipated expiration: 2031-04-22
Also published as: CN102751974B

Abstract

The invention discloses an output buffer which comprises a level conversion module, a preceding-stage drive module and an output module, wherein the level conversion module is used for generating a first logic signal with a first level range and a second logic signal with a second level range according to an input signal; the preceding-stage drive module is composed of a low-voltage transistor and is used for generating a first control signal and a second control signal according to the first logic signal and the second logic signal; the output module is used for generating an output signal with a third level range according to the first control signal and the second control signal; and the size of either of the first level range and the second level range is smaller than the size of the third level range.

Description

Output buffer

Technical field

The present invention relates to a kind of output buffer, refer to a kind of output buffer especially with low output jitter.

Background technology

Please refer to Fig. 1, Fig. 1 is the sketch map of known technology one output buffer 10.Output buffer 10 can be applicable to output voltage signal to the outside purposes of IC usually; For example be applied to system single chip (System-on-a-chip; SoC) on; Be sent to such as DRAM (Dynamic Random Access Memory, DRAM) required signal drive circuit such as memory device such as grade will export signal.As shown in Figure 1, output buffer 10 include usually one in logic and (AND) output transistor array 120_1～120_M, 122_1～122_M and the resistance 130 of lock 100, the accurate converting unit in position 102,104, fore-stage driver unit 110,112, parallel connection.And lock 100 pairs one an activation signals OE and a data-signal DATA actuating logic " and " operation, with according to enable signal OE, whether determine communicated data signal DATA, as an input signal IN.The value of input signal IN is between an initial high voltage VDD and an initial, low-voltage VSS.

The accurate converting unit 102,104 in position is according to a preset input and output transformation curve; Conversion and amplification input signal IN are one first logical signal LG1 and one second logical signal LG2 respectively; The codomain of the first logical signal LG1 and the second logical signal LG2 is all between one first high voltage VDDQ and one first low-voltage VSSQ, and VDDQ-VSSQ＞VDD-VSS.Fore-stage driver unit 110,112 by the inverter of serial connection or step by step amplifier forms, the foundation first logical signal LG1 and the second logical signal LG2 produces one first control signal CON1 and one second control signal CON2 respectively.At last, the output transistor array 120_1～120_M of parallel connection, 122_1～122_M are respectively according to the first control signal CON1 and the second control signal CON2, and the generation value is between the output signal OUT of the first high voltage VDDQ and the first low-voltage VSSQ.130 of resistance are used to provide static discharge (electrostaticdischarge, ESD) guard delay.

Output transistor array 120_1～120_M, 122_1～122_M are the output stage of directly facing load, are that (ComplementaryMetal-Oxide-Semiconductor, CMOS) transistor is formed by the high-voltage complementary metal-oxide semiconductor (MOS).In addition, fore-stage driver unit 110,112 is similarly the high-voltage complementary metal oxide semiconductor component.Yet; The employed operating voltage of high-speed interface circuit constantly descends; For example (Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2SDRAM) interface is that 1.8v, third generation double data rate SDRAM (DDR3SDRAM) interface are reduced to 1.5v, low-voltage third generation double data rate SDRAM (DDR3L SDRAM) interface is more reduced to 1.35v to second generation double data rate SDRAM.Under the trend that this output stage power supply supply voltage level reduces, the drive current of high voltage transistor will with weaken, and then produce bigger signal delay time.The noise that produces when simultaneously, low operating voltage also is unfavorable for resisting from power supply simultaneous operation relatively.As a result, output signal OUT can produce bigger output jitter.

Therefore, how under the continuous downward trend of operating voltage, keep stable one of effort target of industry that become of output buffer output signal.

Summary of the invention

Therefore, main purpose of the present invention promptly is to provide a kind of output buffer with low output jitter.

The present invention discloses a kind of output buffer, includes an accurate modular converter, is used for producing one first logical signal with first accurate scope and one second logical signal with second accurate scope according to an input signal; One prime driver module, it is made up of low voltage transistor, is used for according to this first logical signal and this second logical signal, and produces one first control signal and produce one second control signal in a Section Point in a first node; An and output module; Be coupled to this first node and this Section Point of this prime driver module; Be used for to produce the output signal with the 3rd accurate scope in an output according to this first control signal and this second control signal, wherein the size of each is the size less than the 3rd accurate scope in the middle of this first accurate scope and this second accurate scope.

Cooperate detailed description and claims of attached drawings, embodiment at this, will on address other purpose of the present invention and advantage and be specified in after.

Description of drawings

Fig. 1 is the configuration diagram of known technology one output buffer.

Fig. 2 is the configuration diagram according to the output buffer of an embodiment.

Wherein, description of reference numerals is following:

The VDD initial high voltage

The VSS initial, low-voltage

VDDQ first high voltage

VSSQ first low-voltage

VSS_SINK second low-voltage

The DATA data-signal

The OE enable signal

The IN input signal

LG1 first logical signal

LG2 second logical signal

CON1 first control signal

CON2 second control signal

OUT exports signal

VSWP [1:N] the first sequencing signal

VSWN [1:N] the second sequencing signal

The n1 first node

The n2 Section Point

The n_out output

10,20 output buffers

100 and lock

110,112 fore-stage driver unit

120_1～120_M, 122_1～122_M output transistor array

200 logical blocks

210 accurate modular converters

102,104,212 accurate converting units

214 delay cells

220 prime driver modules

222 first low pressure fore-stage driver unit

224 second low pressure fore-stage driver unit

230 output modules

The 232_1 first output block

The 232_2 second output block

The 232_p first type low voltage transistor

The 232_n second type low voltage transistor

234 high pressure sequencing unit

23,4_1 first sequencing control block

23,4_2 second sequencing control block

234_p1～234_pN first type high voltage transistor

234_n1～234_nN second type high voltage transistor

130,240 resistance

Embodiment

In the output buffer that following examples provided, can under the continuous downward trend of operating voltage, keep the stable of output signal.Following examples are considered at CMOS (Complementary Metal-Oxide-Semiconductor; CMOS) in the processing procedure; The drive current of low-voltag transistor is supplied the reduction of voltage level and the effect that weakens is more not obvious, therefore with directly realizing in the face of the part assembly of load changes with the low pressure assembly in the middle of the output buffer.As a result, output buffer is preferable for the resistivity of power supply noise, and can reach less output signal delay time, and then is prone to realize the output signal of low jitter.

Please refer to Fig. 2, Fig. 2 is the configuration diagram according to the output buffer 20 of an embodiment.Output buffer 20 includes the accurate modular converter of a logical block 200,210, a prime driver module 220, an output module 230 and a resistance 240.In addition, with the known technology of Fig. 1 similarly be, the input signal IN that is positioned at input side has the accurate scope of an initial bit, and it is equally between an initial high voltage VDD and an initial, low-voltage VSS.An output signal OUT who is positioned at an output n_out then has the 3rd accurate scope, and it is equally between one first high voltage VDDQ and one first low-voltage VSSQ.Yet compared to output buffer shown in Figure 1 10, output buffer 20 has several significant differences, comprising: directly realize in the face of the part assemblies in the middle of the prime driver module 220 of load and the output module 230 change with the low pressure assembly.In addition, in order to cooperate above-mentioned low-pressure structure, the accurate conversion range in position and the structure of the accurate modular converter 210 in position are also revised to some extent.The structure and the operation of each assembly in the output buffer 20 below more specifically are described.

Logical block 200 preferably is one and (AND) lock, be used for to an activation signal OE and a data-signal DATA actuating logic " and " operation, with according to enable signal OE, whether determine communicated data signal DATA, as an input signal IN.

The accurate modular converter 210 in position is used for producing one first logical signal LG1 with one first accurate scope and one second logical signal LG2 with one second accurate scope according to input signal IN.One specific characteristic of the accurate modular converter 210 in position is; In order to let the prime driver module 220 at rear can adopt the low pressure assembly to implement; The accurate modular converter 210 in position does not need amplification input signal IN, that is the accurate conversion range in position that its accurate conversion range can be arranged to than known technology is little.

Specifically; The accurate modular converter 210 in position known technology no longer as shown in Figure 1 all is converted to the first logical signal LG1 and the second logical signal LG2 the accurate scope in big position of the supply voltage of output module 230; That is the 3rd accurate scope (VDDQ～VSSQ), but less first accurate scope and second the accurate scope of the scope that is converted to.In other words, the size of second accurate scope of the size of first of the first logical signal LG1 accurate scope and the second logical signal LG2 is all less than the size of the 3rd the accurate scope of output signal OUT.

In addition; Different with known technology is; (the big I of each is arranged to no longer that (VDD～VSS) is less than or equal to the accurate scope of the initial bit (size of VDD～VSS) in fact but change into being arranged to greater than the accurate scope of the initial bit of input signal IN in the middle of the VDD～VSS) for first accurate scope of the first logical signal LG1 and second accurate scope of the second logical signal LG2.Preferably, the accurate modular converter 210 in position can be continued to use accurate scope of (LG2) initial bit or the accurate scope of translation (LG1) initial bit, can drive the low pressure assembly of prime driver module 220.More careful, first the accurate scope that obtains after the conversion then can be arranged between one first high voltage VDDQ and one second low-voltage VSS_SINK.Wherein the first high voltage VDDQ and the second low-voltage VSS_SINK must satisfy that (condition of VDDQ-VSS_SINK≤VDD-VSS), for example first accurate scope of initial bit that accurate scope is translation, that is VSS_SINK is set at and equals VDDQ-(VDD-VSS).In addition, it is different with first accurate scope that second accurate scope then can be set at, and for example can be set at the accurate scope of initial bit of continuing to use (promptly equaling in fact) input signal IN, also is between initial high voltage VDD and initial, low-voltage VSS.

Fig. 2 also shows the thin portion of the example framework of the accurate modular converter 210 in position, and it can be used to realize the above-mentioned preferable accurate conversion range in position.As shown in Figure 2, the accurate modular converter 210 in position is to include an accurate converting unit 212 and a delay cell 214.The accurate converting unit 212 in position is used for input signal IN is carried out the accurate conversion in position and produces the first logical signal LG1 with first accurate scope; Wherein first accurate scope can be arranged between the first high voltage VDDQ and the second low-voltage VSS_SINK; Wherein (condition of VDDQ-VSS_SINK≤VDD-VSS) must satisfy, and is VSS_SINK=VDDQ-(VDD-VSS) for example.In addition, 214 of delay cells are used for delay input signal IN, and with the second logical signal LG2 that generation has second accurate scope, wherein second accurate scope can be arranged between initial high voltage VDD and initial, low-voltage VSS.

Prime driver module 220 can by the serial connection inverter or step by step amplifier form.One specific characteristic of prime driver module 220 is that its known technology not as Fig. 1 adopts high voltage transistor to implement, and forms and change with low voltage transistor, therefore has less operating voltage range.Prime driver module 220 is used for according to the first logical signal LG1 and the second logical signal LG2, and produces one first control signal CON1 and produce one second control signal CON2 in a Section Point n2 in a first node n1.In specific embodiment shown in Figure 2, more show the thin bilge construction of an example of prime driver module 220, wherein 220 of prime driver modules can include one first low pressure fore-stage driver unit 222 and one second low pressure fore-stage driver unit 224.The first low pressure fore-stage driver unit 222 is used for exporting the first high voltage VDDQ or the second low-voltage VSS_SINK to first node n1, as the first control signal CON1 according to the first logical signal LG1.The second low pressure fore-stage driver unit 224 is used for according to the second logical signal LG2, and output initial high voltage VDD or initial, low-voltage VSS are to Section Point n2, as the second control signal CON2.

Output module 230 is used for to have the 3rd accurate scope (the output signal OUT of VDDQ～VSSQ) in output n_out generation according to the first control signal CON1 and the second control signal CON2.240 of resistance are used to provide static discharge (electrostatic discharge, ESD) guard delay.In specific embodiment shown in Figure 2, more show the thin bilge construction of an example of output module 230, wherein output module 230 includes a low pressure output unit and a high pressure sequencing unit 234.The former is owing to not directly in the face of load, therefore can be made up of low voltage transistor; Therefore latter Ze Yin is made up of high voltage transistor directly in the face of load.

The low pressure output unit includes one first output block 232_1 and one second output block 232_2; Formed by one first type low voltage transistor (for example being the P transistor npn npn) 232_p and one second type low voltage transistor (for example being the N transistor npn npn) 232_n respectively; Be used to receive the control of the first control signal CON1 and the second control signal CON2; Determining whether the first high voltage VDDQ is passed to output n_out, and determine whether the first low-voltage VSSQ is passed to output n_out.

In addition; 234 of high pressure sequencing unit include one first sequencing control block 234_1 and one second sequencing control block 234_2; Form by one or more first type high voltage transistor 234_p1～234_pN and one or more second type high voltage transistor 234_n1～234_nN respectively; It is coupled between low pressure output unit and the output n_out; Be used to receive the control of one first sequencing signal VSWP [1:N] and one second sequencing signal VSWN [1:N], determining between the first type low voltage transistor 232_p and the output n_out whether conducting, and determine between the second type low voltage transistor 232_n and the output n_out whether conducting.Through the conducting number among control high voltage transistor 234_p1～234_pN, the 234_n1～234_nN; One output impedance of the first sequencing signal VSWP [1:N] and second sequencing signal VSWN [1:N] the may command output buffer 20, and then the position of control output signal OUT is accurate.

It is noted that in this embodiment, to have only in the middle of the output buffer 20 in the face of realizing the high pressure sequencing unit of load 234, and prime driver module 220 and all change with the low pressure assembly with the low pressure output unit is realized with high potential assembly.Owing to directly realize with high potential assembly, can prevent that therefore output stage from meeting with puncturing (punch-through), or can avoid the accurate integrity problem that is caused that changes in output signal OUT position on the different application in the face of the high pressure sequencing unit 234 of load.In addition; Because prime driver module 220 and all change with the low pressure assembly with the low pressure output unit is realized; Therefore output buffer 20 is preferable for the resistivity of power supply noise, reaches the time of delay of less output signal OUT, and then is prone to realize the demand of output signal OUT low jitter.

In addition, it should be noted that therefore the first control signal CON1 and the second control signal CON2 must keep opposite phases because the running of output module 230 is only to go up bridge circuit (232_1,234_1) or bridge circuit (232_1,234_1) conducting down the same time.For this reason; Output buffer 20 preferably can also be set up a coupling capacitance 250 and be coupled between first node n1 and the Section Point n2; In order to the handover operation of the synchronous first control signal CON1 and the second control signal CON2, and then the work period of improving output signal OUT.

In known technology; Fore-stage driver unit 110,112 and output transistor array 120_1～120_M, the 122_1～122_M of output buffer 10 all realize with high potential assembly; Cause when operating voltage descends, output signal OUT shake is big or because of the higher normally problem of start of the conducting threshold voltage (Vth) of high potential assembly.In comparison; Have only in the middle of the output buffer 20 in the face of realizing the high pressure sequencing unit of load 234 with high potential assembly; And prime driver module 220 and low pressure output unit all change with the realization of low pressure assembly, and then reach when low operating voltage, the purpose of stable output signal OUT.

In sum, the present invention replaces high potential assembly in the driving stage and the output stage of output buffer with the low pressure assembly, under the trend that reduces at operating voltage, keeps the stable of output signal.

The above is merely the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. an output buffer is characterized in that, includes:

An accurate modular converter is used for producing one first logical signal with first accurate scope and one second logical signal with second accurate scope according to an input signal;

One prime driver module, it is made up of low voltage transistor, is used for according to this first logical signal and this second logical signal, and produces one first control signal and produce one second control signal in a Section Point in a first node; And

One output module is coupled to this first node and this Section Point of this prime driver module, is used for to produce an output signal with the 3rd accurate scope in an output according to this first control signal and this second control signal,

Wherein the size of each is the size less than the 3rd accurate scope in the middle of this first accurate scope and this second accurate scope.

2. output buffer as claimed in claim 1 is characterized in that, this first accurate scope is to be different from this second accurate scope.

3. output buffer as claimed in claim 1 is characterized in that, the size of each is the size that is less than or equal to the accurate scope of an initial bit of this input signal in fact in the middle of this first and second accurate scope.

4. output buffer as claimed in claim 1; It is characterized in that; The accurate scope of one initial bit of this input signal is between an initial high voltage and an initial, low-voltage; The 3rd accurate scope is between one first high voltage and one first low-voltage, and this first accurate scope reaches between one second low-voltage different with this first low-voltage between this first high voltage, and this second accurate scope is between this initial high voltage and this initial, low-voltage.

5. output buffer as claimed in claim 4 is characterized in that, this second low-voltage is to equal this first high voltage-(this initial high voltage-this initial, low-voltage) in fact.

6. output buffer as claimed in claim 1 is characterized in that, this output module comprises:

One low pressure output unit; It is made up of low voltage transistor; Be used to receive the control of this first control signal and this second control signal, whether be coupled to this output, and determine whether one first low-voltage source is coupled to this output to determine one first high voltage source.

7. output buffer as claimed in claim 6 is characterized in that, this output module more comprises:

One high pressure sequencing unit; It is made up of high voltage transistor; And be coupled to this low pressure output unit in one the 3rd node and one the 4th node; Be used to receive the control of one first sequencing signal and one second sequencing signal, determining between the 3rd node and this output whether conducting, and determine between the 4th node and this output whether conducting.

8. output buffer as claimed in claim 6 is characterized in that, this low pressure output unit comprises:

One first output block comprises one first type low voltage transistor coupled in parallel between this first high voltage source and one the 3rd node, and the control that is used to receive bridge control signal on this is with conducting or cut-out; And

One second output block comprises that one second type low voltage transistor coupled in parallel between this first low-voltage source and one the 4th node, is used to receive this second control signal with conducting or cut-out.

9. output buffer as claimed in claim 7 is characterized in that, this high pressure sequencing unit comprises:

One first sequencing control block comprises one or more first type high voltage transistor coupled in parallel between the 3rd node and this output, and the control that is used to receive this first sequencing signal is with conducting or cut-out; And

One second sequencing control block comprises one or more second type high voltage transistor coupled in parallel between the 4th node and this output, and the control that is used to receive this second sequencing signal is with conducting or cut-out.

10. output buffer as claimed in claim 1 is characterized in that, this accurate modular converter includes:

An accurate converting unit is coupled to this logical block, is used for this input signal is carried out the accurate conversion in position and produces this first logical signal with this first accurate scope; And

One delay cell is coupled to this logical block, is used for postponing this input signal has this second accurate scope with generation this second logical signal.

11. output buffer as claimed in claim 1 is characterized in that, this prime driver module includes:

One first low pressure fore-stage driver unit is coupled between one first high voltage source and one second low-voltage source, is used for according to this first logical signal to produce this first control signal in this first node; And

One second low pressure fore-stage driver unit is coupled between an initial high voltage source and the initial, low-voltage source, is used for according to this second logical signal to produce this second control signal in this Section Point.

12. output buffer as claimed in claim 1 is characterized in that, also comprises a coupling capacitance, is coupled between this first node and this Section Point, is used to increase the work period of this output signal.