CN102750245B - Message method of reseptance, message receiver module, Apparatus and system - Google Patents
Message method of reseptance, message receiver module, Apparatus and system Download PDFInfo
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Abstract
The invention provides a kind of message method of reseptance, message receiver module, Apparatus and system, after wherein message method of reseptance comprises and receives message, by the physical address in the first descriptor in message and the first descriptor queue and virtual address, and the virtual address in the second descriptor in the first descriptor queue is configured to bus message; Bus message is sent to current message buffer zone corresponding with the physical address in the first descriptor in internal memory, for the virtual address that central processing unit is corresponding according to current message buffer zone, reads the message in current message buffer zone; After removing physical address in the first descriptor and virtual address, the descriptor order in the first descriptor queue is shifted.Thus make central processing unit sequentially can be read content in message buffer by the mode of poll, effectively improve the treatment effeciency of system, reduce system overhead.
Description
Technical field
The present invention relates to computer communication technology, particularly relate to a kind of message method of reseptance, message receiver module, Apparatus and system.
Background technology
Direct access memory (DirectMemoryAccess, DMA) technology is the method for high speed transmission data between a kind of peripheral hardware and internal memory, and external apparatus interface card directly can access the data in mainframe memory with dma mode.
DMA transmission technology adopts two kinds of gordian techniquies, and namely message buffer descriptor is safeguarded and interrupt handling program.Message buffer descriptor safeguards the application and management that are mainly used in the message buffer of descriptor and descriptor indication; Interrupt handling program relates generally to the release of Message processing and buffer zone in buffer zone.
But, the software-hardware synergism that synchronously needs receiving and send descriptor is safeguarded, need to arrange multiple register, such as, descriptor base register, interrupt register, outage threshold register, descriptor quantity register and timeout register etc., not only process complexity, and occupy expense and the hardware logic resource of a large amount of central processing unit (CentralProcessingUnit, CPU).Down trigger mechanism needs to produce interruption according to the threshold value of setting to CPU, if interruption times is too frequent, can causes a large amount of process switching expenses, affect the work efficiency of CPU.Therefore, there is the lower problem of system treatment effeciency in DMA transmission technology of the prior art.
Summary of the invention
The invention provides a kind for the treatment of effeciency for improving DMA transmission technology, and reduce message method of reseptance, message receiver module, the Apparatus and system of system overhead.
First aspect of the present invention is to provide a kind of message method of reseptance, comprising:
After receiving message, by the physical address in the first descriptor in described message and the first descriptor queue and virtual address, and the virtual address in the second descriptor in described first descriptor queue is configured to bus message;
Wherein, described first descriptor comprises physical address and the virtual address of current message buffer zone in internal memory; Described second descriptor order comprises physical address and the virtual address of the next message buffer behind current message buffer zone described in described internal memory after being arranged in described first descriptor;
Described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, read the message in described current message buffer zone;
After removing physical address in described first descriptor and virtual address, descriptor order in described first descriptor queue is shifted, becomes physical address in the first descriptor after renewal and virtual address to make the physical address in described second descriptor and virtual address.
Another aspect of the present invention is to provide a kind of message receiver module, comprising:
First receiving element, for after receiving message, by the physical address in the first descriptor in described message and the first descriptor queue and virtual address, and the virtual address in the second descriptor in described first descriptor queue is configured to bus message;
Wherein, described first descriptor comprises physical address and the virtual address of current message buffer zone in internal memory; Described second descriptor order comprises physical address and the virtual address of the next message buffer behind current message buffer zone described in described internal memory after being arranged in described first descriptor;
First transmitting element, for described bus message being sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, read the message in described current message buffer zone;
First processing unit, for after the physical address removed in described first descriptor and virtual address, descriptor order in described first descriptor queue is shifted, becomes physical address in the first descriptor after renewal and virtual address to make the physical address in described second descriptor and virtual address.
Another aspect of the present invention is to provide a kind of network interface unit, comprises above-mentioned message receiver module.
Present invention also offers a kind of message receiving system, comprise above-mentioned network interface unit, internal memory and central processing unit.
Message method of reseptance provided by the invention, message receiver module, Apparatus and system, by being configured to the message received to comprise the bus message of the descriptor of current message buffer zone and the descriptor of next message buffer in internal memory, the virtual address of next message buffer can be known when making CPU read the message of current message buffer zone from internal memory, thus the content that can be read by the mode order of poll in message buffer, do not need to use multiple register to coordinate, do not need to produce to CPU to interrupt yet, effectively improve the treatment effeciency of system, reduce system overhead.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of message method of reseptance one embodiment of the present invention;
Fig. 2 is the schematic diagram of message buffer form in embodiment of the present invention internal memory;
Fig. 3 is the process flow diagram of another embodiment of message method of reseptance of the present invention;
Fig. 4 is the process flow diagram that embodiment of the present invention message receiver module receives message;
Fig. 5 is the process flow diagram that embodiment of the present invention central processing unit receives message;
Fig. 6 is the structural representation of message receiver module embodiment of the present invention;
Fig. 7 is the structural representation of message receiving system embodiment of the present invention;
Fig. 8 is a kind of system architecture of embodiment of the present invention message receiving system.
Embodiment
Technical scheme in various embodiments of the present invention is the improvement carried out from the method that dma controller receives message host memory.Dma controller adopts the packet sending and receiving between the realization of DMA technology with host memory, and wherein, dma controller comprises DMA and sends engine and DMA reception engine.DMA sends engine and is used for the message in host memory to be sent to external device or the network equipment etc.; DMA receives engine and is used for the message received from external device or the network equipment to be sent to host memory.
Message receiver module in various embodiments of the present invention comprises DMA and receives engine and relevant functional module, and the message receiver module namely in following embodiment has DMA and receives the function of engine and relevant control and processing capacity; Host memory is also called internal memory for short in following embodiment; Central processing unit is also called CPU for short in following embodiment.
Fig. 1 is the process flow diagram of message method of reseptance one embodiment of the present invention, and as shown in Figure 1, the method comprises:
Step 101, receive message after, by the physical address in the first descriptor in described message and the first descriptor queue and virtual address, and the virtual address in the second descriptor in described first descriptor queue is configured to bus message.
Wherein, described first descriptor comprises physical address and the virtual address of current message buffer zone in internal memory; Described second descriptor order comprises physical address and the virtual address of the next message buffer behind current message buffer zone described in described internal memory after being arranged in described first descriptor.
Message receiver module is from after external device or the network equipment receive message, and need the message received to be configured to bus message, this bus message comprises descriptor field and message territory.
Concrete building method is, the first descriptor and the second descriptor is read in the first descriptor queue stored from this message receiver module, by the physical address in the first descriptor and virtual address, virtual address in second descriptor, and control information and the message that receives are configured to bus message.Wherein, the physical address in the first descriptor and virtual address, the virtual address in the second descriptor and control information are stored in the descriptor field of bus message, and the packet storage received is in the message territory of bus message.In bus message comprise information order controlled by message receiver module and the software program be stored in advance in CPU, carry out constructing according to the agreement of communicating pair.
Wherein, the first descriptor queue stored in message receiver module, comprise at least two tactic descriptors, each descriptor includes a physical address and a virtual address, and in same descriptor, physical address and virtual address correspond to the same storage space in internal memory.
Difference is, physical address is the actual address of the storage space of stored messages in internal memory, for supplying other devices or module according to this physical address by storage space corresponding in message write memory, when CPU needs the message reading this storage space in internal memory, then need to access this storage space according to virtual address, the same storage space that what physical address and virtual address were pointed to is in internal memory.
Because the descriptor in the first descriptor queue is tactic, being therefore the first descriptor by the descriptor definition being wherein positioned at queue reference position, is the second descriptor by the order descriptor definition be arranged in after the first description.First and second only for the location order of flag descriptor in queue.
When constructing bus message, by the storage space in the physical address in the first descriptor and the internal memory pointed by virtual address, as the destination of this bus message; Except comprising destination-address, in bus message, also carry the virtual address in the second descriptor, storage space in the internal memory pointed by virtual address in this second descriptor is the storage space that order is arranged in after bus message sending destination, i.e. next message buffer.
Control information comprises the transmitting state information of this bus message, comprises the length of message and the port information of message transmission etc. in the message territory of this bus message in addition and ensures the information of message normal transmission.
By the virtual address in the physical address in the first descriptor and virtual address, the second descriptor, and control information is stored in the descriptor field of bus message, by the packet storage that receives in message territory, be bus message by descriptor field and message domain construction.
What the message buffer of the reception bus message in internal memory adopted is chain sheet form, concrete, the virtual address in the second descriptor preserved in current message buffer zone, is the pointer pointing to next message buffer.
Be understandable that, in order to ensure the bus message that internal memory normally can receive message receiver module and sends, the form of bus message is consistent with the form of the message buffer receiving bus message in internal memory.
Fig. 2 is the schematic diagram of message buffer form in embodiment of the present invention internal memory, as shown in Figure 2, is illustrated the form of message buffer.
Message buffer is made up of descriptor field and message territory, wherein sets the size of message buffer as 2KB, is divided into 64 unit, and the size of each unit is 256.Wherein, 1st unit is the descriptor field of message buffer, comprise 64 physical address Phy_Addr of current message buffer zone, 64 virtual address Virt_Addr, 64 virtual address Next_Virt_Addr of next message buffer after 64 control information Ctrl_Status and current message buffer zone, wherein control information comprises 1 hardware transport and completes flag HWCpl, and all the other positions retain; 2nd unit is message territory Packet to the 64th unit.
Wherein, Phy_Addr is the physical address of current message buffer zone, and message can be write this current message buffer according to this physical address by message receiver module.
Virt_Addr is the virtual address of current message buffer zone, and CPU can access the message in this current message buffer according to this virtual address.
Ctrl_Status is the control information of this bus message, mainly comprises and is transmitted flag HWCpl.If when message buffer does not receive bus message, in the descriptor field of this message buffer, this flag is 0, in the bus message that message receiver module constructs, this flag is 1, so after message buffer receives bus message, namely this flag is updated to 1, thus illustrating that message buffer have received bus message, the message transmissions of message receiver module and internal memory completes; If control information in message receiver module is set to control information in 0 and message buffer be set to 1, the renewal of control information after interior existence receives bus message can be realized equally, and the form of control information is not limited in this.
Next_Virt_Addr is the virtual address of next message buffer after this current message buffer, for knowing the virtual address of next message buffer when accessing current message buffer zone for CPU, thus when next message buffer accessed by needs, utilize this virtual address can realize access.
Message territory is for storing the message content received.The form of bus message sent due to message receiver module is consistent with the form of message buffer, message buffer is not when receiving bus message, its descriptor field comprises current message buffer zone, the address information of next message buffer and control information, and message territory is empty; After current message buffer zone receives bus message, the content of bus message covers the content of current message buffer zone, thus the control information in current message buffer zone is upgraded, and is written with message content in message territory.
Be understandable that, above illustrational content is only a kind of implementation in the embodiment of the present invention, and optional implementation is not limited in this.
Step 102, described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, read the message in described current message buffer zone.
Message receiver module is after having constructed bus message, according to the physical address read from the first descriptor entrained in the descriptor field of this bus message, bus message is sent to the message buffer that this physical address is corresponding, this message buffer is current message buffer zone.
After bus message is sent to internal memory by message receiver module, CPU according to the virtual address of the message buffer of correspondence, can read the message content in the message territory of this message buffer from internal memory.
CPU judges the control information in the descriptor field of current message buffer zone, if judge, current message buffer zone receives message, then read message in the message territory of current message buffer zone, do not receive message if judge in current message buffer zone, be then in waiting status.
Step 103, remove physical address in described first descriptor and virtual address after, descriptor order in described first descriptor queue is shifted, becomes physical address in the first descriptor after renewal and virtual address to make the physical address in described second descriptor and virtual address.
Content corresponding for the first descriptor in first descriptor queue, after the bus message of structure is sent to internal memory, is removed by message receiver module, that is, the physical address in the first descriptor and virtual address are removed.And, because order in the first descriptor queue is arranged with two or more descriptor, if when the descriptor in the first descriptor queue is three or more, descriptor order in this first descriptor queue is shifted, that is, after the content in the first descriptor is eliminated, first descriptor is empty, descriptor entirety is shifted forward, the physical address and the virtual address that make to be arranged in the second descriptor are displaced to the first descriptor, the descriptor being arranged in the 3rd position in former first descriptor queue is displaced in the second descriptor, by that analogy, descriptor is all to reach one, correspondingly, in first descriptor queue, the memory location of the descriptor at end is empty.Physical address in first descriptor and the second descriptor and virtual address obtain renewal respectively.
In actual applications, message receiver module is when constructing bus message, the mode reading the first descriptor and the second descriptor from the first descriptor queue can also be, by the first descriptor of reading stored in register Cur_Des, by the second descriptor of reading stored in register Next_Des, utilize the descriptor construction bus message in these two registers; And after the first two descriptor in the first descriptor queue is read, removing to two descriptors, the descriptor entirety in queue shifts forward, and makes the position of the initial memory descriptor of the first descriptor queue not for empty; Thus after this bus message sends by message receiver module, under construction during a bus message, the physical address stored in former register Cur_Des and virtual address are removed, physical address in former register Next_Des and virtual address are stored in register Cur_Des, continue to read new descriptor from the initial position the first descriptor queue, stored in register Next_Des, and by that analogy.
Message method of reseptance in the embodiment of the present invention, by being configured to the message received to comprise the bus message of the descriptor of current message buffer zone and the descriptor of next message buffer in internal memory, the virtual address of next message buffer can be known when making CPU read the message of current message buffer zone from internal memory, thus the content that can be read by the mode order of poll in message buffer, do not need to use multiple register to coordinate, do not need to produce to CPU to interrupt yet, effectively improve the treatment effeciency of system, reduce system overhead.
Further, on the basis of above-described embodiment, after performing step 103, the method also comprises:
Step 104, receive that described central processing unit sends after reading the message in described current message buffer zone, to the recovery command that physical address and the virtual address of described current message buffer zone reclaim.
Step 105, by the physical address that carries in described recovery command and the virtual address end stored in described first descriptor queue.
CPU after reading message from current message buffer zone, the message read is sent to network protocol stack, and send recovery command to message receiver module, physical address and the virtual address of current message buffer zone is carried in this recovery command, that is, this message buffer can continue the bus message that sends for receiving message receiver module.
Now, control information in descriptor field in this current message buffer is updated to the state not receiving bus message, and the content in message territory retains, when waiting for that this message buffer receives follow-up bus message, the content in this message territory covers by the content in the message territory of new bus message.
The physical address carried in this recovery command and virtual address, after the recovery command receiving CPU transmission, are stored on the room at the end of the first descriptor queue by message receiver module.
Message method of reseptance in the embodiment of the present invention, by after the message that read current message buffer zone in internal memory at CPU, the descriptor of instruction message receiver module to current message buffer zone reclaims, stored in the end of the first descriptor queue, when reading descriptor construction bus message to make message receiver module order from the first descriptor queue, available descriptor can be got continuously, thus avoid the action that message receiver module initiates interruption after available descriptor is all by use, effectively improve the treatment effeciency of system, reduce system overhead.
Fig. 3 is the process flow diagram of another embodiment of message method of reseptance of the present invention, and on the basis of the various embodiments described above, before performing step 101, as shown in Figure 3, the method also comprises:
Step 200, receive described central processing unit after initialization is carried out to described internal memory, the base address of the second descriptor queue in the described internal memory of transmission, and the quantity of descriptor in described second descriptor queue.
Wherein, described second descriptor queue stores at least two message buffers descriptor separately in described internal memory, and described descriptor comprises the physical address of described message buffer in described internal memory and virtual address.
Step 201, the descriptor of described quantity will read from described internal memory according to described base address, as described first descriptor queue.
Before message receiver module receives message, need the first descriptor queue first obtained for constructing bus message.
Concrete grammar is, CPU is when internally depositing into row initialization, and can be stored in queue by the descriptor of at least two message buffers initialized in internal memory, this queue is the second descriptor queue.Save these at least two message buffers descriptor separately in second descriptor queue, the descriptor of each message buffer comprises the physical address of this message buffer and the virtual address corresponding with this physical address; The quantity of descriptor that CPU will store in the base address of the second descriptor queue and the second descriptor queue, send to message receiver module, wherein this base address is the initial physical address of storage second descriptor queue; Message receiver module is according to this base address and quantity, and the storage space that this base address is corresponding from internal memory, reads the descriptor of this quantity, and descriptor order composition the first descriptor queue that will read, for constructing bus message.
Message method of reseptance in the embodiment of the present invention, by CPU to interior deposit into row initialization time, obtain the descriptor of the message buffer in internal memory, for constructing bus message, because CPU is after the descriptor of the message buffer read, can inform that message receiver module reclaims this descriptor, the descriptor that message receiver module is obtained when internal memory initialization can be recycled, interrupting without the need to producing to CPU, effectively improve the treatment effeciency of system, reducing system overhead.
Further, on the basis of the various embodiments described above, when CPU reads the message in current message buffer zone from internal memory, it knows that the method for the virtual address of current message buffer zone has following two kinds.
The first situation is, if described bus message is the first bus message sent to described internal memory, that is, CPU after internally depositing into row initialization, the situation of first message buffer in access memory.
CPU to interior deposit into row initialization after, virtual address in first descriptor in the second descriptor queue stored in internal memory is the virtual address of first message buffer, CPU reads the virtual address of first descriptor from the second descriptor queue, get final product message buffer corresponding in access memory, obtain the message content in the message territory of current message buffer zone.
The second situation is, if described bus message is not the first bus message sent to described internal memory, that is, CPU read the message in message buffer from internal memory, then can know the virtual address preparing to carry out the message buffer read the descriptor field of message buffer that CPU has read from this.CPU gets final product the current message buffer zone in access memory according to this virtual address, reads the message content in the message territory in current message buffer zone.The rest may be inferred, according to the structure of bus message and the form of message buffer, CPU can know the virtual address of next message buffer from the descriptor field of current message buffer zone, thus can access next message buffer according to this virtual address learnt.
Message method of reseptance in the embodiment of the present invention, CPU is after to internal memory initialization, after reading message according to the virtual address of first message buffer, according to the virtual address of next message buffer in the descriptor field of current message buffer zone, next message buffer can be accessed, and utilize the message buffer in the method poll internal memory, do not need to safeguard separately descriptor list, do not need to produce to CPU to interrupt, effectively improve the treatment effeciency of system, reduce system overhead yet.
Fig. 4 is the process flow diagram that embodiment of the present invention message receiver module receives message, and as shown in Figure 4, the flow process that message receiver module receives message comprises:
Step 400, message receiver module, before reception message, need to carry out initialization, read the descriptor of at least two message buffers in internal memory from the second descriptor queue CPU, by the descriptor that reads stored in the first descriptor queue;
Step 401, message receiver module detect whether receive message, if do not receive message, then circulation performs step 401, wait-receiving mode message; If receive message, then continue to perform step 402;
Step 402, message receiver module are after receiving message, the descriptor of application message buffer, namely from the first descriptor queue, descriptor is applied for, the descriptor being positioned at queue reference position from the first descriptor queue and the descriptor be sequentially arranged in after this descriptor, respectively stored in register Cur_Des and register Next_Des;
Step 403, message receiver module extract physical address Phy_Addr in register Cur_Des and virtual address Virt_Addr, prepare the bus message of structure stored in the current message buffer zone in internal memory corresponding to this descriptor; Extract the virtual address Virt_Addr in register Next_Des, as Nest_Virt_Addr, being carried on during for constructing bus message in the descriptor field of bus message, knowing the memory address of next message buffer after current message buffer zone to make CPU according to this virtual address;
Step 404, message receiver module utilize the physical address and virtual address that extract from register Cur_Des and register Next_Des, and the message received and the control information required for message transmission, and structure comprises the bus message of above-mentioned each data;
Step 405, message receiver module are by the message buffer in the bus message write memory of structure, and this message buffer is current message buffer zone corresponding to physical address that message receiver module extracts from register Cur_Des;
Step 406, message receiver module are after by bus message write memory, by in the descriptor write register Cur_Des in register Next_Des, continue from the first descriptor queue, apply for that new descriptor is stored in register Next_Des, and continue to perform step 401, wait-receiving mode message, correspondingly performs subsequent operation.
Fig. 5 is the process flow diagram that embodiment of the present invention central processing unit receives message, and as shown in Figure 5, the flow process that central processing unit receives message comprises:
Step 500, CPU extract thread parameter, according to when internally depositing into row initialization, and the virtual address of first message buffer in the second descriptor queue stored in internal memory, message buffer corresponding to this virtual address is read in access;
Step 501, CPU, according to being transmitted flag HWCpl, judge whether have message in current message buffer zone, due to this message buffer do not receive bus message time, its HWCpl is 0, and after receiving bus message, HWCpl is 1; If thus judge not receive bus message in current message buffer zone according to HWCpl, then circulation perform step 501, wait-receiving mode bus message; Receive bus message if judge in current message buffer zone, then perform step 502;
Step 502, CPU are after receiving bus message, extract the summary info of message in the message territory of bus message, and perform step 503 and summary info is stored in summary queue, for system, record is carried out to information such as the quantity of received message, byte length, the quantity of data stream and the duration of data stream; Continue to perform step 504 simultaneously;
It should be noted that, the implementation in step 502 is identical with mode used in the prior art;
The message received is sent to network protocol stack by step 504, CPU, and wherein network protocol stack is upper layer application;
Step 505, CPU receive and after processing message, the HWCpl in the descriptor field of this message buffer are reverted to original state, namely resets;
The message buffer read reclaims by step 506, CPU, the physical address of this message buffer and virtual address are carried in recovery command, send to message receiver module, instruction message receiver module reclaims this message buffer, that is, this message buffer is in upstate, can be used for receiving new bus message;
Step 507, CPU, according to the virtual address of next message buffer entrained in the descriptor field of the message buffer read, namely may have access to next message buffer, thus realize the poll of CPU to the message buffer in internal memory.
The embodiment of the present invention is by being configured to the message received, comprise the bus message of the descriptor of current message buffer zone and the descriptor of next message buffer in internal memory, the virtual address of next message buffer can be known when making CPU read the message of current message buffer zone from internal memory, thus the content that can be read by the mode order of poll in message buffer, do not need to use multiple register to coordinate, do not need to produce to CPU to interrupt yet, effectively improve the treatment effeciency of system, reduce system overhead.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Fig. 6 is the structural representation of message receiver module embodiment of the present invention, and as shown in Figure 6, this message receiver module comprises:
First receiving element 11, for after receiving message, by the physical address in the first descriptor in described message and the first descriptor queue and virtual address, and the virtual address in the second descriptor in described first descriptor queue is configured to bus message;
Wherein, described first descriptor comprises physical address and the virtual address of current message buffer zone in internal memory; Described second descriptor order comprises physical address and the virtual address of the next message buffer behind current message buffer zone described in described internal memory after being arranged in described first descriptor;
First transmitting element 12, for described bus message being sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, read the message in described current message buffer zone;
First processing unit 13, for after the physical address removed in described first descriptor and virtual address, descriptor order in described first descriptor queue is shifted, becomes physical address in the first descriptor after renewal and virtual address to make the physical address in described second descriptor and virtual address.
Further, on the basis of above-described embodiment, this message receiver module also comprises:
Second receiving element 14, after the descriptor order in described first descriptor queue being shifted at described first processing unit 13, receive that described central processing unit sends after reading the message in described current message buffer zone, to the recovery command that physical address and the virtual address of described current message buffer zone reclaim;
Second processing unit 15, for the physical address that will carry in described recovery command and the virtual address end stored in described first descriptor queue.
Further, on the basis of the various embodiments described above, this message receiver module also comprises:
3rd receiving element 16, before receiving message at described first receiving element 11, receive described central processing unit after initialization is carried out to described internal memory, the base address of the second descriptor queue in the described internal memory of transmission, and the quantity of descriptor in described second descriptor queue;
Wherein, described second descriptor queue stores at least two message buffers descriptor separately in described internal memory, and described descriptor comprises the physical address of described message buffer in described internal memory and virtual address;
3rd processing unit 17, for the descriptor of described quantity will read from described internal memory according to described base address, as described first descriptor queue.
Further, on the basis of the various embodiments described above, if described first transmitting element 12 is first bus message to the bus message that described internal memory sends;
Correspondingly, described first transmitting element 12 also for, described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for described central processing unit according to the virtual address in the first descriptor in described second descriptor queue, read the message in described current message buffer zone;
If described first transmitting element 12 is not first bus message to the bus message that described internal memory sends;
Correspondingly, described first transmitting element 12 also for, described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address of described central processing unit according to the described current message buffer zone read from the upper message buffer before described current message buffer zone, read the message in described current message buffer zone.
It should be noted that, the content such as adopt during name to each functional module first, second, and third, only for distinguishing each functional module, does not represent the order between each functional module.
Concrete, the message receiver module in the embodiment of the present invention carries out the method for message reception, see the embodiment of the method for above-mentioned correspondence, can repeat no more herein.
Message receiver module in the embodiment of the present invention, by being configured to the message received to comprise the bus message of the descriptor of current message buffer zone and the descriptor of next message buffer in internal memory, the virtual address of next message buffer can be known when making CPU read the message of current message buffer zone from internal memory, thus the content that can be read by the mode order of poll in message buffer, do not need to use multiple register to coordinate, do not need to produce to CPU to interrupt yet, effectively improve the treatment effeciency of system, reduce system overhead.
Fig. 7 is the structural representation of message receiving system embodiment of the present invention; Fig. 8 is a kind of system architecture of embodiment of the present invention message receiving system.As shown in Figure 7, this message receiving system comprises network interface unit 1, internal memory 2 and central processing unit 3, and wherein network interface unit 1 comprises message receiver module 4.
Concrete, in the embodiment of the present invention, message receiving system carries out the method for message reception, see the embodiment of the method for above-mentioned correspondence, can repeat no more herein.
Message receiving system in the embodiment of the present invention, by being configured to the message received to comprise the bus message of the descriptor of current message buffer zone and the descriptor of next message buffer in internal memory, the virtual address of next message buffer can be known when making CPU read the message of current message buffer zone from internal memory, thus the content that can be read by the mode order of poll in message buffer, do not need to use multiple register to coordinate, do not need to produce to CPU to interrupt yet, effectively improve the treatment effeciency of system, reduce system overhead.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a message method of reseptance, is characterized in that, comprising:
After receiving message, by the physical address in the first descriptor in described message and the first descriptor queue and virtual address, and the virtual address in the second descriptor in described first descriptor queue is configured to bus message;
Wherein, described first descriptor comprises physical address and the virtual address of current message buffer zone in internal memory; Described second descriptor order comprises physical address and the virtual address of the next message buffer behind current message buffer zone described in described internal memory after being arranged in described first descriptor;
Described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, read the message in described current message buffer zone;
After removing physical address in described first descriptor and virtual address, descriptor order in described first descriptor queue is shifted, becomes physical address in the first descriptor after renewal and virtual address to make the physical address in described second descriptor and virtual address.
2. message method of reseptance according to claim 1, is characterized in that, after the described descriptor order by described first descriptor queue is shifted, described method also comprises:
Receive that described central processing unit sends after reading the message in described current message buffer zone, to the recovery command that physical address and the virtual address of described current message buffer zone reclaim;
By the physical address that carries in described recovery command and the virtual address end stored in described first descriptor queue.
3. message method of reseptance according to claim 1 and 2, is characterized in that, described in receive message before, described method also comprises:
Receive described central processing unit after initialization is carried out to described internal memory, the base address of the second descriptor queue in the described internal memory of transmission, and the quantity of descriptor in described second descriptor queue;
Wherein, described second descriptor queue stores at least two message buffers descriptor separately in described internal memory, described descriptor comprises the physical address of described message buffer in described internal memory and virtual address, and described base address is store the initial base address that described second describes queue;
According to the quantity of descriptor in the base address of described second descriptor queue and described second descriptor queue, from the storage space that the base address of the second descriptor queue described in described internal memory is corresponding, read the descriptor of the descriptor quantity in described second descriptor queue, and descriptor order composition the first descriptor queue that will read, for constructing bus message.
4. message method of reseptance according to claim 3, is characterized in that, if described bus message is the first bus message sent to described internal memory;
Correspondingly, describedly described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, the message read in described current message buffer zone comprises:
Described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for described central processing unit according to the virtual address in the first descriptor in described second descriptor queue, read the message in described current message buffer zone;
If described bus message is not the first bus message sent to described internal memory;
Correspondingly, describedly described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, the message read in described current message buffer zone comprises:
Described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address of described central processing unit according to the described current message buffer zone read from the upper message buffer before described current message buffer zone, read the message in described current message buffer zone.
5. a message receiver module, is characterized in that, comprising:
First receiving element, for after receiving message, by the physical address in the first descriptor in described message and the first descriptor queue and virtual address, and the virtual address in the second descriptor in described first descriptor queue is configured to bus message;
Wherein, described first descriptor comprises physical address and the virtual address of current message buffer zone in internal memory; Described second descriptor order comprises physical address and the virtual address of the next message buffer behind current message buffer zone described in described internal memory after being arranged in described first descriptor;
First transmitting element, for described bus message being sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address that central processing unit is corresponding according to described current message buffer zone, read the message in described current message buffer zone;
First processing unit, for after the physical address removed in described first descriptor and virtual address, descriptor order in described first descriptor queue is shifted, becomes physical address in the first descriptor after renewal and virtual address to make the physical address in described second descriptor and virtual address.
6. message receiver module according to claim 5, is characterized in that, described message receiver module also comprises:
Second receiving element, after the descriptor order in described first descriptor queue being shifted at described first processing unit, receive that described central processing unit sends after reading the message in described current message buffer zone, to the recovery command that physical address and the virtual address of described current message buffer zone reclaim;
Second processing unit, for the physical address that will carry in described recovery command and the virtual address end stored in described first descriptor queue.
7. the message receiver module according to claim 5 or 6, is characterized in that, described message receiver module also comprises:
3rd receiving element, before receiving message at described first receiving element, receive described central processing unit after initialization is carried out to described internal memory, the base address of the second descriptor queue in the described internal memory of transmission, and the quantity of descriptor in described second descriptor queue;
Wherein, described second descriptor queue stores at least two message buffers descriptor separately in described internal memory, described descriptor comprises the physical address of described message buffer in described internal memory and virtual address, and described base address is the initial physical address storing described second descriptor queue;
3rd processing unit, for the quantity according to descriptor in the base address of described second descriptor queue and described second descriptor queue, from the storage space that the base address of the second descriptor queue described in described internal memory is corresponding, read the descriptor of the quantity of the independent interior descriptor of described second descriptor, the descriptor read order is formed described first descriptor queue, for constructing bus message.
8. message receiver module according to claim 7, is characterized in that, if described first transmitting element is first bus message to the bus message that described internal memory sends;
Correspondingly, described first transmitting element also for, described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for described central processing unit according to the virtual address in the first descriptor in described second descriptor queue, read the message in described current message buffer zone;
If described first transmitting element is not first bus message to the bus message that described internal memory sends;
Correspondingly, described first transmitting element also for, described bus message is sent to described current message buffer zone corresponding with the physical address in described first descriptor in described internal memory, for the virtual address of described central processing unit according to the described current message buffer zone read from the upper message buffer before described current message buffer zone, read the message in described current message buffer zone.
9. a network interface unit, is characterized in that, comprise as arbitrary in claim 5-8 as described in message receiver module.
10. a message receiving system, is characterized in that, comprises network interface unit as claimed in claim 9, internal memory and central processing unit.
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| CN103150278B (en) * | 2013-03-05 | 2014-03-05 | 中国人民解放军国防科学技术大学 | Submission method of descriptor of network interface card (NIC) based on mixing of PIO (process input output) and DMA (direct memory access) |
| CN104461924A (en) * | 2014-11-04 | 2015-03-25 | 福建星网锐捷网络有限公司 | Collection method and system for message memories |
| CN104394099B (en) * | 2014-12-08 | 2017-09-19 | 福建星网锐捷网络有限公司 | A kind of message transmitting method and device |
| CN105656805B (en) * | 2016-01-20 | 2018-09-25 | 中国人民解放军国防科学技术大学 | A kind of packet receiving method and device based on control block predistribution |
| CN108234348B (en) * | 2016-12-13 | 2020-09-25 | 深圳市中兴微电子技术有限公司 | Processing method and device in queue operation |
| CN110943941B (en) * | 2019-12-06 | 2022-03-11 | 北京天融信网络安全技术有限公司 | Message receiving method, network card and electronic equipment |
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