CN102739472A - Method for testing stability of high-frequency data transmission for server - Google Patents
Method for testing stability of high-frequency data transmission for server Download PDFInfo
- Publication number
- CN102739472A CN102739472A CN2012102197922A CN201210219792A CN102739472A CN 102739472 A CN102739472 A CN 102739472A CN 2012102197922 A CN2012102197922 A CN 2012102197922A CN 201210219792 A CN201210219792 A CN 201210219792A CN 102739472 A CN102739472 A CN 102739472A
- Authority
- CN
- China
- Prior art keywords
- communication link
- test
- communication
- data
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
The invention provides a method for testing the stability of high-frequency data transmission for a server. The communication bit error rate of key nodes through which high-frequency data passes when being transmitted in a server system is tested to detect whether the server system is designed reasonably or not and the running stability meets market requirements or not. The key testing node comprises a communication link between processors, a memory communication link and a PCIE (Peripheral Component Interconnect Express) high-speed expansion equipment communication link, wherein a data transmission node between the processors is responsible for data transmission between the processors, and a memory communication link node is responsible for data transmission between the processors and a memory; and a PCIE high-speed expansion equipment communication link node is responsible for data transmission between the processors/memory and PCIE high-speed expansion equipment. According to the method, the data transmission bit error rate of the communication link between processors, the memory communication link and the PCIE high-speed expansion equipment communication link is tested to validate whether the server runs stably or not under the condition of high-frequency data transmission.
Description
Technical field
The current server system development is rapid; Message transmission rate in the server system progressively improves; Challenge to the stability Design of server is brought is also increasing; In order to satisfy in effective authentication server system under the lower cost in high-frequency data transmission stability down, this paper has designed a kind of no code check of the key node through testing the high speed data transfer process respectively, thereby effectively whether stable the authentication server system move method.
Background technology
Nowadays server inner high speed transfer of data has following characteristics:
1, data need visit each other between the processor, and transmission rate is the highest;
2, data need visit each other between processor and the memory device, and transmission rate is high;
3, low speed long term data storage equipment (for example hard disk) is connected to processor through the high-speed PCI E equipment of integrated RAID function, and data need visit each other between high-speed PCI E expansion equipment and the processor, and transmission rate is lower.
Summary of the invention
The method of testing that the purpose of this invention is to provide a kind of server high-frequency data transmission stability.
The objective of the invention is to realize by following mode; Come the authentication server whether can stable operation under high-frequency data transmission situation through the data transmission error rate on communication link, internal memory communication link, the PCIE high speed expansion equipment communication link between test processor; Through the communication error rate of test between the key node of server system medium-high frequency transfer of data process; Whether detect the server system design reasonable; Whether operation stability meets the need of market, and crucial test node comprises: communication among processors link, internal memory communication link, PCIE high speed expansion equipment communication link, wherein:
The communication among processors link nodes is responsible for the transfer of data between the processor;
Internal memory communication link node is responsible for the transfer of data between processor and the internal memory;
PCIE high speed expansion equipment communication link node is responsible for the transfer of data between processor/internal memory and the PCIE high speed expansion equipment, and concrete testing procedure is following:
1) communication link between test processor: utilize QPI BER test to carry out the processor data test of giving out a contract for a project; Contrast sending and receiving two ends processor test data; If deviation is bigger; It is bigger to explain that transmission link disturbs the data communication, should adopt and improve and optimizate CPU Layout circuit, the amplification of increase cpu signal is provided with and improves communication among processors;
2) test memory communication link: utilize the data communication between Rank Margin tool test processor and internal memory; The Margin value that obtains under the various memory configurations of collecting test feedback is judged the risk that the internal memory communication link exists; If the Margin value is lower; It is bigger to explain that transmission link disturbs the data communication, should adopt the Layout circuit that improves and optimizates between CPU and internal memory to improve communication;
3) test PCIE high speed expansion equipment communication link: utilize signal eye diagram to test and judge whether the PCIE signal quality passes through industrial standard; If there is the FAIL state in signal graph; It is bigger to explain that transmission link disturbs the data communication, should adopt the Layout circuit that improves and optimizates between CPU and PCIE slot to improve communication.
Friendship effect of the present invention is: the server high-frequency data transmission stability method of testing that to sum up proposes through this paper, and the effective stability Design of authentication server, pass test data is fed back can effectively promote the product design quality.
Description of drawings
Fig. 1 is a server system high-frequency data transmission flow graph;
Fig. 2 is a test flow chart.
Embodiment
Explanation at length below with reference to Figure of description method of the present invention being done.
Current server system and interior data logical transport path are through the connection between above 3 mutual paths of data, form server internal data high-speed transfer network.To above transmission feature; Communication among processors link, internal memory communication link, PCIE high speed expansion equipment communication link are carried out the serial testing authentication respectively as tested object; If design objective is satisfied in the communication of each link, can guarantee that then service system satisfies the stability under the high-speed cruising.
The method of testing of a kind of server high-frequency data transmission stability of the present invention, below introduce respectively to the dependence test means of each communication link and give an example:
1, communication link between test processor: utilize QPI BER test to carry out the processor data test of giving out a contract for a project; Contrast sending and receiving two ends processor test data; If deviation is bigger; It is bigger to explain that transmission link disturbs the data communication, should adopt and improve and optimizate CPU Layout circuit, the amplification of increase cpu signal is provided with and improves communication among processors;
2, test memory communication link: utilize the data communication between Rank Margin tool test processor and internal memory; The Margin value that obtains under the various memory configurations of collecting test feedback is judged the risk that the internal memory communication link exists; If the Margin value is lower; It is bigger to explain that transmission link disturbs the data communication, should adopt the Layout circuit that improves and optimizates between CPU and internal memory to improve communication;
3, test PCIE high speed expansion equipment communication link: utilize signal eye diagram to test and judge whether the PCIE signal quality passes through industrial standard; If there is the FAIL state in signal graph; It is bigger to explain that transmission link disturbs the data communication, should adopt the Layout circuit that improves and optimizates between CPU and PCIE slot to improve communication.
Except that the described technical characterictic of specification, be the known technology of those skilled in the art.
Claims (1)
1. the stability test method of server high-frequency data transmission; It is characterized in that; Come the authentication server whether can stable operation under high-frequency data transmission situation through the data transmission error rate on communication link, internal memory communication link, the PCIE high speed expansion equipment communication link between test processor; Whether through the communication error rate of test between the key node of server system medium-high frequency transfer of data process, it is reasonable to detect the server system design, and whether operation stability meets the need of market; Crucial test node comprises: communication among processors link, internal memory communication link, PCIE high speed expansion equipment communication link, wherein:
The communication among processors link nodes is responsible for the transfer of data between the processor;
Internal memory communication link node is responsible for the transfer of data between processor and the internal memory;
PCIE high speed expansion equipment communication link node is responsible for the transfer of data between processor/internal memory and the PCIE high speed expansion equipment, and concrete testing procedure is following:
1) communication link between test processor: utilize QPI BER test to carry out the processor data test of giving out a contract for a project; Contrast sending and receiving two ends processor test data; If deviation is bigger; It is bigger to explain that transmission link disturbs the data communication, should adopt and improve and optimizate CPU Layout circuit, the amplification of increase cpu signal is provided with and improves communication among processors;
2) test memory communication link: utilize the data communication between Rank Margin tool test processor and internal memory; The Margin value that obtains under the various memory configurations of collecting test feedback is judged the risk that the internal memory communication link exists; If the Margin value is lower; It is bigger to explain that transmission link disturbs the data communication, should adopt the Layout circuit that improves and optimizates between CPU and internal memory to improve communication;
3) test PCIE high speed expansion equipment communication link: utilize signal eye diagram to test and judge whether the PCIE signal quality passes through industrial standard; If there is the FAIL state in signal graph; It is bigger to explain that transmission link disturbs the data communication, should adopt the Layout circuit that improves and optimizates between CPU and PCIE slot to improve communication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210219792.2A CN102739472B (en) | 2012-06-29 | 2012-06-29 | A kind of stability test method of high-frequency data transmission for server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210219792.2A CN102739472B (en) | 2012-06-29 | 2012-06-29 | A kind of stability test method of high-frequency data transmission for server |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102739472A true CN102739472A (en) | 2012-10-17 |
| CN102739472B CN102739472B (en) | 2016-06-29 |
Family
ID=46994301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210219792.2A Active CN102739472B (en) | 2012-06-29 | 2012-06-29 | A kind of stability test method of high-frequency data transmission for server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102739472B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102932175A (en) * | 2012-10-29 | 2013-02-13 | 华为技术有限公司 | Node partition dividing method, device and server |
| CN103425582A (en) * | 2013-08-19 | 2013-12-04 | 浪潮电子信息产业股份有限公司 | QPI (Quick Path Interconnect) bus signal integrity testing method |
| CN104615518A (en) * | 2015-03-04 | 2015-05-13 | 浪潮集团有限公司 | Memory rank margin test method combining temperature and voltage variables |
| CN106452968A (en) * | 2016-10-24 | 2017-02-22 | 郑州云海信息技术有限公司 | Accelerated detection method for reliability of PCIE (Peripheral Component Interconnect Express) equipment |
| CN109165125A (en) * | 2018-08-10 | 2019-01-08 | 郑州云海信息技术有限公司 | A kind of QPI signal optimizing method, device, terminal and storage medium |
| CN112306775A (en) * | 2020-11-19 | 2021-02-02 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and medium for testing communication link between two-way CPUs (central processing unit) |
| CN114443400A (en) * | 2022-04-11 | 2022-05-06 | 飞腾信息技术有限公司 | Signal testing method and device, system on chip, electronic device and storage medium |
| CN115801203A (en) * | 2023-01-19 | 2023-03-14 | 苏州浪潮智能科技有限公司 | Distributed cluster reliability management method, device and equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030204611A1 (en) * | 2002-04-29 | 2003-10-30 | Mccosh John C. | Communications tester and method of using same |
| CN101820259A (en) * | 2010-02-08 | 2010-09-01 | 成都市华为赛门铁克科技有限公司 | Method and device for adjusting signal amplitude |
| CN101902677A (en) * | 2010-06-23 | 2010-12-01 | 中兴通讯股份有限公司 | Audio detection device and method |
| CN101908383A (en) * | 2009-06-03 | 2010-12-08 | 富士通株式会社 | Proving installation and method of testing |
| CN102315889A (en) * | 2011-09-30 | 2012-01-11 | 华为技术有限公司 | High speed signal test method, apparatus thereof and system |
-
2012
- 2012-06-29 CN CN201210219792.2A patent/CN102739472B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030204611A1 (en) * | 2002-04-29 | 2003-10-30 | Mccosh John C. | Communications tester and method of using same |
| CN101908383A (en) * | 2009-06-03 | 2010-12-08 | 富士通株式会社 | Proving installation and method of testing |
| CN101820259A (en) * | 2010-02-08 | 2010-09-01 | 成都市华为赛门铁克科技有限公司 | Method and device for adjusting signal amplitude |
| CN101902677A (en) * | 2010-06-23 | 2010-12-01 | 中兴通讯股份有限公司 | Audio detection device and method |
| CN102315889A (en) * | 2011-09-30 | 2012-01-11 | 华为技术有限公司 | High speed signal test method, apparatus thereof and system |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102932175A (en) * | 2012-10-29 | 2013-02-13 | 华为技术有限公司 | Node partition dividing method, device and server |
| WO2014067268A1 (en) * | 2012-10-29 | 2014-05-08 | 华为技术有限公司 | Node partition dividing method, device and server |
| CN102932175B (en) * | 2012-10-29 | 2016-03-09 | 华为技术有限公司 | The method of partitioning site subregion, device and server |
| CN103425582A (en) * | 2013-08-19 | 2013-12-04 | 浪潮电子信息产业股份有限公司 | QPI (Quick Path Interconnect) bus signal integrity testing method |
| CN104615518A (en) * | 2015-03-04 | 2015-05-13 | 浪潮集团有限公司 | Memory rank margin test method combining temperature and voltage variables |
| CN106452968A (en) * | 2016-10-24 | 2017-02-22 | 郑州云海信息技术有限公司 | Accelerated detection method for reliability of PCIE (Peripheral Component Interconnect Express) equipment |
| CN109165125A (en) * | 2018-08-10 | 2019-01-08 | 郑州云海信息技术有限公司 | A kind of QPI signal optimizing method, device, terminal and storage medium |
| CN112306775A (en) * | 2020-11-19 | 2021-02-02 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and medium for testing communication link between two-way CPUs (central processing unit) |
| CN112306775B (en) * | 2020-11-19 | 2023-03-14 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device, equipment and medium for testing communication link between two-way CPUs (central processing unit) |
| CN114443400A (en) * | 2022-04-11 | 2022-05-06 | 飞腾信息技术有限公司 | Signal testing method and device, system on chip, electronic device and storage medium |
| CN115801203A (en) * | 2023-01-19 | 2023-03-14 | 苏州浪潮智能科技有限公司 | Distributed cluster reliability management method, device and equipment |
| CN115801203B (en) * | 2023-01-19 | 2023-04-25 | 苏州浪潮智能科技有限公司 | Distributed cluster reliability management method, device and equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102739472B (en) | 2016-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102739472A (en) | Method for testing stability of high-frequency data transmission for server | |
| US20160352578A1 (en) | System and method for adaptive paths locator for virtual network function links | |
| US9143338B2 (en) | Position discovery by detecting irregularities in a network topology | |
| CN103929492A (en) | Method, devices and system for load balancing of service chain | |
| CN109768970A (en) | It is a kind of based on configurable puppy parc generation method | |
| US9898435B2 (en) | Aggregate baseboard management controller (BMC) controller | |
| JP6139032B2 (en) | Millimeter-wave directional link switching method, device for realizing link switching, and storage medium | |
| CN105528325A (en) | Protection method and system for high-speed transmission through standard SPI protocol | |
| CN104821957B (en) | A kind of implementation method of BFD state machines, apparatus and system | |
| US9032118B2 (en) | Administration device, information processing device, and data transfer method | |
| US20160006801A1 (en) | Data sharing system | |
| KR20160077110A (en) | Input output data alignment | |
| JP2018527869A5 (en) | ||
| CN103392304B (en) | Alarming inhibiting method and optical network device | |
| CN116010130B (en) | Cross-card link aggregation method, device, equipment and medium for DPU virtual port | |
| TWI459737B (en) | Routing analyzing apparatus and routing analyzing method thereof for use in power line communication network | |
| CN103501257A (en) | Method for selecting IP (Internet Protocol) network fault probe | |
| CN104320333B (en) | A kind of method and apparatus for detecting asymmetric static polymerization | |
| CN103856373A (en) | Web system robustness testing method based on HTTP mutation | |
| US20170070430A1 (en) | Network-on-chip flit transmission method and apparatus | |
| CN102854458B (en) | The checking method for designing of a kind of compatible high-speed and low speed layout | |
| CN103413003A (en) | Sequence transmitting device, sequence receiving device, sequence transmitting method and sequence receiving method | |
| CN108880914B (en) | Interconnection network fault detection and positioning method based on network bandwidth test | |
| CN105721234A (en) | Port aggregation method and apparatus | |
| CN104038386A (en) | Method for detecting service looped network, node and network management device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |