CN102739253A - Pipeline analog to digital circuit (ADC) structure - Google Patents
Pipeline analog to digital circuit (ADC) structure Download PDFInfo
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- CN102739253A CN102739253A CN2011100824578A CN201110082457A CN102739253A CN 102739253 A CN102739253 A CN 102739253A CN 2011100824578 A CN2011100824578 A CN 2011100824578A CN 201110082457 A CN201110082457 A CN 201110082457A CN 102739253 A CN102739253 A CN 102739253A
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Abstract
A pipeline analog to digital circuit (ADC) structure comprises two adjacent sublevels. The two sublevels share one amplifier by turns. The amplifier is used for the rear sublevel in a first timing sequence and is used for the previous sublevel in a second timing sequence. The first timing sequence is different from the second timing sequence. By using the pipeline ADC structure provided in the invention, an occupied chip area is small and power consumption is low.
Description
Technical field
The present invention relates to the analog to digital converter technical field, particularly a kind of pipeline ADC structure.
Background technology
(Analog to Digital Circuit ADC) is part important in the mixed-signal system to analog to digital converter, and in various ADC, pipeline ADC is extensively adopted in distinctive compromise advantage aspect precision, speed, power consumption and the area with it.
Please refer to Fig. 1; Fig. 1 is the structural representation of existing pipeline ADC, pipeline ADC by several sub levels 101 (STAGE1, STAGE2, STAGE3 ... .., STAGEk-1, STAGEk), time-delay SYN register array 102 and digital correction module 103 form.Please refer to Fig. 2; Fig. 2 is the sub level electrical block diagram of existing pipeline ADC; Wherein, Each sub level (STAGE1, STAGE2, STAGE3 ... .., STAGEk-1, STAGEk) include sampling hold circuit (S/H circuit) 201, sub-adc converter (SubADC) 202, subnumber weighted-voltage D/A converter (SubDAC) 203, subtracter 204 and surplus poor amplifier 205; The input of wherein said sampling hold circuit 201 links to each other as the input of said sub level 101 with the input of said sub-adc converter 202; The output of said sampling hold circuit 201 links to each other with the first input end of subtracter 204; The output of said sub-adc converter 202 links to each other with the input of subnumber weighted-voltage D/A converter 203 and the input of time-delay SYN register array 102, and the output of said subnumber weighted-voltage D/A converter 203 links to each other with second input of said subtracter 204, and the output of said subtracter 204 links to each other with the input of surplus poor amplifier 205.
Please in the lump with reference to figure 1 and Fig. 2, each sub level 101 of existing pipeline ADC alternation between sampling period and amplification cycle is accomplished analog signal conversion and is become digital signal, particularly; With i sub level (STAGEi) 200 is that example is done exemplary illustrated, and input voltage signal is at first by sampling hold circuit 201 samplings, in the sampling period; The signal of sampling is handled by the sub-adc converter among the STAGEi 202; Produce the Bi+r digit numeric code, the subnumber weighted-voltage D/A converter of sending among the STAGEi200 when this digital code is admitted to time-delay SYN register array 102 203 converts analog signal again into, and in subtracter 204, subtracts each other with original input voltage signal; The result who subtracts each other is for surplus poor; Said surplus difference signal multiply by 2r1 at surplus poor amplifier, is fed to next sub level STAGEi+1 again and handles, and this process repeats to the STAGEk level always.The Bk digit numeric codes that produce at different levels are sent into time-delay SYN register array 102 alignings of delaying time, and after digital correction module 103 is carried out correction process, export final digital code then.
But; 205 in the surplus poor amplifier of each sub level 101 of existing pipeline ADC is amplifying cycling; At sampling period pipeline ADC and cut little ice and but will consume dc power; And existing each sub level all has a surplus poor amplifier 205, and the chip area that causes pipeline ADC to take is big.
Summary of the invention
The problem that the present invention solves provides a kind of pipeline ADC structure of sharing surplus poor amplifier.
For addressing the above problem, the present invention provides a kind of pipeline ADC structure, comprising: two adjacent sub levels; Said two son levels are taken turns a shared amplifier, and said amplifier first sequential working in the back one sub level, in last sub level, and first sequential is different with second sequential in second sequential working.
Optional, said sub level comprises:
First node;
Sampling unit is used for the current potential of said first node is raised to residual error voltage;
Comparing unit is used for current potential with first node by residual error voltage amplification to the second voltage, and with said second voltage as transferring to next sub level and as its residual error voltage, said second voltage becomes the multiple relation with residual error voltage.
Optional, said multiple is 3.
Optional, shared first electric capacity of said sampling unit and comparing unit and second electric capacity.
Optional, said sampling unit comprises: first branch road and second branch road of parallel connection; Said first branch road comprises: first electric capacity of series connection and first switch; Second branch road comprises: second electric capacity and the second switch of series connection;
Said first node is between the second switch and second electric capacity;
The residual error voltage of the input voltage input previous stage of said sampling unit, the input voltage of said sampling unit is via the node place input of first branch road and the parallel connection of second branch road.
Optional, said sampling unit also comprises:
The burning voltage input, said burning voltage input is connected with second branch road with said first branch road of parallel connection via the 3rd switch, and said burning voltage input is used to import burning voltage.
The burning voltage input, said burning voltage input is connected with second branch road with said first branch road of parallel connection via the 3rd switch, and said burning voltage is used to import burning voltage.
Optional, said comparing unit comprises: reference voltage switch, first electric capacity and second electric capacity of connecting successively, the input voltage of said comparing unit is imported via said reference voltage switch.
Optional, said reference voltage number of switches is at least 1.
Optional, said reference voltage number of switches is 3.
Optional; Said reference voltage switch comprises: the first reference voltage switch, the second reference voltage switch and the 3rd reference voltage switch of parallel connection; The non-parallel connected end of the said first reference voltage switch, the second reference voltage switch and the 3rd reference voltage switch is imported first reference voltage, second reference voltage and the 3rd reference voltage input voltage as said comparing unit respectively, and said first reference voltage, second reference voltage and the 3rd reference voltage are relevant with previous stage residual error voltage.
Optional, said comparing unit also comprises: amplifier; One end of said first electric capacity links to each other with second electric capacity, one end and said link is a Section Point; Said Section Point links to each other with an end of the 4th switch, and the other end of said the 4th switch is electrically connected between said first electric capacity and said second electric capacity of connecting with the positive input terminal of amplifier via the 4th switch; First node links to each other with an end of the 5th switch, and the other end of said the 5th switch links to each other with the negative output terminal of amplifier;
In sampling unit work, said first switch, second switch, the 3rd switch closure, said reference voltage switch, the 4th switch and the 5th switch break off;
In comparing unit work, said first switch, second switch, the 3rd switch break off said reference voltage switch, the 4th switch and the 5th switch closure.
Optional, said sub level also comprises: with the mirror image sampling unit of said sampling unit mirror image symmetry and the mirror image comparing unit symmetrical with said comparing unit mirror image.
Compared with prior art; The present invention has the following advantages: the present invention takes turns a shared amplifier through adjacent two son levels; And said amplifier is used for last sub level in first sequential, be used for back one sub level in second sequential, and first sequential is different with second sequential; Improve the utilance of amplifier, reduce the power consumption of pipeline ADC structure of the present invention, further, shared first electric capacity of said sampling unit of the present invention and comparing unit and second electric capacity reduce the pipeline ADC structure and take area of chip.
Further; The sub level of pipeline ADC structure of the present invention has sampling unit, and comparing unit is with the mirror image sampling unit of said sampling unit mirror image symmetry; And with the mirror image comparing unit of said comparing unit mirror image symmetry, can reduce the error of pipeline ADC structure.
Description of drawings
Fig. 1 is the structural representation of existing pipeline ADC;
Fig. 2 is the sub level electrical block diagram of existing pipeline ADC;
Fig. 3 is the sub level sketch map of one embodiment of the invention;
Fig. 4 is the structural representation of the pipeline ADC of one embodiment of the invention.
Embodiment
Can know by background technology; The surplus poor amplifier of each sub level of existing pipeline ADC is only amplifying cycling; At sampling period pipeline ADC and cut little ice and but will consume dc power; And existing each sub level all has a surplus poor amplifier, and the chip area that causes pipeline ADC to take is big.
For this reason; Inventor of the present invention proposes a kind of pipeline ADC structure of optimization; Comprise: two adjacent sub levels, said two son levels take turns a shared amplifier, and said amplifier is used for last sub level in first sequential; Be used for back one sub level in second sequential, and first sequential is different with second sequential.
Concrete, please refer to Fig. 3, each sub level 300 comprises:
Comparing unit 303 is used for residual error voltage amplification to the second voltage, and with said second voltage as the residual error voltage transmission of next sub level to next sub level, said second voltage becomes the multiple relation with residual error voltage.
Need to prove that those skilled in the art can select concrete multiple relation according to the demand of concrete pipeline ADC structure, for example can be 3 times, 2 times, 5 times, 10 times ..., specially explain at this, should too not limit protection scope of the present invention.
Also need to prove; In the present embodiment; Shared first electric capacity of said sampling unit and comparing unit and second electric capacity realize sampling unit 302 be used for the current potential of said first node 301 is raised to the residual error voltage function; And being used for of comparing unit 303, and with the function of said second voltage as residual error voltage transmission to next sub level of next sub level with residual error voltage amplification to the second voltage.
Wherein, please refer to Fig. 4, said sampling unit 302 comprises: first branch road and second branch road parallelly connected with first branch road.
Said first branch road comprises: first switch 401, first electric capacity 501 of connecting with first switch 401.
Said second branch road comprises: second switch 402, second electric capacity 502 of connecting with second switch 402.
Said first node 603 is between the second switch 402 and second electric capacity 502.
The residual error voltage of the input voltage input previous stage of said sampling unit 302, the input voltage of said sampling unit 302 is via the node 601 places input of first branch road and the parallel connection of second branch road.
Further, said sampling unit 302 also comprises: the 3rd switch 403 that is connected with the other end of said first branch road and second branch road parallel connection.
Said sampling unit 302 comprises also and comprising: burning voltage (Vd) input; Said burning voltage input is connected with second branch road with said first branch road of parallel connection via the 3rd switch 403; Said burning voltage input input burning voltage Vd, said burning voltage Vd is used for stablizing the current potential between first electric capacity 501 and second electric capacity 502 in sample phase.
Please remain unchanged with reference to figure 4, said comparing unit 303 comprises: the reference voltage switch 700 of series connection, first electric capacity 501, second electric capacity 502 successively.
The quantity of said reference voltage switch 700 is at least 1, and in the present embodiment, said reference voltage switch 700 quantity are 3, is followed successively by the first reference voltage switch 701, the second reference voltage switch and the 3rd reference voltage switch.
As an embodiment, please refer to Fig. 4, said comparing unit 303 comprises: the first reference voltage switch 701, the second reference voltage switch 702 are parallelly connected with the 3rd reference voltage switch 703, and connect successively first electric capacity 501 and second electric capacity 502; The link of said first electric capacity 501 and second electric capacity 502 is a Section Point 602, and said Section Point 602 links to each other with an end of the 4th switch 404, and the other end of said the 4th switch 404 links to each other with the positive input terminal of amplifier 800; The other end of said second electric capacity 502 is the 3rd node 603, and said the 3rd node 603 links to each other with an end of the 5th switch 405, and the other end of said the 5th switch 405 links to each other with the negative output terminal of amplifier 800.
Concrete, when pipeline ADC arrangement works during in first sequential, first switch 401, second switch 402 and the 3rd switch 403 closures, said reference voltage switch, the 4th switch 404 and the 5th switch 405 break off; First node 601 is accepted the residual error voltage of the last sub level input of this sub level; Burning voltage (Vd) input keeps constant potential; Be 0 current potential for example, make the current potential of said first node be raised to residual error voltage, need to prove; When first sequential, amplifier 800 is operated in the amplifying unit of the adjacent back sub level 900 of this sub level.
When pipeline ADC arrangement works during in second sequential; Said first switch 401, second switch 402, the 3rd switch 403 break off; The 4th switch 404 and the 5th switch 405 closures; The first reference voltage switch 701, the second reference voltage switch 702 and the 3rd reference voltage switch 703 can be selected a closure, and residual error voltage is successively through inputing to the reference voltage switch of closure after analog-to-digital conversion and the digital-to-analogue conversion; Because when first sequential; The voltage of a pole plate of said first electric capacity 501 is residual error voltage; When second sequential; Be loaded on said first electric capacity 501 through the residual error voltage after analog-to-digital conversion and the digital-to-analogue conversion successively, make the current potential of Section Point 602 for passing through residual error voltage and the residual error voltage sum after analog-to-digital conversion and the digital-to-analogue conversion successively, promptly realize said residual error voltage and pass through analog-to-digital conversion and digital-to-analogue conversion successively after residual error voltage compare; At said residual error voltage with when comparing through the residual error voltage after analog-to-digital conversion and the digital-to-analogue conversion successively; Amplifier 800 can be supplied with electric charges to first electric capacity 501, makes the current potential of Section Point 602 be raised to pass through successively residual error voltage and residual error voltage sum after analog-to-digital conversion and the digital-to-analogue conversion; Because in first sequential; The voltage of a pole plate of said second electric capacity 502 is residual error voltage; When the current potential of Section Point 602 is raised to residual error voltage and residual error voltage sum after passing through analog-to-digital conversion and digital-to-analogue conversion successively; The current potential of the 3rd node 603 is raised to 3 times of residual error voltage, and in this process, amplifier 800 can be supplied with electric charge to second electric capacity 502; Be raised to 3 times of residual error voltage when the current potential of the 3rd node 603; Promptly accomplish amplification to said residual error voltage; Residual error voltage after the amplification is loaded on back one sub level; Need to prove, be operated in second sequential at said amplifier 800, and the sampling unit of a back sub level 900 adjacent with this sub level is in second sequential working.
Please refer to Fig. 4, said sub level comprises:
Comparing unit 303;
Mirror image sampling unit 302 ' with said sampling unit mirror image symmetry;
And the mirror image comparing unit 303 ' symmetrical with said comparing unit mirror image.
Wherein, Sampling unit 302 and comparing unit 303 can with reference to before the structure of embodiment; And the sub level that provides at present embodiment, said mirror image sampling unit 302 ' be a mirror with said sampling unit 302, said mirror image comparing unit 303 ' and said comparing unit 303 are mirror.
In existing technology; Said residual error voltage has 2 road signals: the first residual error voltage INP and the second residual error voltage INN; And the first residual error voltage INP and the second residual error voltage INN have the phase difference of 180 degree; In order to reduce the error of pipeline ADC structure, adopt in the present embodiment to comprise: sampling unit 302; Comparing unit 303; Mirror image sampling unit 302 ' with said sampling unit mirror image symmetry; And with the structure of the mirror image comparing unit 303 ' of said comparing unit mirror image symmetry; The input first residual error voltage INP in sampling unit 302 and comparing unit 303; At the 303 ' input of mirror image sampling unit 302 ' and mirror image comparing unit and the first residual error voltage INP second residual error voltage INN that spends of phasic difference 180 mutually, thereby make that the error of pipeline ADC structure is less.
The present invention takes turns a shared amplifier through adjacent two son levels, and said amplifier is used for last sub level in first sequential, be used for back one sub level in second sequential, and first sequential is different with second sequential; Improve the utilance of amplifier, reduce the power consumption of pipeline ADC structure of the present invention, further; Shared first electric capacity of said sampling unit of the present invention and comparing unit and second electric capacity; Reduce the pipeline ADC structure and take area of chip, better, the sub level of pipeline ADC structure of the present invention has sampling unit; Comparing unit; With the mirror image sampling unit of said sampling unit mirror image symmetry, and with the mirror image comparing unit of said comparing unit mirror image symmetry, can reduce the error of pipeline ADC structure.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (12)
1. pipeline ADC structure comprises:
Two adjacent sub levels;
It is characterized in that,
Said two son levels are taken turns a shared amplifier, and said amplifier first sequential working in the back one sub level, in last sub level, and first sequential is different with second sequential in second sequential working.
2. pipeline ADC structure as claimed in claim 1 is characterized in that, said sub level comprises:
First node;
Sampling unit is used for the current potential of said first node is raised to residual error voltage;
Comparing unit is used for current potential with first node by residual error voltage amplification to the second voltage, and with said second voltage as transferring to next sub level and as its residual error voltage, said second voltage becomes the multiple relation with residual error voltage.
3. pipeline ADC structure as claimed in claim 2 is characterized in that, said multiple is 3.
4. pipeline ADC structure as claimed in claim 2 is characterized in that, shared first electric capacity of said sampling unit and comparing unit and second electric capacity.
5. pipeline ADC structure as claimed in claim 4 is characterized in that, said sampling unit comprises: first branch road and second branch road of parallel connection; Said first branch road comprises: first electric capacity of series connection and first switch; Second branch road comprises: second electric capacity and the second switch of series connection;
Said first node is between the second switch and second electric capacity;
The residual error voltage of the input voltage input previous stage of said sampling unit, the input voltage of said sampling unit is via the node place input of first branch road and the parallel connection of second branch road.
6. pipeline ADC structure as claimed in claim 5 is characterized in that, said sampling unit also comprises:
The burning voltage input, said burning voltage input is connected with second branch road with said first branch road of parallel connection via the 3rd switch, and said burning voltage input is used to import burning voltage.The burning voltage input, said burning voltage input is connected with second branch road with said first branch road of parallel connection via the 3rd switch, and said burning voltage is used to import burning voltage.
7. pipeline ADC structure as claimed in claim 4 is characterized in that, said comparing unit comprises: reference voltage switch, first electric capacity and second electric capacity of connecting successively, the input voltage of said comparing unit is imported via said reference voltage switch.
8. pipeline ADC structure as claimed in claim 7 is characterized in that, said reference voltage number of switches is at least 1.
9. pipeline ADC structure as claimed in claim 8 is characterized in that, said reference voltage number of switches is 3.
10. pipeline ADC structure as claimed in claim 9; It is characterized in that; Said reference voltage switch comprises: the first reference voltage switch, the second reference voltage switch and the 3rd reference voltage switch of parallel connection; The non-parallel connected end of the said first reference voltage switch, the second reference voltage switch and the 3rd reference voltage switch is imported first reference voltage, second reference voltage and the 3rd reference voltage input voltage as said comparing unit respectively, and said first reference voltage, second reference voltage and the 3rd reference voltage are relevant with previous stage residual error voltage.
11. pipeline ADC structure as claimed in claim 8 is characterized in that said comparing unit also comprises: amplifier; One end of said first electric capacity links to each other with second electric capacity, one end and said link is a Section Point; Said Section Point links to each other with an end of the 4th switch, and the other end of said the 4th switch is electrically connected between said first electric capacity and said second electric capacity of connecting with the positive input terminal of amplifier via the 4th switch; First node links to each other with an end of the 5th switch, and the other end of said the 5th switch links to each other with the negative output terminal of amplifier;
In sampling unit work, said first switch, second switch, the 3rd switch closure, said reference voltage switch, the 4th switch and the 5th switch break off;
In comparing unit work, said first switch, second switch, the 3rd switch break off said reference voltage switch, the 4th switch and the 5th switch closure.
12. pipeline ADC structure as claimed in claim 2 is characterized in that, said sub level also comprises: with the mirror image sampling unit of said sampling unit mirror image symmetry and the mirror image comparing unit symmetrical with said comparing unit mirror image.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112398474A (en) * | 2020-11-23 | 2021-02-23 | 天津大学合肥创新发展研究院 | Working method of multistage Cyclic ADC |
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| CN112398474A (en) * | 2020-11-23 | 2021-02-23 | 天津大学合肥创新发展研究院 | Working method of multistage Cyclic ADC |
| CN112398474B (en) * | 2020-11-23 | 2023-08-08 | 天津大学合肥创新发展研究院 | Working method of multistage Cyclic ADC |
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