CN102739196B - Multichannel parallel input/output digital smoothing filter and implementation method thereof - Google Patents

Abstract

The invention discloses a multichannel parallel input/output digital smoothing filter and an implementation method thereof, relating to high-speed parallel digital signal processing in an optical communication system. The filter comprises an interchannel accumulator, N parallel channels and a shift register Z-1 of which the time delay is 1; the interchannel accumulator comprises N input ports and N output ports; and the N output ports are connected with the N parallel channels. The implementation method of the filter comprises the following steps: enabling N paths of signals to enter the interchannel accumulator; calculating the interchannel accumulation of all channels; subtracting the signal of the shift register Z-m of which the time delay is m from each path of output of the interchannel accumulator; inputting the result in a connected adder; and for the first to the (N-1)-th pathes of signals, calculating the output value of the filter corresponding to the channel by using the output value of the filter of the N-th path of signals corresponding to the previous period. The multichannel parallel input/output digital smoothing filter and the implementation method thereof reduce the amount of calculation between channel channels through recursive algorithm based on a special design, thereby reducing the resource consumption of hardware and improving the running speed.

Description

Multi-channel parallel input and output digital smoothing filter and its implementation

Technical field

The present invention relates to optical communication system high speed parallel digital signal process field, particularly relate to a kind of multi-channel parallel input and output digital smoothing filter and its implementation.

Background technology

In Modern High-Speed optical communication system, smoothing filter is the extremely important part of electric signal process part, and in frame synchronization, Frequency offset estimation and light phase noise all need to calculate the moving average of certain window length in estimating.Due to current techniques restriction, the speed of Digital Signal Processing can only reach hundreds of MHz, with respect to the transmission speed of the upper GHz of light transmission, must carry out parallel processing to signal at signal process part, and traditional smoothing filter is all realized on single channel, in parallel system, need to consume a large amount of hardware resources if be grafted directly to.

Summary of the invention

The object of the invention is the deficiency in order to overcome above-mentioned background technology, a kind of multi-channel parallel input and output digital smoothing filter and its implementation are provided, reduce the amount of calculation between parallel channel by the recursive algorithm of particular design, can reduce hardware resource consumption and improve the speed of service.

Multi-channel parallel input and output digital smoothing filter provided by the invention, it comprises interchannel accumulator, a N parallel channel and a shift register Z that time delay is 1 ^-1, the positive integer that N is 2 time power, interchannel accumulator comprises N parallel input port and N parallel output port, the N of interchannel accumulator parallel output port is connected with N parallel channel respectively; The internal structure of a described N parallel channel is identical, and each parallel channel comprises the shift register Z that a time delay is m ^-m, subtracter and an adder, each subtracter comprises a minuend input port, a subtrahend input port and an output port, each adder comprises two input ports and an output port, the shift register Z in same passage ^-minput port and the minuend input port of subtracter be all connected with the corresponding output port of interchannel accumulator, shift register Z ^-moutput port be connected with the subtrahend input port of the subtracter in same passage, the output port of subtracter is connected with an input port of the adder in same passage, another input port of the adder in all passages all with the time delay shift register Z that is 1 ^-1output port be connected, output port and the shift register Z of adder in passage N ^-1input port be connected, the output port of adder is the output port of multi-channel parallel input and output digital smoothing filter in passage N.

On the basis of above-mentioned multi-channel parallel input and output digital smoothing filter, the present invention also provides a kind of implementation method of multi-channel parallel input and output digital smoothing filter, comprise the following steps: N road input signal Input1～InputN is accumulator between admission passage simultaneously, calculate the interchannel cumulative sum that all passages are corresponding, each road output signal of interchannel accumulator and its shift register Z that is m through time delay ^-moutput signal carry out subtraction, and by the next connected adder of result input of this subtraction, the 1st Zhi N-1 road signal use its previous cycle the filter output value of corresponding N road signal, calculate the corresponding filter output value of the 1st Zhi N-1 road signalling channel.

In technique scheme, for one group of serial input signals IN (n), the single channel serial input smoothing filter output valve that its right length is L is:

$\mathrm{OUT}\left(n\right)=\frac{1}{L}\underset{t=n}{\overset{n+L-1}{\mathrm{\Σ}}}\mathrm{IN}\left(t\right);$

Wherein: L is length of window, n is input time, and L, n are positive integer, and OUT (n) is smoothing filter output valve corresponding to signal IN (n) of inputting in the n moment, is the mean value of input signal in L clock.

In technique scheme, described single channel serial input smoothing filter output valve through the signal after 1:N deserializer changing down is:

INp(t _i，c _i)＝IN((t _i-1)·N+c _i)，

Wherein: t _ifor representing the positive integer of signal INp output time, c _ifor representing the positive integer of signal INp output channel sequence number, c _ispan is 1 to N.

In technique scheme, described length of window is the integral multiple of parallel signal way.

In technique scheme, the smoothing filter that is mN for a length of window, the output of corresponding each input signal INp adopts recurrence formula to calculate:

$\mathrm{OUT}(t_i,c_i)=\frac{1}{m\·N}\·(\underset{t=t_i}{\overset{t_i+m-1}{\mathrm{\Σ}}}\underset{c=1}{\overset{N}{\mathrm{\Σ}}}\mathrm{INp}(t,c)-\underset{c=1}{\overset{c_i}{\mathrm{\Σ}}}\mathrm{INp}(t_i,c)+\underset{c=1}{\overset{c_i}{\mathrm{\Σ}}}\mathrm{INp}(t_j,c))$

Wherein: N is parallel channel quantity, m is the multiple of the corresponding N of length of window, and m is positive integer, t _ifor signal to be calculated some input time, c _ifor signal to be calculated place channel position, span is the positive integer from 1 to N, t _jfor t _ithe positive integer of+m.

In technique scheme, N road signal is at t _imoment is parallel input smoothing filter simultaneously, for the arbitrary passage c in 1～N parallel channel now _iinput signal INp (t _i, c _i), its corresponding output signal is OUT (t _i, c _i), the same clock cycle of interchannel accumulator computes is interior from channel 1 to all parallel channel c _icumulative sum c _ibe the positive integer of 1～N, in described recurrence formula Section 1 multinomial be N output channel of accumulator within m cycle and:

In technique scheme, input signal S (t, N) and its shift register Z that is m through a time delay ^-moutput signal carry out subtraction, and by the next connected adder of poor input of this subtraction, the shift register Z that the other end of this adder and output port are 1 by a time delay ^-1be connected, the output port of this adder is the represented computing of Section 1 in described recurrence formula, and in described recurrence formula, latter two are respectively at t _iwith t _ithe output valve of the arbitrary same channels of accumulator between+m moment respective channels, the difference of two is by a subtracter and a shift register Z that time delay is m ^-mrealize.

Compared with prior art, advantage of the present invention is as follows:

The present invention has reduced the amount of calculation between parallel channel by the recursive algorithm of particular design, can reduce hardware resource consumption and improve the speed of service, and being applicable to length of window is parallel channel number integer situation doubly.

Brief description of the drawings

Fig. 1 is the structural representation of embodiment of the present invention median filter.

Fig. 2 is the recursive algorithm the general frame adopting in the embodiment of the present invention.

Fig. 3 is the recursive algorithm schematic diagram adopting in the embodiment of the present invention.

Fig. 4 is N the recursive algorithm schematic diagram that parallel channel adopts in the filter of the embodiment of the present invention.

Embodiment

Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.

Shown in Figure 1, the embodiment of the present invention provides a kind of multi-channel parallel input and output digital smoothing filter, comprises interchannel accumulator, a N parallel channel and a shift register Z that time delay is 1 ^-1, N is desirable any positive integer in theory, is generally taken as 2 positive integer time power in reality.Interchannel accumulator comprises N parallel input port and N parallel output port, and the N of interchannel accumulator parallel output port is connected with N parallel channel respectively.

Shown in Figure 1, the internal structure of N parallel channel is identical, and each parallel channel comprises the shift register Z that a time delay is m ^-m, subtracter and an adder, each subtracter comprises a minuend input port, a subtrahend input port and an output port, each adder comprises two input ports and an output port, the shift register Z in same passage ^-minput port and the minuend input port of subtracter be all connected with the corresponding output port of interchannel accumulator, shift register Z ^-moutput port be connected with the subtrahend input port of the subtracter in same passage, the output port of subtracter is connected with an input port of the adder in same passage, another input port of the adder in all passages all with the time delay shift register Z that is 1 ^-1output port be connected, output port output1 and the shift register Z of adder in passage N ^-1input port be connected, the output port of adder is the output port of multi-channel parallel input and output digital smoothing filter in passage N.

Shown in Figure 1, the implementation method of above-mentioned multi-channel parallel input and output digital smoothing filter is as follows:

N road input signal Input1～InputN is accumulator between admission passage simultaneously, calculates the interchannel cumulative sum that all passages are corresponding, each road output signal of interchannel accumulator and its shift register Z that is m through time delay ^-moutput signal carry out subtraction, and by the next connected adder of result input of this subtraction, the 1st Zhi N-1 road signal use its previous cycle the filter output value of corresponding N road signal, calculate the corresponding filter output value of the 1st Zhi N-1 road signalling channel.

Shown in Figure 2, for one group of serial input signals IN (n) (n is input time), the single channel serial input smoothing filter output valve that its right length is L can be expressed as:

$\mathrm{OUT}\left(n\right)=\frac{1}{L}\underset{t=n}{\overset{n+L-1}{\mathrm{\Σ}}}\mathrm{IN}\left(t\right);$ (formula 1.1)

Formula 1.1 has been described the mathematic(al) representation of the single channel serial input smoothing filter output valve that length of window is L, L, n are positive integer, OUT (n) is smoothing filter output valve corresponding to signal IN (n) of inputting in the n moment, is the mean value of input signal in L clock.

Above-mentioned single channel serial input smoothing filter output valve can be expressed as through the signal after 1:N deserializer changing down at it:

INp (t _i, c _i)=IN ((t _i-1) N+c _i) (formula 1.2)

In optical communication system, due to the restriction of Contemporary Digital chip processing speed, pending high-speed digital signal must pass through 1:N deserializer, is converted into low rate and processes.Formula 1.2 has been described the relation of parallel digital signal INp and the former serial signal IN of the generation after 1:N deserializer, t _ifor representing the positive integer of signal INp output time, c _ifor representing the positive integer of signal INp output channel sequence number, c _ispan is 1 to N.

Can not affect owing to increasing within the specific limits or reducing the length of window of smoothing filter the function that noise is eliminated that smoothing filter plays, therefore in the parallel digital signal system after deserializer as described above, in order to reduce the complexity of computing, can selection window length be the integral multiple of parallel signal way.

The smoothing filter that is mN for a length of window (m is any positive integer), the output of corresponding each input signal INp (in black solid box all signals and) recursion method described of available formula 1.3 below calculates:

$\mathrm{OUT}(t_i,c_i)=\frac{1}{m\·N}\·(\underset{t=t_i}{\overset{t_i+m-1}{\mathrm{\Σ}}}\underset{c=1}{\overset{N}{\mathrm{\Σ}}}\mathrm{INp}(t,c)-\underset{c=1}{\overset{c_i}{\mathrm{\Σ}}}\mathrm{INp}(t_i,c)+\underset{c=1}{\overset{c_i}{\mathrm{\Σ}}}\mathrm{INp}(t_j,c))$

(formula 1.3)

In formula 1.3: N is parallel channel quantity, m is the multiple (positive integer) of the corresponding N of length of window, t _ifor signal to be calculated some input time, c _ifor signal to be calculated place channel position (span is the positive integer from 1 to N), t _jfor t _ithe positive integer of+m.

Describe the described recursion method of formula 1.3 below in detail.

Shown in Figure 2, N road signal is at t _imoment is parallel input smoothing filter simultaneously, for the arbitrary passage c carving at this moment in 1～N parallel channel _iinput signal INp (t _i, c _i), its corresponding output signal can be expressed as OUT (t _i, c _i), the mean value that in Fig. 2, black solid box part comprises signal, because length of window is definite value, so its output signal can be directly by signal read group total in black solid box.

Above-mentioned summation process can be expressed as again described three the polynomial relations of formula 1.3 and carry out computing: shown in Figure 3, first use in the same clock cycle of interchannel accumulator computes from channel 1 to all parallel channel c _i(c _ibe the positive integer of 1～N) cumulative sum afterwards in formula 1.3 Section 1 multinomial can be exchanged into N output channel of accumulator within m cycle and:

The corresponding recursive algorithm of said process is shown in Figure 4: first input signal S (t, N) and its shift register Z that is m through a time delay ^-moutput signal carry out subtraction, and by the next connected adder of poor input of this subtraction, the shift register Z that the other end of this adder and output port are 1 by a time delay ^-1be connected, the output port of this adder is the represented computing of Section 1 in formula 1.3, and in formula 1.3, latter two are respectively at t _iwith t _ithe output valve of the arbitrary same channels of accumulator between+m moment respective channels, and this difference of two can be by a subtracter and a shift register Z that time delay is m ^-mrealize.

Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention comprises these changes and modification interior.The content not being described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.

Claims (8)

1. a multi-channel parallel input and output digital smoothing filter, is characterized in that: it comprises interchannel accumulator, a N parallel channel and a shift register Z that time delay is 1 ^-1, the positive integer that N is 2 time power, interchannel accumulator comprises N parallel input port and N parallel output port, the N of interchannel accumulator parallel output port is connected with N parallel channel respectively; The internal structure of a described N parallel channel is identical, and each parallel channel comprises the shift register Z that a time delay is m ^-m, subtracter and an adder, each subtracter comprises a minuend input port, a subtrahend input port and an output port, each adder comprises two input ports and an output port, the shift register Z in same passage ^-minput port and the minuend input port of subtracter be all connected with the corresponding output port of interchannel accumulator, shift register Z ^-moutput port be connected with the subtrahend input port of the subtracter in same passage, the output port of subtracter is connected with an input port of the adder in same passage, another input port of the adder in all passages all with the time delay shift register Z that is 1 ^-1output port be connected, output port and the shift register Z of adder in passage N ^-1input port be connected, the output port of adder is the output port of multi-channel parallel input and output digital smoothing filter in passage N.

2. the implementation method based on multi-channel parallel input and output digital smoothing filter claimed in claim 1, it is characterized in that comprising the following steps: N road input signal Input1～InputN is accumulator between admission passage simultaneously, calculate the interchannel cumulative sum that all passages are corresponding, each road output signal of interchannel accumulator and its shift register Z that is m through time delay ^-moutput signal carry out subtraction, and by the next connected adder of result input of this subtraction, the 1st Zhi N-1 road signal use its previous cycle the filter output value of corresponding N road signal, calculate the corresponding filter output value of the 1st Zhi N-1 road signalling channel.

3. the implementation method of multi-channel parallel input and output digital smoothing filter as claimed in claim 2, it is characterized in that: for one group of serial input signals IN (n), the single channel serial input smoothing filter output valve that its right length is L is:

Wherein: L is length of window, n is input time, and L, n are positive integer, and OUT (n) is smoothing filter output valve corresponding to signal IN (n) of inputting in the n moment, is the mean value of input signal in L clock.

4. the implementation method of multi-channel parallel input and output digital smoothing filter as claimed in claim 3, is characterized in that: described single channel serial input smoothing filter output valve through the signal after 1:N deserializer changing down is:

INp(t _i，c _i)＝IN((t _i-1)·N+c _i)，

Wherein: t _ifor representing the positive integer of signal INp output time, c _ifor representing the positive integer of signal INp output channel sequence number, c _ispan is 1 to N.

5. the implementation method of multi-channel parallel input and output digital smoothing filter as claimed in claim 4, is characterized in that: described length of window is the integral multiple of parallel signal way.

6. the implementation method of multi-channel parallel input and output digital smoothing filter as claimed in claim 5, is characterized in that: the smoothing filter that is mN for a length of window, and the output of corresponding each input signal INp adopts recurrence formula to calculate:

；

Wherein: N is parallel channel quantity, m is the multiple of the corresponding N of length of window, and m is positive integer, t _ifor signal to be calculated some input time, c _ifor signal to be calculated place channel position, span is the positive integer from 1 to N, t _jfor t _ithe positive integer of+m.

7. the implementation method of multi-channel parallel input and output digital smoothing filter as claimed in claim 6, is characterized in that: N road signal is at t _imoment is parallel input smoothing filter simultaneously, for the arbitrary passage c in 1～N parallel channel now _iinput signal INp (t _i, c _i), its corresponding output signal is OUT (t _i, c _i), the same clock cycle of interchannel accumulator computes is interior from channel 1 to all parallel channel c _icumulative sum c _ibe the positive integer of 1～N, in described recurrence formula Section 1 multinomial be N output channel of accumulator within m cycle and:

8. the implementation method of multi-channel parallel input and output digital smoothing filter as claimed in claim 7, is characterized in that: input signal S (t, N) and its shift register Z that is m through a time delay ^-moutput signal carry out subtraction, and by the next connected adder of poor input of this subtraction, the shift register Z that the other end of this adder and output port are 1 by a time delay ^-1be connected, the output port of this adder is the represented computing of Section 1 in described recurrence formula, and in described recurrence formula, latter two are respectively at t _iwith t _ithe output valve of the arbitrary same channels of accumulator between+m moment respective channels, the difference of two is by a subtracter and a shift register Z that time delay is m ^-mrealize.