CN102737994A - Method for manufacturing semiconductor device - Google Patents
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- CN102737994A CN102737994A CN2011100819688A CN201110081968A CN102737994A CN 102737994 A CN102737994 A CN 102737994A CN 2011100819688 A CN2011100819688 A CN 2011100819688A CN 201110081968 A CN201110081968 A CN 201110081968A CN 102737994 A CN102737994 A CN 102737994A
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Abstract
The invention relates to a method for manufacturing a semiconductor device, comprising the steps of: a) providing a substrate, forming a gate dielectric layer on the substrate, forming a dummy gate on the gate dielectric layer, and forming an etch stop layer covering the gate dielectric layer and the dummy gate; b) forming a pre-metal dielectric layer on a front-end device layer structure; c) planarizing the pre-metal dielectric layer until the upper surface of the dummy gate is exposed; d) removing the dummy gate to form an opening for accommodating a metal gate; e) forming a photoresist layer within the opening and on the surface of the pre-metal dielectric layer; f) planarizing the photoresist layer and the protruding etch stop layer; g) removing the photoresist layer within the opening; and h) forming a metal gate within the opening. The method, after the dummy gate is removed, can help effectively reduce dishing phenomenon in dense areas, overcome the defects caused by residue of metal used for forming gates and reduction on the thickness of gates, and improve performance of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly, the present invention relates to a kind of manufacturing approach with semiconductor device of metal gates.
Background technology
Grid has the minimum physical size in the semiconductor fabrication process usually, and its width critical dimension (CD) of most critical on the wafer normally, and therefore the making of grid is one of step of most critical in the flow process in fabrication of semiconductor device.
Because that polycrystalline silicon material has is high temperature resistant, can stop that injecting the atom mixed with ion gets into advantages such as channel region, so, when making typical metal oxide semiconductor transistor, can use polycrystalline silicon material to make transistorized grid usually.But polysilicon gate has higher resistance value, is easy to generate depletion effects and boron penetration to channel region etc.And, along with the metal oxide semiconductor transistor device size continue dwindle, adopt metal gates to replace conventional polysilicon gate usually.
Figure 1A-1E makes the cutaway view of each step of semiconductor device for last grid (Gate-last) technology that adopts prior art.Shown in Figure 1A, at first, substrate 101 is provided, on substrate 101, define device active region and form shallow trench isolation and leave.Then, on substrate 101, form gate dielectric layer 102.Said gate dielectric layer is selected for use usually has high dielectric constant materials.Then, on gate dielectric layer 102, form dummy grid 103, and carry out ion injection and high-temperature annealing process formation regions and source.Then, on dummy grid 103 and regions and source, form etching stopping layer 104.Said etching stopping layer adopts silicon nitride usually.Shown in Figure 1B, dielectric layer (PMD) 105 before the formation metal on said etching stopping layer 104, dielectric layer adopts oxide usually before the said metal.Shown in Fig. 1 C, then, carry out cmp (CMP) technology, until the upper surface that exposes dummy grid 103.Shown in Fig. 1 D, remove dummy grid 103, be formed for holding the opening 106 of metal gates.Then, in said opening 106 and before the said metal, form metal material layer on the dielectric layer, then carry out cmp (CMP) technology and in said opening, form metal gates, said metal gates adopts metallic aluminium usually.
Usually, adopt nitride and oxide main material respectively as dielectric layer 105 before etching stop layer 104 and the metal.Therefore yet oxide hardness with respect to nitride is little, and in the chemical mechanical milling tech process, oxide consumes more, therefore can produce dish effect (dishing) and form depression (shown in Fig. 1 C) on the surface.The degree of depth that should cave in usually is only less than 30 dusts.But; Remove in the process at follow-up dummy grid; Use hydrofluoric acid (DHF) cleaning agent of for example dilution to remove at the epontic native oxide of dummy grid (native OX); It can make said dish phenomenon further worsen, and the degree of depth of said depression further enlarges, and it is right to reach 100 Izods usually.This can produce very big influence to subsequent technique, for example causes leakage current increase etc.The more important thing is that it can cause when subsequent handling is filled metal with the formation metal gates, the residual metal that is used to form metal gates in depression.Prior art adopted grinding (over polishing) technology to remove the kish in the said depression usually, but can bring said metal gates thickness to reduce and a series of problem such as metal gates surface dishization.
Summary of the invention
In order to overcome the shortcoming of above-mentioned prior art, the present invention proposes the method that effectively lowers the dish effect in a kind of grid technique in the end.
A kind of manufacturing approach of semiconductor device comprises:
A) provide substrate, forming gate dielectric layer on the said substrate, on said gate dielectric layer, forming dummy grid and form to cover said gate dielectric layer and the etching stop layer of said dummy grid;
B) on said etching stopping layer, form dielectric layer before the metal;
C) the preceding dielectric layer of the said metal of planarization is to the upper surface that exposes said dummy grid;
D) remove said dummy grid, to be formed for holding the opening of metal gates;
E) form photoresist layer on the surface of dielectric layer in said opening and before the metal;
F) said photoresist layer of planarization and outstanding etching stopping layer;
G) remove the interior said photoresist layer of said opening;
H) in said opening, form metal gates.
What said planarisation step adopted is CMP technology.
The thickness of said photoresist layer is 200 ~ 1500 dusts.
The thickness of said photoresist layer is 500 ~ 800 dusts.
Said etching stop layer is a silicon nitride layer.
Dielectric layer is an oxide skin(coating) before the said metal.
The material of said dummy grid is a polysilicon.
In step f), the grinding selectivity ratio of dielectric layer before said etching stop layer and the said metal is set at greater than 1.
The material of said metal gates is a metallic aluminium.
Said gate dielectric layer is silicon nitride or silica.
Said gate dielectric layer is the high dielectric constant material layer.
Also be included between sidewall and the said etching stopping layer of said dummy grid and form side wall layer.
Said metal gates comprises tungsten, titanium nitride, tantalum, tantalum nitride or copper.
In step d), also comprise and use cleaning agent to remove the step that is grown in the surperficial native oxide layer of dummy grid.Said cleaning agent is the hydrofluoric acid of dilution.
In sum, method of the present invention can reduce the dish phenomenon of compact district effectively after removing dummy grid, and then has overcome the defective that the attenuating of the residual and gate of the metal that is used to form grid causes, thereby has promoted the performance of semiconductor device.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A ~ 1D is depicted as the cutaway view that the Gate-last technology that adopts prior art forms each step in the semiconductor device process;
Fig. 2 A-2G shows the cutaway view of making each step in the semiconductor device process according to the preferred embodiment of the present invention;
Fig. 3 is according to preferred embodiment for the present invention methods of making semiconductor devices flow chart.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
Now, will describe in more detail according to exemplary embodiment of the present invention with reference to accompanying drawing.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as the embodiment that is only limited to here to be set forth.Should be understood that, provide these embodiment of the present inventionly to disclose thoroughly and complete, and the design of these exemplary embodiments fully conveyed to those of ordinary skills in order to make.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and used the identical Reference numeral to represent components identical, thereby will omit description of them.
At first, specify the methods of making semiconductor devices of the preferred embodiment for the present invention with reference to figure 2A-2G.
Shown in Fig. 2 A; Substrate 201 is provided, and said substrate 201 can be at least a in the following material of mentioning: silicon, silicon-on-insulator (SOI), insulator laminated silicon (SSOI), insulator laminated SiGe (S-SiGeOI), germanium on insulator silicon (SiGeOI) and germanium on insulator (GeOI).On substrate 201, define device active region and form shallow trench isolation and leave.Then, on substrate 201, form gate dielectric layer 202.Said gate dielectric layer select for use usually this area commonly used have a high dielectric constant materials, hafnium oxide etc. for example.Then, on gate dielectric layer 202, form dummy grid 203, said dummy grid adopts polycrystalline silicon material usually, carries out ion injection and high-temperature annealing process and forms regions and source.Then, on dummy grid 203 and regions and source, form etching stopping layer 204.Said etching stopping layer adopts nitride usually, silicon nitride for example, and its thickness is about 200 ~ 400 dusts.In addition, between the sidewall of dummy grid 203 and said etching stop layer 204, can also be formed with side wall layer.
Shown in Fig. 2 B, dielectric layer (PMD) 205 before the formation metal on said etching stopping layer 204.Its thickness is 1000 ~ 6000 dusts, is used to make between upper metal layers and the substrate insulate.Can adopt PECVD (plasma enhanced CVD), SACVD (inferior normal pressure chemical vapor deposition) or LPCVD technologies such as (low-pressure chemical vapor phase depositions) to form the preceding dielectric layer 205 of metal.The material of dielectric layer 205 is generally oxide before the metal, for example silica.Preferably; For the leakage current that reduces integrated circuit, reduce capacity effect between the lead, reduce integrated circuit heating etc.; The material of dielectric layer 205 can also be selected the material with low-k for use before the metal; For example black diamond (Black Diamond, BD) or unadulterated silica (USG) etc.
Shown in Fig. 2 C, dielectric layer 205 is to the upper surface that exposes dummy grid 203 before the planarization material.
Adopt cmp (CMP) to carry out said planarization operation.When carrying out said planarization operation, but synchronous operation end-point detecting system (EPD), so that process of lapping is monitored in real time.
Shown in Fig. 2 D, remove dummy grid 203 through etching, to be formed for holding the opening 206 of metal gates.Can utilize dry etching or wet etching to remove said dummy grid 203.And preferably, before removing dummy grid 203, remove native oxide (native OX) layer that is grown in dummy grid 203 surfaces with the cleaning agent of the for example hydrofluoric acid of dilution earlier.
Shown in Fig. 2 E, form photoresist layer 208 on the surface of dielectric layer 205 in opening 206 and before the metal after the planarization.Wherein, the thickness of this photoresist layer is 200 ~ 1500 dusts, is preferably 500 to 800 dusts.
Shown in Fig. 2 F, carry out CMP technology polishing said outstanding etching stopping layer and photoresist layer, and then reduce because the depression that the dish phenomenon of the preceding dielectric layer of said metal forms.Wherein, In order to guarantee when CMP grinds; Remove outstanding etching stop layer 204 as quickly as possible; Dielectric layer (PMD) 205 before the loss metal of trying one's best few simultaneously, described CMP technology has following characteristics, and promptly the grinding selectivity ratio to dielectric layer 205 before said etching stop layer 204 and the said metal is greater than 1.Then remove the said photoresist in the said opening 206.
Shown in Fig. 2 G, in said opening 206 and before the metal, form metal material layer on the dielectric layer surface, then carry out cmp (CMP) technology and in said opening, form metal gates 207.The material of metal gates can select to have the material of excellent polishing characteristic, for example tungsten, titanium nitride, tantalum, aluminium, tantalum nitride or copper.Be preferably aluminum or aluminum alloy.Under preferred especially situation, grid electrode layer is followed successively by titanium aluminide and aluminium from bottom to top.
Below with reference to Fig. 3, to being elaborated according to preferred embodiment for the present invention methods of making semiconductor devices.In step S301, substrate is provided, is forming gate dielectric layer on the said substrate, on said gate dielectric layer, form dummy grid and forming the etching stop layer that covers said gate dielectric layer and said dummy grid.In step S302, dielectric layer before the formation metal on said etching stopping layer.In step S303, dielectric layer is to the upper surface that exposes said dummy grid before the said metal of planarization.In step S304, remove said dummy grid, to be formed for holding the opening of metal gates.In step S305, form photoresist layer on the surface of dielectric layer in said opening and before the metal.In step S306, dielectric layer before the metal after planarization photoresist layer and outstanding etching stopping layer to the planarization is removed the photoresist in the opening.In step S307, in opening, fill metal material, to form metal gates.
Method of the present invention can reduce the dish phenomenon of compact district effectively after removing dummy grid, and then has overcome the defective that the attenuating of the residual and gate of the metal that is used to form grid causes, thereby has promoted the performance of semiconductor device.
Those skilled in the art know, and above-mentioned formation method includes but are not limited to deposition, plating, sputter and absorbing process; Above-mentioned lithographic method comprises dry etching method and wet etching method; Above-mentioned doping method includes but are not limited to ion implantation technology.Those skilled in the art can select suitable method according to actual conditions.Those skilled in the art know, and in order to reach better effect, possibly also have other layers structure such as etching stop layer etc. between above-mentioned each layer structure, but concise and to the point in order to describe, and are not described in detail at this.Can also be with well known to a person skilled in the art that any means forms above-mentioned various layer structure, various through hole or other structures.Further it will be appreciated that, when mention certain one deck be positioned at another layer or substrate " on ", when D score or " surface ", this layer can be located immediately at another layer or substrate " on " or D score, also the intermediate layer can appear therebetween perhaps.
Semiconductor device according to aforesaid execution mode manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products; In various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (15)
1. the manufacturing approach of a semiconductor device comprises:
A) provide substrate, forming gate dielectric layer on the said substrate, on said gate dielectric layer, forming dummy grid and form to cover said gate dielectric layer and the etching stop layer of said dummy grid;
B) on said etching stopping layer, form dielectric layer before the metal;
C) the preceding dielectric layer of the said metal of planarization is to the upper surface that exposes said dummy grid;
D) remove said dummy grid, to be formed for holding the opening of metal gates;
E) form photoresist layer on the surface of dielectric layer in said opening and before the metal;
F) said photoresist layer of planarization and outstanding etching stopping layer;
G) remove the interior said photoresist layer of said opening;
H) in said opening, form metal gates.
2. method according to claim 1 is characterized in that, what said planarisation step adopted is CMP technology.
3. method according to claim 1 is characterized in that, the thickness of said photoresist layer is 200 ~ 1500 dusts.
4. method according to claim 3 is characterized in that, the thickness of said photoresist layer is 500 ~ 800 dusts.
5. method according to claim 1 is characterized in that, said etching stop layer is a silicon nitride layer.
6. method according to claim 1 is characterized in that, dielectric layer is an oxide skin(coating) before the said metal.
7. method according to claim 1 is characterized in that, the material of said dummy grid is a polysilicon.
8. method according to claim 1 is characterized in that, in step f), the grinding selectivity ratio of dielectric layer before said etching stop layer and the said metal is set at greater than 1.
9. method according to claim 1 is characterized in that, the material of said metal gates is a metallic aluminium.
10. method according to claim 1 is characterized in that, said gate dielectric layer is silicon nitride or silica.
11. method according to claim 1 is characterized in that, said gate dielectric layer is the high dielectric constant material layer.
12. method according to claim 1 is characterized in that, also is included between sidewall and the said etching stopping layer of said dummy grid and forms side wall layer.
13. method according to claim 1 is characterized in that, said metal gates comprises tungsten, titanium nitride, tantalum, tantalum nitride or copper.
14. method according to claim 1 is characterized in that, in step d), also comprises using cleaning agent to remove the step that is grown in the surperficial native oxide layer of dummy grid.
15. method according to claim 14 is characterized in that, said cleaning agent is the hydrofluoric acid of dilution.
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| CN201110081968.8A CN102737994B (en) | 2011-04-01 | 2011-04-01 | Method for manufacturing semiconductor device |
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| CN102737994B CN102737994B (en) | 2015-02-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952714A (en) * | 2014-03-24 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281082B1 (en) * | 2000-03-13 | 2001-08-28 | Chartered Semiconductor Manufacturing Ltd. | Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill |
| US20040198009A1 (en) * | 2001-07-16 | 2004-10-07 | Taiwan Semiconductor Manufacturing Company | Selective formation of metal gate for dual gate oxide application |
| CN101626022A (en) * | 2008-07-09 | 2010-01-13 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN101872742A (en) * | 2009-04-22 | 2010-10-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281082B1 (en) * | 2000-03-13 | 2001-08-28 | Chartered Semiconductor Manufacturing Ltd. | Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill |
| US20040198009A1 (en) * | 2001-07-16 | 2004-10-07 | Taiwan Semiconductor Manufacturing Company | Selective formation of metal gate for dual gate oxide application |
| CN101626022A (en) * | 2008-07-09 | 2010-01-13 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN101872742A (en) * | 2009-04-22 | 2010-10-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952714A (en) * | 2014-03-24 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN104952714B (en) * | 2014-03-24 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
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