CN102737270A - Security co-processor of bank smart card chip based on domestic algorithms - Google Patents
Security co-processor of bank smart card chip based on domestic algorithms Download PDFInfo
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Abstract
The invention disclosed a security co-processor of a bank smart card chip based on domestic algorithms. The security co-processor comprises a storage unit, a control module, an SM1 algorithm module, an SM2 algorithm module, an SM3 algorithm module, and a modular multiplication module, wherein the storage unit is used for enabling and controlling the SM1 algorithm module, the SM2 algorithm module, the SM3 algorithm module, and the modular multiplication module, and inputting and outputting data. When one function module of the SM1 algorithm module, the SM2 algorithm module, the SM3 algorithm module, and the modular multiplication module is enabled, a data and address output end is used as an input end of the control module, and data is written into a specified address space of the storage unit through the output end of the control module according to an address. A comprehensive hardware solidification of state encryption SM1, SM2, SM3 and sub-functions is completed by adopting the security co-processor of the invention which has the characteristics of faster speed and higher security compared with a software method and a software-hardware combination method.
Description
Technical field
The present invention relates to field of information security technology, particularly be a kind of security coprocessor of the bank intelligent card chip based on homemade algorithm SM1, SM2 and SM3 algorithm.
Background technology
At present; Domestic bank card mainly uses magnetic stripe card; But there is tangible deficiency: information storage is little, magnetic stripe is prone to read and forgery, confidentiality are poor, is stolen the data on the magnetic stripe by the offender easily, duplicates puppet simultaneously and emits the cost of card lower; Cause the various crime cases that relate to the magnetic stripe card security frequently to take place, the safety problem of bank card causes that day by day the holder worries.
State's close SM1 SM2 SM3 algorithm is that national Password Management office is for ensureing national information safety, the algorithm of the independent research of release.The close SM1 algorithm of state is a kind of symmetry algorithm by the establishment of national Password Management office.The close SM2 algorithm of state is the disclosed a public key algorithm based on the discrete logarithm elliptic curve of national Password Management office; Comprise two element field and prime field, and, realize digital signature/authentication with 256 or two kinds of lower bit wides of 192bit; Key agreement, the function of data encryption/decryption.That algorithm itself has is safe, size of key is little, good or the like the advantage of dirigibility.The close SM3 algorithm of state is a hash algorithm that national Password Management office releases, and Hash Value length is 256 bits.
Therefore, how to create a kind of security coprocessor that uses the IC bank card chip of autonomous algorithm of China and industrial security standard, be those skilled in the art's research direction place.
Summary of the invention
A purpose of the present invention provides a kind of bank intelligent card chip security coprocessor based on homemade algorithm; It is on the basis of close SM1, SM2 and SM3 algorithm based on state; Multiplexing through storage unit and functional module; Reach 1 card two algorithm, realize that 1 people blocks two supports of terminal traffic both at home and abroad 1, satisfies the electronic wallet/electronic passbook of bank intelligent card, the function of debit/credit.
A purpose more of the present invention provides a kind of bank intelligent card chip security coprocessor based on homemade algorithm; It is mutual through address bus, data bus and control signal and CPU; Utilize the close SM1 of state, SM2, SM3 hardware circuit IP kernel; Provide the mould of the big several RSA of 1024bit to take advantage of the hardware accelerator interface; Completion is used required information security function to electronic wallet/electronic passbook, the debit/credit of bank card, satisfies the dual safety requirements of terminal traffic both at home and abroad, and satisfies other hardware requirements of national financial integrated circuit (IC) calliper model regulation.
In order to achieve the above object; The present invention provides a kind of bank intelligent card chip security coprocessor based on homemade algorithm; It is characterized in that it comprises: a storage unit, a control module, a SM1 algoritic module, a SM2 algoritic module, a SM3 algoritic module and a mould are taken advantage of module, wherein
Described storage unit be used for to described SM1 algoritic module, SM2 algoritic module and SM3 algoritic module and mould take advantage of that module enables, control and data input and output; After described SM1 algoritic module, SM2 algoritic module, SM3 algoritic module and mould take advantage of one of them functional module of module to enable; Data and address output end are as the input end of said control module; According to the address, data are write the designated address space of said storage unit through the output terminal of said control module.
In the preferred implementation, be provided with the control word register in the said storage unit, the control word in the said control register comprises the control bit and the SM2 algoritic module parameter of above-mentioned each module.
In the preferred implementation, said SM2 algoritic module provides the mould of the big several RSA of 1024bit to take advantage of the hardware accelerator interface.
In the preferred implementation, described SM1 algoritic module has the hardware circuit IP kernel, is used to provide key distribution, the key encryption and decryption security function of 128bit.
In the preferred implementation; Described SM2 algoritic module has the hardware circuit IP kernel; Be used to provide the digital signature/authentication of the public key system of 256bit or two kinds of bit wides of 192bit, two element field or two kinds of algorithms of prime field, key agreement, the security function of data encryption.
In the preferred implementation, described SM3 algoritic module has the hardware circuit IP kernel, and it is the submodule of said SM2 algoritic module, is used to provide the HASH algorithm, to length L less than 2
64The message of bit, output 256bit Hash Value;
In the preferred implementation, described mould takes advantage of module to have the hardware circuit IP kernel, and it is the submodule of said SM2 algoritic module, and the mould that also can be used for accomplishing the big several RSA Algorithms of 1024bit is taken advantage of the hardware accelerator function.
In the preferred implementation, the input end that said SM3 algoritic module, mould take advantage of module and the shared and said storage unit of SM2 algoritic module to be connected, the data output end of shared and said control module.
In the preferred implementation, described SM3 module is the submodule of said SM2 algorithm unit, and its output terminal returns to described SM2 algoritic module, perhaps directly returns to said storage unit, for CPU reads.
In the preferred implementation, it is the submodule of said SM2 algorithm unit that said mould is taken advantage of module, and its output terminal returns to described SM2 algoritic module, perhaps directly returns to said storage unit, for CPU reads.
Compared with prior art, beneficial effect of the present invention is:
The present invention provides the hardware implementations of the close SM1 of a kind of state, SM2, SM3 algorithm; Accomplish the close SM1 of state, SM2 and the application of SM3 algorithm aspect bank card of new generation; It is the security coprocessor that uses the IC bank card chip of autonomous algorithm of China and industrial security standard fully; The comprehensive hardware that can accomplish the close SM1 of state, SM2, SM3 and subfunction solidifies, and the method that combines than software approach and soft or hard has more fast and the characteristics of higher security; Need the characteristic of use both at home and abroad to bank intelligent card, SM2 provides the mould of the big several RSA Algorithms of 1024bit to take advantage of interface, satisfies the hsrdware requirements of the information security algorithm of International Banks smart card; The present invention is that 1 card/people accomplishes the double-point information safety requirements of terminal traffic both at home and abroad, provide hardware maybe, for the promotion and application of the close SM1 of state, SM2, SM3 algorithm very big value is arranged.CPU writes/sense data to storage unit through data bus alternately, can accomplish the SM1 key distribution; SM1 key encryption and decryption, SM2 digital signature/authentication, SM2 key agreement; The SM2 data encryption/decryption, the multiple function that SM3 message hash and 1024bit mould are taken advantage of enable control.Wherein the SM2 module can Galois field in the selection of 2 yuan of territories or prime field elliptic curve, accomplish 256 and the selection of 192 two kind of bit wide.
Description of drawings
Fig. 1 is CPU of the present invention and the mutual synoptic diagram of security coprocessor;
Fig. 2 is security coprocessor detailed architecture figure of the present invention;
Fig. 3 distributes synoptic diagram for secure coprocessor, which stores space address of the present invention;
Fig. 4 is a security coprocessor control word data structure synoptic diagram of the present invention.
Description of reference numerals: 1-coprocessor; The 11-storage unit; The 12-control module; The 13-SM1 algoritic module; The 14-SM2 algoritic module; The 15-SM3 algoritic module; The 16-mould is taken advantage of module (MMUL module); The 2-CPU.
Embodiment
Below in conjunction with accompanying drawing, do more detailed explanation with other technical characterictic and advantage to the present invention is above-mentioned.
The present invention is the security algorithm coprocessor of the bank intelligent card chip that is the basis with homemade commercial algorithm SM1, SM2 and SM3 algorithm that national Password Management office releases.It is based on the close algorithm of state, satisfies bank intelligent card pboc2.0 standard, satisfies the double-point information security algorithm demand of terminal traffic both at home and abroad with the mode of the hardware co-processor of single deck tape-recorder two algorithm.
Consult Fig. 1 and Fig. 2, be CPU of the present invention and mutual synoptic diagram of coprocessor and coprocessor composition frame chart; Coprocessor 1 of the present invention is mutual through address bus, data bus and control signal and CPU 2 (CPU, Central Processing Unit), is used to alleviate the Processing tasks of CPU 2, improves the speed of system.
Described coprocessor 1 comprises that a storage unit 11, a control module 12, a SM1 algoritic module 13, a SM2 algoritic module 14, a SM3 algoritic module 15, a mould take advantage of module (MMUL module) 16.
Described storage unit 11 is as the interface of CPU 2 with coprocessor 1 internal arithmetic unit; Be provided with control word register 111 in it; Be used for to described SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15 and mould take advantage of that module 16 enables, control and data input and output; 32bit control word in control word register 111 offers described SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15, mould, and to take advantage of module 16 one of them functional module enable signal be 1; After described SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15, mould take advantage of module 16 to enable; Data and address output end according to the address, write data through the output terminal of control module 12 designated address space of said storage unit 11 as the input end of said control module.
Above-mentioned SM1 algoritic module 13 has the hardware circuit IP kernel, is used to provide key distribution, the key encryption and decryption security function of 128bit; The concrete security mechanism of the electronic wallet/electronic passbook of national financial integrated circuit (IC) calliper model PBOC2.0 standard code that realizes comprises: key dispersion, safe packet encryption and decryption, safe packet MAC calculate and transaction MAC/TAC/GMAC/GTAC calculates, and realize that single deck tape-recorder satisfies the function of terminal traffic demand both at home and abroad.
Described SM2 algoritic module 14 has the hardware circuit IP kernel, is used to provide the digital signature/authentication of the public key system of 256bit or two kinds of bit wides of 192bit, two element field or two kinds of algorithms of prime field, key agreement, the security function of data encryption; It has simultaneously 2 yuan of territories or p unit territory, 256 or 4 kinds of parameters of 192bit select, accomplish the bank card debit/credit use in the security mechanism of digital signature/authentication, key agreement or data encryption/decryption function.
Described SM3 algoritic module 15 has the hardware circuit IP kernel, and it is the submodule of said SM2 algoritic module 14, is used to provide the HASH algorithm, to length L less than 2
64The message of bit, output 256bit Hash Value.
Described mould takes advantage of module 16 to have the hardware circuit IP kernel, and it is the submodule of said SM2 algoritic module 14, and the mould that also can be used for accomplishing the big several RSA Algorithms of 1024bit is taken advantage of the hardware accelerator function.Described SM2 algorithm 14 provides the mould of the big several RSA of 1024bit to take advantage of the hardware accelerator interface, accomplishes the mode that combines with soft or hard and realizes the big several RSA Algorithms of 1024bit, realizes the single deck tape-recorder two algorithm, satisfies the demand of 1 card/people's international terminal traffic.
Bank intelligent card chip security coprocessor 1 of the present invention; Its synchronization completion SM1 algoritic module 13, SM2 algoritic module 14 and SM3 algoritic module 15, mould are taken advantage of a function of module 16; Above-mentioned SM1 algoritic module 13, SM2 algoritic module 14, SM3 algoritic module 15 and mould take advantage of module 16 each algorithm IP kernel to read in separately input parameter and data through storage unit 11, export result separately.Said CPU 2 is called each algoritic module IP kernel of control through read 11, and reads the output result of each algoritic module IP kernel.Control word in the control register of storage unit 11 comprises the control bit and the SM2 algoritic module parameter of above-mentioned each algoritic module.
Continue to consult shown in Figure 2, SM3 algoritic module 15 of the present invention and mould take advantage of module 16 to be the submodule of SM2 algoritic module 14.The output terminal of SM3IP nuclear as the submodule of SM2IP nuclear, returns to SM2IP nuclear, and in addition, the output terminal of SM3IP nuclear directly returns to storage unit 11, for CPU 2 reads, accomplishes 256bit message hash security mechanism; Mould is taken advantage of the output terminal of module 16, as the submodule of SM2IP nuclear, returns to SM2IP nuclear; In addition, mould takes advantage of the output terminal of module 16 directly to return to storage unit 11, for CPU 2 reads; SM2IP nuclear provides mould to take advantage of the interface of hardware accelerator; Completion realizes the big several RSA Algorithms of 1024bit with the mode that soft or hard combines, and realizes the single deck tape-recorder two algorithm, satisfies the demand of 1 card/people's international terminal traffic.
For SM3 algoritic module among the present invention 15 and mould are taken advantage of the submodule of module 16 as SM2 algoritic module 14,3 shared input ends that are connected with storage unit 11 of module, the data output end of shared and control module 12; When SM2 algoritic module 13 enables, its fan-in factor is according to then from SM2 inside, otherwise its fan-in factor is according to the control word from storage unit 11, and its output terminal directly drives the output terminal of SM2 algoritic module 13 inside and SM2 algoritic module 13 simultaneously.
Consult Fig. 2, Fig. 3, described storage unit 6 is the storage space of described SM1, SM2, SM3 and MMUL functional module shared (1+8*13) * 32bit, addressing space XX08H-XX77H; 32bit control word on the XX08H of its address offers described SM1 algoritic module 13, SM2 algoritic module 14, SM3 algoritic module 15 and mould, and to take advantage of module 16 one of them functional module enable signal be 1.After described SM1, SM2, SM3 and MMUL functional module enabled, data and address output end were as the input end of said control module 12, and according to the address, the fan-out factor of control module 12 is according to the designated address space that writes said storage unit 11.
Consult Fig. 3, Fig. 4, the control word register on the XX08H address of said storage unit 11, enctrl [1:0] equals 2 ' b00, and then SM1 algoritic module 13 enables; Equal 2 ' b01, then SM2 algoritic module 14 enables; Equal 2 ' b10, then SM3 algoritic module 15 enables; Equal 2 ' b11, then mould takes advantage of module 16 to enable; Smctrl [1:0] equals 2 ' b10 when SM1 enables, then carry out key distribution; Equal 2 ' b11, then carry out the key encryption and decryption.When SM2 algoritic module 14 enables, equal 2 ' b01, then combine digital signature/authentication; Equal 2 ' b10, then carry out key agreement; Equal 2 ' b11, then carry out data encrypting and deciphering.When SM3 algoritic module 15 enables, equal 2 ' b00, then message is continued; Equal 2 ' b11, then last one group of message of 256*13.Encryption and decryption control bit dectrl equals 1 ' b0, and then each module is carried out corresponding cryptographic calculation; Equal 1 ' b1, carry out decrypt operation.25 to 7bit positions are the special-purpose control bit of SM2 algoritic module, are followed successively by from low to high: Galois field control bit gfctrl, and equaling 1 ' b0 is prime field; Equaling 1 ' b1 is two element field.Bit wide control bit fxctrl equals 1 ' b0, then carries out the 192bit data; Equal 1 ' b1, then carry out the 256bit data.8bit data length klen; H.31, the ID length entl of 8bit, 3bit complementary divisor are SM2 algoritic module two element field point most significant digit exclusive data position to the 26bit position, and the position is followed successively by from low to high: gf2xr and the gf2yr of some R; Gf2xp and the gf2yp of point P, gf2xg and the gf2yg of some G.
In sum; The present invention provides the hardware implementations of the close SM1 of a kind of state, SM2, SM3 algorithm; Accomplish the close SM1 of state, SM2 and the application of SM3 algorithm aspect bank card of new generation; Be the security coprocessor that uses the IC bank card chip of autonomous algorithm of China and industrial security standard fully, the comprehensive hardware that can accomplish the close SM1 of state, SM2, SM3 and subfunction solidifies, and the method that combines than software approach and soft or hard has more fast and the characteristics of higher security; Need the characteristic of use both at home and abroad to bank intelligent card, SM2 provides the mould of the big several RSA Algorithms of 1024bit to take advantage of interface, satisfies the hsrdware requirements of the information security algorithm of International Banks smart card; The present invention is that 1 card/people accomplishes the double-point information safety requirements of terminal traffic both at home and abroad, provide hardware maybe, for the promotion and application of the close SM1 of state, SM2, SM3 algorithm very big value is arranged.CPU writes/sense data to storage unit through data bus alternately, can accomplish the SM1 key distribution; SM1 key encryption and decryption, SM2 digital signature/authentication, SM2 key agreement; The SM2 data encryption/decryption, the multiple function that SM3 message hash and 1024bit mould are taken advantage of enable control.Wherein, the SM2 module can Galois field in the selection of 2 yuan of territories or prime field elliptic curve, accomplish 256 and the selection of 192 two kind of bit wide.
More than explanation is just illustrative for the purpose of the present invention, and nonrestrictive, those of ordinary skills understand; Under the situation of spirit that does not break away from following accompanying claims and limited and scope, can make many modifications, change; Or equivalence, but all will fall in protection scope of the present invention.
Claims (10)
1. bank intelligent card chip security coprocessor based on homemade algorithm, it is characterized in that it comprises: a storage unit, a control module, a SM1 algoritic module, a SM2 algoritic module, a SM3 algoritic module and a mould are taken advantage of module, wherein,
Described storage unit be used for to described SM1 algoritic module, SM2 algoritic module and SM3 algoritic module and mould take advantage of that module enables, control and data input and output; After described SM1 algoritic module, SM2 algoritic module, SM3 algoritic module and mould take advantage of one of them functional module of module to enable; Data and address output end are as the input end of said control module; According to the address, data are write the designated address space of said storage unit through the output terminal of said control module.
2. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1; It is characterized in that; Be provided with the control word register in the said storage unit, the control word in the said control register comprises the control bit and the SM2 algoritic module parameter of above-mentioned each module.
3. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1 is characterized in that said SM2 algoritic module provides the mould of the big several RSA of 1024bit to take advantage of the hardware accelerator interface.
4. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1 is characterized in that described SM1 algoritic module has the hardware circuit IP kernel, is used to provide key distribution, the key encryption and decryption security function of 128bit.
5. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1; It is characterized in that; Described SM2 algoritic module has the hardware circuit IP kernel; Be used to provide the digital signature/authentication of the public key system of 256bit or two kinds of bit wides of 192bit, two element field or two kinds of algorithms of prime field, key agreement, the security function of data encryption.
6. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1; It is characterized in that described SM3 algoritic module has the hardware circuit IP kernel, it is the submodule of said SM2 algoritic module; Be used to provide the HASH algorithm, to length L less than 2
64The message of bit, output 256bit Hash Value.
7. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1; It is characterized in that; Described mould takes advantage of module to have the hardware circuit IP kernel; It is the submodule of said SM2 algoritic module, and the mould that also is used to accomplish the big several RSA Algorithms of 1024bit is taken advantage of the hardware accelerator function.
8. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1; It is characterized in that; The input end that said SM3 algoritic module, mould take advantage of module and the shared and said storage unit of SM2 algoritic module to be connected, the data output end of shared and said control module.
9. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1; It is characterized in that; Described SM3 module is the submodule of said SM2 algorithm unit; Its output terminal returns to described SM2 algoritic module, perhaps directly returns to said storage unit, for CPU reads.
10. the bank intelligent card chip security coprocessor based on homemade algorithm according to claim 1; It is characterized in that; It is the submodule of said SM2 algorithm unit that said mould is taken advantage of module; Its output terminal returns to described SM2 algoritic module, perhaps directly returns to said storage unit, for CPU reads.
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