CN102722463A - System for acquiring and processing multi-type information based on cPCI bus - Google Patents
System for acquiring and processing multi-type information based on cPCI bus Download PDFInfo
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- CN102722463A CN102722463A CN201210146470XA CN201210146470A CN102722463A CN 102722463 A CN102722463 A CN 102722463A CN 201210146470X A CN201210146470X A CN 201210146470XA CN 201210146470 A CN201210146470 A CN 201210146470A CN 102722463 A CN102722463 A CN 102722463A
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Abstract
The invention discloses a system for acquiring and processing multi-type information based on cPCI bus, comprising a front end device and a back end device which is connected with the front end device. The front end device integrates a separating and conditioning circuit for multipath signals, a first FPGA, a digital I/O card, an A/D acquisition card, a second FPGA and a single board computer, wherein the separating and conditioning circuit for multipath signals is used for acquiring and processing multipath time bunch signals, multipath simulation signals, multipath contact signals and multipath pulse signals. A controlling host of the back end device carries out remote controls over the acquiring and processing system, and carries out real-time/after judgments and analyses on the multipath time bunch signals, the multipath digital signals, the multipath contact signals and the multipath pulse signals, wherein the signals are stored in a single board computer. A signal which exceeds a preset corresponding range is displayed with highlight and alarmed. Thus, integration of multi-type and multipath signal acquisition based on cPCI bus and intelligence of data analysis are both realized. In addition, the system only comprises the front end device and the back end device, which is small in total volume.
Description
Technical field
The present invention relates to a kind of electronic measurement system, relate in particular to a kind of polymorphic type data collecting and processing system that can be applicable to the carrier rocket integration test based on the cPCI bus.
Background technology
Carrier rocket test signal type and One's name is legion; Cause testing apparatus of a great variety; The testing apparatus that is widely used in the space flight field tests has at present comprised notes appearance, GPIB, CAMAC, VXI etc.; Numerous quantity and complex types have been brought many deficiencies and defective in the test process of carrier rocket:
At first; Carrier rocket part subsystem is often used two kinds even two or more testing apparatus in test process, make uphole equipment in large scale, and the complicacy of itself has been brought the reduction of reliability; The fault of testing apparatus happens occasionally in the test process, incurs loss through delay test period.Secondly, various testing apparatus has also been brought difficulty to the study of regular job and new operator, has increased the possibility of maloperation.Once more, present testing apparatus costs an arm and a leg, and easy care not.Especially external special product, module if fault, are then bought, maintenance cycle is long, even maybe short supply.In addition, the data layout that each testing apparatus gets access to is numerous and diverse, is difficult to handle and effectively utilization, analyzes the interpretation ability automatically, the dependence manpower of the very big degree of interpretation work.
Summary of the invention
The object of the present invention is to provide the polymorphic type data collecting and processing system that a kind of integrated degree is high, volume is little based on the cPCI bus.
For achieving the above object, the invention provides a kind of polymorphic type data collecting and processing system based on the cPCI bus, comprise front-end equipment and coupled rear end equipment, wherein,
Said front-end equipment comprises:
Multiple signals are isolated modulate circuit, and string signal, multichannel analog signals, multichannel contact signal and multiplex pulse signal carry out the conditioning of anti-interference isolation and voltage respectively when being used for the multichannel to input;
The one FPGA; String signal is isolated the output gating and the data acquisition of modulate circuit when being used to control said multichannel; String signal during multichannel that the said multiple signals of buffer memory are isolated modulate circuit output; And the signal of being gathered is carried out filtering, edge judge and the framing pre-service, treat after this sampling is accomplished it to be write among the FIFO of digital I/O card;
Numeral I/O card when string signal reaches and sets storage or setting-up time when the multichannel of storing among its FIFO, is sent to the single-borad computer storage with it through the cPCI bus;
The A/D capture card; Be used for the multichannel analog signals of said multiple signals isolation modulate circuit output is transformed into corresponding multi-path digital signal and storage; When the multi-path digital signal of storing among its FIFO reaches setting value, it is sent to said single-borad computer storage through said cPCI bus;
The 2nd FPGA, the multichannel contact signal and the multiplex pulse signal of be used to gather, buffer memory and the said multiple signals of pre-service being isolated modulate circuit output, and it is sent to said single-borad computer storage through cPCI bus controller and said cPCI bus;
Said rear end equipment comprises main control system; Be used for this acquisition processing system being carried out Long-distance Control through the universal network switching equipment; String signal, multi-path digital signal, multichannel contact signal and the multiplex pulse signal shows respectively in real time, storage, discriminatory analysis and playback afterwards during simultaneously to the multichannel of said single-borad computer collection storage; As exceeding corresponding preset range, then outstandingly show this signal and report to the police.
Polymorphic type data collecting and processing system based on the cPCI bus of the present invention; String signal was isolated modulate circuit when said multiple signals isolation modulate circuit comprised several; To isolate that modulate circuit is used for input voltage range be that the time string signal of 20V～40V is isolated conditioning to string signal during every road; It comprises that model is optocoupler, voltage stabilizing diode D1, decoupling capacitor C1, diode D2, current-limiting resistance R1, pull-up resistor R2 and the capacitor C 2 of TLP114A; The end of the input end of voltage stabilizing diode D1 and current-limiting resistance R1 is corresponding respectively to link to each other with the 3rd pin with the 1st of said optocoupler; Decoupling capacitor C1 and diode D2 are connected to respectively between voltage stabilizing diode D1 and the pull-up resistor R2; The other end of the output terminal of voltage stabilizing diode D1 and current-limiting resistance R1 is the electrode input end and the negative input of corresponding conduct respectively; The 6th pin of said optocoupler connects+5V and link to each other as signal output part with the 5th pin of optocoupler through pull-up resistor R2, and one termination of capacitor C 2+5V, its other end is with the 4th pin ground connection of said optocoupler.
Polymorphic type data collecting and processing system based on the cPCI bus of the present invention; Said multiple signals are isolated modulate circuit and are comprised several simulating signal isolation modulate circuit; Every road simulating signal is isolated modulate circuit and is used for input reference signal is isolated conditioning for the simulating signal of-40V～40V; And the analog signal conditioner after isolation left under order decay to said A/D capture card required-5V～+ scope of 5V in; It comprises that model is the operational amplifier of OP07, isolated amplifier, resistance AR1, resistance AR2, resistance AR3, resistance AR4, resistance AR5, resistance AR6, resistance AR7, electric capacity AC1, electric capacity AC2, stabilivolt AD1, stabilivolt AD2, range switch AS1, AS2 and the AS3 that model is ISO124; The end of resistance AR1 is as electrode input end; Its other end links to each other with the end of resistance AR2 and the end of range switch AS1 respectively; The resistance AR2 other end links to each other with the end of resistance AR3 and the end of range switch AS2 respectively; The resistance AR3 other end links to each other with the end of resistance AR4 and the end of range switch AS3 respectively; The other end of range switch AS1, AS2 and AS3 and connect after link to each other with the input end of stabilivolt AD1 and the end of resistance AR5 respectively, the other end of resistance AR5 links to each other with the input end in the same way of operational amplifier, the output terminal of stabilivolt AD1 links to each other with the output terminal of stabilivolt AD2; The other end of the input end of stabilivolt AD2 and resistance AR4 connects together as negative input; The output terminal of operational amplifier links to each other with the 15th pin of its reverse input end and isolated amplifier respectively, and the 7th pin of isolated amplifier links to each other with the end of resistance AR6, and the other end of resistance AR6 links to each other with the end of resistance AR7 and the end of electric capacity AC1 respectively; The end of the other end of resistance AR7 and electric capacity AC2 connects together as signal output part, the other end ground connection of the other end of electric capacity AC1 and electric capacity AC2.
Polymorphic type data collecting and processing system based on the cPCI bus of the present invention; Said multiple signals are isolated modulate circuit and are comprised several contact signal isolation modulate circuit; The said contact signal in every road is isolated modulate circuit and is used for contact signal is isolated conditioning; And the contact signal after isolation left under order convert 0 to～+ the 5V voltage signal; It comprises that model is the DC power supplier of WRA0512, optocoupler, resistance R 1, resistance R 2, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, electrochemical capacitor C5, electrochemical capacitor C6, stabilivolt D1 and the diode D2 that model is TLP114A; The input end of stabilivolt D1 links to each other with the 1st pin of optocoupler, and the output terminal of stabilivolt D1 is as negative input, and capacitor C 1 and diode D2 are connected between the 1st pin and the 3rd pin of optocoupler; And corresponding respectively the 3rd pin and the 1st pin that connects optocoupler of the input end of diode D2, output terminal; The 3rd pin of optocoupler links to each other with the 8th pin of DC power supplier, and the 6th pin of optocoupler connects+5V and link to each other as signal output part with its 5th pin through resistance R 2, the 4th pin ground connection of optocoupler and connect+5V through capacitor C 2; Electrochemical capacitor C6 and capacitor C 3 are connected between the 8th pin and the 6th pin of DC power supplier; And corresponding respectively the 6th pin and the 8th pin that connects DC power supplier of the positive pole of electrochemical capacitor C6, negative pole, the 1st pin and the 2nd pin of DC power supplier connect+24V, and the 6th pin of DC power supplier passes through resistance R 1 as electrode input end; Electrochemical capacitor C5 and capacitor C 4 are connected between the 1st pin and the 2nd pin of DC power supplier, and corresponding respectively the 2nd pin and the 1st pin that connects DC power supplier of the positive pole of electrochemical capacitor C5, negative pole.
Polymorphic type data collecting and processing system based on the cPCI bus of the present invention; Said multiple signals are isolated modulate circuit and are comprised several pulse signal isolation modulate circuit; Every road pulse signal is isolated modulate circuit and is used for pulse signal is isolated conditioning; And the pulse signal after isolation left under order converts the same frequency count pulse of 5V to, and it comprises that model is optocoupler, capacitor C 1, diode D1, resistance R 1, resistance R 2 and the phase inverter of TLP114A, the 1st pin of optocoupler through resistance R 1 as electrode input end; The 3rd pin of optocoupler is as negative input; Capacitor C 1 and diode D1 are connected between the 1st pin and the 3rd pin of optocoupler, and the input end of diode D1 and output terminal are corresponding respectively links to each other with the 1st pin with the 3rd pin of optocoupler, and the 6th pin of optocoupler connects+and 5V and link together with its 5th pin through resistance R 2 links to each other with the input end of phase inverter; The output terminal of phase inverter is as signal output part, the 4th pin ground connection of optocoupler.
Polymorphic type data collecting and processing system based on the cPCI bus of the present invention; The every 0.2ms once sampling of said FPGA data; And the data that the current data that sample and preceding 0.2ms sample are compared; If taken place to change then produce one and latch/the output identification signal simultaneously will new data be latched into again and waits among the corresponding FIFO and exporting; If all data all do not change in one second, then FPGA exports current test data values, confirms self duty to test macro.
Polymorphic type data collecting and processing system based on the cPCI bus of the present invention; Said the 2nd FPGA latchs once the every 40ms of multiplex pulse signal accumulated counts result according to the order of system software; Said the 2nd FPGA is to the every 1ms once sampling of multichannel contact signal, and the data latching after the sampling is in the FIFO of FPGA, and the every 1ms of contact signal uploads once; The every 40ms of pulse signal uploads once; All comprise time, address, data message in each Frame, for guaranteeing the reliability in the data upload process, data upload adopts " shaking hands " pattern to carry out.
Polymorphic type data collecting and processing system based on the cPCI bus of the present invention comprises front-end equipment and coupled rear end equipment; Wherein integrated string signal, multichannel analog signals, multichannel contact signal and multiplex pulse signal and it is carried out pretreated multiple signals isolate modulate circuit, a FPGA, digital I/O card, A/D capture card, the 2nd FPGA and single-borad computer when being used to gather multichannel in the front-end equipment; The main control system of rear end equipment then carries out Long-distance Control through the universal network switching equipment to this acquisition processing system; String signal, multi-path digital signal, multichannel contact signal and the multiplex pulse signal shows respectively in real time, storage, discriminatory analysis and playback afterwards during simultaneously to the multichannel of single-borad computer collection storage; As exceeding corresponding preset range; Then outstanding this signal that shows is also reported to the police; Thereby realized the integrated test analysis of multiple class, multi channel signals; And only there are front-end equipment and rear end equipment in this system, and cumulative volume is less, has realized the miniaturization based on the polymorphic type data collecting and processing system of cPCI bus.
Description of drawings
Fig. 1 is the structural representation of the polymorphic type data collecting and processing system based on the cPCI bus of the present invention;
Fig. 2 is circuit theory diagrams of isolating modulate circuit based on each road simulating signal in the polymorphic type data collecting and processing system of cPCI bus of the present invention;
Fig. 3 is circuit theory diagrams of isolating modulate circuit based on each road contact signal in the polymorphic type data collecting and processing system of cPCI bus of the present invention;
Fig. 4 is circuit theory diagrams of isolating modulate circuit based on each road pulse signal in the polymorphic type data collecting and processing system of cPCI bus of the present invention;
Fig. 5 be of the present invention based in the polymorphic type data collecting and processing system of cPCI bus during each road string signal isolate the circuit theory diagrams of modulate circuit.
Embodiment
Be described in detail below in conjunction with the accompanying drawing specific embodiments of the invention:
With reference to shown in Figure 1; The polymorphic type data collecting and processing system based on the cPCI bus of present embodiment comprises front-end equipment and coupled rear end equipment; Integrated multiple signals are isolated modulate circuit, a FPGA, digital I/O card, A/D capture card, the 2nd FPGA and single-borad computer in the front-end equipment, wherein:
Multiple signals are isolated modulate circuit; String signal, multichannel analog signals, multichannel contact signal and multiplex pulse signal carried out the conditioning of anti-interference isolation and voltage respectively when it was used for the multichannel of input, and string signal was isolated modulate circuit, 128 tunnel simulating signals isolation modulate circuit when this multiple signals isolation modulate circuit comprised 512 the tunnel, 16 road contact signals isolate modulate circuit and 32 road pulse signals are isolated modulate circuit; The one FPGA; String signal was isolated the output gating and the data acquisition of modulate circuit when it was used to control multichannel; String signal during multichannel that buffer memory and pre-service multiple signals are isolated modulate circuit output, and to the signal of being gathered carry out filtering, the edge is judged and pre-service such as framing, treat after this sampling is accomplished it to be write among the FIFO of digital I/O card; The every 0.2ms once sampling of the one FPGA data; And the data that the current data that sample and preceding 0.2ms sample are compared, if taken place to change then produce one and latch/the output identification signal simultaneously will new data be latched into again and waits among the corresponding FIFO and exporting, if all data all do not change in one second; Then FPGA exports current test data values, confirms self duty to test macro; Numeral I/O card when string signal reaches and sets storage or setting-up time when the multichannel of storing among its FIFO, is sent to the single-borad computer storage with it through the cPCI bus; The A/D capture card; Its multichannel analog signals that is used for multiple signals are isolated modulate circuit output is transformed into corresponding multi-path digital signal and storage; When the multi-path digital signal of storing among its FIFO reaches setting value, it is sent to the single-borad computer storage through the cPCI bus; The 2nd FPGA latchs once the every 40ms of multiplex pulse signal accumulated counts result according to the order of system software; The 2nd FPGA is to the every 1ms once sampling of multichannel contact signal, and the data latching after the sampling is in the FIFO of FPGA, and the every 1ms of contact signal uploads once; The every 40ms of pulse signal uploads once; All comprise time, address, data message in each Frame, for guaranteeing the reliability in the data upload process, data upload adopts " shaking hands " pattern to carry out.
And rear end equipment mainly comprises main control system; It carries out Long-distance Control through the universal network switching equipment to this acquisition processing system; String signal, multi-path digital signal, multichannel contact signal and the multiplex pulse signal shows respectively in real time, storage, discriminatory analysis and ex-post analysis during simultaneously to the multichannel of single-borad computer collection storage; As exceeding corresponding preset range; Then outstanding this signal that shows is also reported to the police, and wherein, the employed criterion of analysis and judgement can be carried out open setting according to user's demand.
In conjunction with shown in Figure 2; Wherein, Every road simulating signal is isolated modulate circuit and is used for input reference signal is isolated conditioning for the simulating signal of-40V～40V, and the analog signal conditioner after isolation left under order decay to A/D capture card Suo Xu De – 5V～+ scope of 5V in.Every road simulating signal is isolated the SF acquiescence 1kHz/ passage of modulate circuit, and the sampling period can be changed according to customer requirements, and the sampling rate setting of different passages can be different.Every road simulating signal is isolated modulate circuit and is comprised that model is the operational amplifier of OP07, isolated amplifier, resistance AR1, resistance AR2, resistance AR3, resistance AR4, resistance AR5, resistance AR6, resistance AR7, electric capacity AC1, electric capacity AC2, stabilivolt AD1, stabilivolt AD2, range switch AS1, AS2 and the AS3 that model is ISO124; The end of resistance AR1 is as electrode input end; Its other end links to each other with the end of resistance AR2 and the end of range switch AS1 respectively; The resistance AR2 other end links to each other with the end of resistance AR3 and the end of range switch AS2 respectively; The resistance AR3 other end links to each other with the end of resistance AR4 and the end of range switch AS3 respectively; The other end of the other end of range switch AS1, the other end of AS2 and AS3 and connect after link to each other with the input end of stabilivolt AD1 and the end of resistance AR5 respectively; The other end of resistance AR5 links to each other with the input end in the same way of operational amplifier; The output terminal of stabilivolt AD1 links to each other with the output terminal of stabilivolt AD2; The other end of the input end of stabilivolt AD2 and resistance AR4 connects together as negative input; The output terminal of operational amplifier links to each other with the 15th pin of its reverse input end and isolated amplifier respectively, and the 7th pin of isolated amplifier links to each other with the end of resistance AR6, and the other end of resistance AR6 links to each other with the end of resistance AR7 and the end of electric capacity AC1 respectively; The end of the other end of resistance AR7 and electric capacity AC2 connects together as signal output part, the other end ground connection of the other end of electric capacity AC1 and electric capacity AC2.
In conjunction with shown in Figure 3; Wherein, Every road contact signal is isolated modulate circuit and is used for contact signal is isolated conditioning; And the contact signal after isolation left under order convert 0 to～+ the 5V voltage signal; Every road contact signal is isolated modulate circuit and is comprised that model is the DC power supplier of WRA0512, optocoupler, resistance R 1, resistance R 2, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, electrochemical capacitor C5, electrochemical capacitor C6, stabilivolt D1 and the diode D2 that model is TLP114A; The input end of stabilivolt D1 links to each other with the 1st pin of optocoupler, and the output terminal of stabilivolt D1 is as negative input, and capacitor C 1 and diode D2 are connected between the 1st pin and the 3rd pin of optocoupler; And corresponding respectively the 3rd pin and the 1st pin that connects optocoupler of the input end of diode D2, output terminal; The 3rd pin of optocoupler links to each other with the 8th pin of DC power supplier, and the 6th pin of optocoupler connects+5V and link to each other with its 5th pin through resistance R 2 and to be connected to the signal input part of the 2nd FPGA as signal output part, the 4th pin ground connection of optocoupler and connect+5V through capacitor C 2; Electrochemical capacitor C6 and capacitor C 3 are connected between the 8th pin and the 6th pin of DC power supplier; And corresponding respectively the 6th pin and the 8th pin that connects DC power supplier of the positive pole of electrochemical capacitor C6, negative pole, the 1st pin and the 2nd pin of DC power supplier connect+24V, and the 6th pin of DC power supplier passes through resistance R 1 as electrode input end; Electrochemical capacitor C5 and capacitor C 4 are connected between the 1st pin and the 2nd pin of DC power supplier, and corresponding respectively the 2nd pin and the 1st pin that connects DC power supplier of the positive pole of electrochemical capacitor C5, negative pole.
In conjunction with shown in Figure 4; Every road pulse signal is isolated modulate circuit and is used for pulse signal is isolated conditioning; And the pulse signal after isolation left under order converts the same frequency count pulse of 5V to; Every road pulse signal is isolated modulate circuit and is comprised that model is optocoupler, capacitor C 1, diode D1, resistance R 1, resistance R 2 and the phase inverter of TLP114A; As electrode input end, the 3rd pin of optocoupler is as negative input through resistance R 1 for the 1st pin of optocoupler, and capacitor C 1 and diode D1 are connected between the 1st pin and the 3rd pin of optocoupler; And the input end of diode D1 links to each other with the 1st pin with the 3rd pin of optocoupler with output terminal is corresponding respectively; The 6th pin of optocoupler connects+and 5V and link together with its 5th pin through resistance R 2 links to each other with the input end of phase inverter, and the output terminal of phase inverter is connected to the signal input part of the 2nd FPGA, the 4th pin ground connection of optocoupler as signal output part.
In conjunction with shown in Figure 5; To isolate that modulate circuit is used for input voltage range be that the time string signal of 20V～40V is isolated conditioning to string signal during every road; And will not receive less than the narrow pulse signal of lms when incoming signal level is lower than 14V and pulse width; And rising edge and negative edge to input signal all respond also timing, import along change interval when difference and arrive less than can be considered simultaneously of lms, and the resolution of timing is not more than 0.2ms.String signal is isolated modulate circuit and is comprised that model is optocoupler, voltage stabilizing diode D1, decoupling capacitor C1, diode D2, current-limiting resistance R1, pull-up resistor R2 and the capacitor C 2 of TLP114A during every road; The end of the input end of voltage stabilizing diode D1 and current-limiting resistance R1 is corresponding respectively to link to each other with the 3rd pin with the 1st of optocoupler; Decoupling capacitor C1 and diode D2 are connected to respectively between voltage stabilizing diode D1 and the pull-up resistor R2; The other end of the output terminal of voltage stabilizing diode D1 and current-limiting resistance R1 is the electrode input end and the negative input of corresponding conduct respectively; The 6th pin of optocoupler connects+5V and link to each other with the 5th pin of optocoupler through pull-up resistor R2 and to be connected to the signal input bus of a FPGA as signal output part; One termination of capacitor C 2+5V, its other end is with the 4th pin ground connection of optocoupler.
Above embodiment describes preferred implementation of the present invention; Be not that scope of the present invention is limited; Design under the prerequisite of spirit not breaking away from the present invention; Various distortion and improvement that the common engineering technical personnel in this area make technical scheme of the present invention all should fall in the definite protection domain of claims of the present invention.
Claims (7)
1. the polymorphic type data collecting and processing system based on the cPCI bus is characterized in that, comprises front-end equipment and coupled rear end equipment, wherein,
Said front-end equipment comprises:
Multiple signals are isolated modulate circuit, and string signal, multichannel analog signals, multichannel contact signal and multiplex pulse signal carry out the conditioning of anti-interference isolation and voltage respectively when being used for the multichannel to input;
The one FPGA; String signal is isolated the output gating and the data acquisition of modulate circuit when being used to control said multichannel; String signal during multichannel that the said multiple signals of buffer memory are isolated modulate circuit output; And the signal of being gathered is carried out filtering, edge judge and the framing pre-service, treat after this sampling is accomplished it to be write among the FIFO of digital I/O card;
Numeral I/O card when string signal reaches and sets storage or setting-up time when the multichannel of storing among its FIFO, is sent to the single-borad computer storage with it through the cPCI bus;
The A/D capture card; Be used for the multichannel analog signals of said multiple signals isolation modulate circuit output is transformed into corresponding multi-path digital signal and storage; When the multi-path digital signal of storing among its FIFO reaches setting value, it is sent to said single-borad computer storage through said cPCI bus;
The 2nd FPGA, the multichannel contact signal and the multiplex pulse signal of be used to gather, buffer memory and the said multiple signals of pre-service being isolated modulate circuit output, and it is sent to said single-borad computer storage through cPCI bus controller and said cPCI bus;
Said rear end equipment comprises main control system; Be used for this acquisition processing system being carried out Long-distance Control through the universal network switching equipment; String signal, multi-path digital signal, multichannel contact signal and the multiplex pulse signal shows respectively in real time, storage, discriminatory analysis and playback afterwards during simultaneously to the multichannel of said single-borad computer collection storage; As exceeding corresponding preset range, then outstandingly show this signal and report to the police.
2. the polymorphic type data collecting and processing system based on the cPCI bus according to claim 1; It is characterized in that; String signal was isolated modulate circuit when said multiple signals isolation modulate circuit comprised several; To isolate that modulate circuit is used for input voltage range be that the time string signal of 20V～40V is isolated conditioning to string signal during every road; It comprises that model is optocoupler, voltage stabilizing diode D1, decoupling capacitor C1, diode D2, current-limiting resistance R1, pull-up resistor R2 and the capacitor C 2 of TLP114A; The end of the input end of voltage stabilizing diode D1 and current-limiting resistance R1 is corresponding respectively to link to each other with the 3rd pin with the 1st of said optocoupler; Decoupling capacitor C1 and diode D2 are connected to respectively between voltage stabilizing diode D1 and the pull-up resistor R2, and the other end of the output terminal of voltage stabilizing diode D1 and current-limiting resistance R1 is the electrode input end and the negative input of corresponding conduct respectively, and the 6th pin of said optocoupler connects+5V and link to each other as signal output part with the 5th pin of optocoupler through pull-up resistor R2; One termination of capacitor C 2+5V, its other end is with the 4th pin ground connection of said optocoupler.
3. the polymorphic type data collecting and processing system based on the cPCI bus according to claim 1; It is characterized in that; Said multiple signals are isolated modulate circuit and are comprised several simulating signal isolation modulate circuit; Every road simulating signal is isolated modulate circuit and is used for input reference signal is isolated conditioning for the simulating signal of-40V～40V; And the analog signal conditioner after isolation left under order decay to said A/D capture card Suo Xu De – 5V～+ scope of 5V in; It comprises that model is the operational amplifier of OP07, isolated amplifier, resistance AR1, resistance AR2, resistance AR3, resistance AR4, resistance AR5, resistance AR6, resistance AR7, electric capacity AC1, electric capacity AC2, stabilivolt AD1, stabilivolt AD2, range switch AS1, AS2 and the AS3 that model is ISO124; The end of resistance AR1 is as electrode input end; Its other end links to each other with the end of resistance AR2 and the end of range switch AS1 respectively; The resistance AR2 other end links to each other with the end of resistance AR3 and the end of range switch AS2 respectively, and the resistance AR3 other end links to each other with the end of resistance AR4 and the end of range switch AS3 respectively, the other end of range switch AS1, AS2 and AS3 and connect after link to each other with the input end of stabilivolt AD1 and the end of resistance AR5 respectively; The other end of resistance AR5 links to each other with the input end in the same way of operational amplifier; The output terminal of stabilivolt AD1 links to each other with the output terminal of stabilivolt AD2, and the other end of the input end of stabilivolt AD2 and resistance AR4 connects together as negative input, and the output terminal of operational amplifier links to each other with the 15th pin of its reverse input end and isolated amplifier respectively; The 7th pin of isolated amplifier links to each other with the end of resistance AR6; The other end of resistance AR6 links to each other with the end of resistance AR7 and the end of electric capacity AC1 respectively, and the end of the other end of resistance AR7 and electric capacity AC2 connects together as signal output part, the other end ground connection of the other end of electric capacity AC1 and electric capacity AC2.
4. the polymorphic type data collecting and processing system based on the cPCI bus according to claim 1; It is characterized in that; Said multiple signals are isolated modulate circuit and are comprised several contact signal isolation modulate circuit; The said contact signal in every road is isolated modulate circuit and is used for contact signal is isolated conditioning; And the contact signal after isolation left under order convert 0 to～+ the 5V voltage signal; It comprises that model is the DC power supplier of WRA0512, optocoupler, resistance R 1, resistance R 2, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, electrochemical capacitor C5, electrochemical capacitor C6, stabilivolt D1 and the diode D2 that model is TLP114A; The input end of stabilivolt D1 links to each other with the 1st pin of optocoupler, and the output terminal of stabilivolt D1 is as negative input, and capacitor C 1 and diode D2 are connected between the 1st pin and the 3rd pin of optocoupler; And corresponding respectively the 3rd pin and the 1st pin that connects optocoupler of the input end of diode D2, output terminal; The 3rd pin of optocoupler links to each other with the 8th pin of DC power supplier, and the 6th pin of optocoupler connects+5V and link to each other as signal output part with its 5th pin through resistance R 2, the 4th pin ground connection of optocoupler and connect+5V through capacitor C 2; Electrochemical capacitor C6 and capacitor C 3 are connected between the 8th pin and the 6th pin of DC power supplier; And corresponding respectively the 6th pin and the 8th pin that connects DC power supplier of the positive pole of electrochemical capacitor C6, negative pole, the 1st pin and the 2nd pin of DC power supplier connect+24V, and the 6th pin of DC power supplier passes through resistance R 1 as electrode input end; Electrochemical capacitor C5 and capacitor C 4 are connected between the 1st pin and the 2nd pin of DC power supplier, and corresponding respectively the 2nd pin and the 1st pin that connects DC power supplier of the positive pole of electrochemical capacitor C5, negative pole.
5. the polymorphic type data collecting and processing system based on the cPCI bus according to claim 1; It is characterized in that; Said multiple signals are isolated modulate circuit and are comprised that the several pulse signal isolates modulate circuit, and every road pulse signal is isolated modulate circuit and is used for pulse signal is isolated conditioning, and the pulse signal after isolation left under order converts the same frequency count pulse of 5V to; It comprises that model is optocoupler, capacitor C 1, diode D1, resistance R 1, resistance R 2 and the phase inverter of TLP114A; As electrode input end, the 3rd pin of optocoupler is as negative input through resistance R 1 for the 1st pin of optocoupler, and capacitor C 1 and diode D1 are connected between the 1st pin and the 3rd pin of optocoupler; And the input end of diode D1 links to each other with the 1st pin with the 3rd pin of optocoupler with output terminal is corresponding respectively; The 6th pin of optocoupler connects+and 5V and link together with its 5th pin through resistance R 2 links to each other with the input end of phase inverter, and the output terminal of phase inverter is as signal output part, the 4th pin ground connection of optocoupler.
6. the polymorphic type data collecting and processing system based on the cPCI bus according to claim 1; It is characterized in that; The every 0.2ms once sampling of said FPGA data; And the data that the current data that sample and preceding 0.2ms sample are compared, if taken place to change then produce one and latch/the output identification signal simultaneously will new data be latched into again and waits among the corresponding FIFO and exporting, if all data all do not change in one second; Then FPGA exports current test data values, confirms self duty to test macro.
7. the polymorphic type data collecting and processing system based on the cPCI bus according to claim 1; It is characterized in that said the 2nd FPGA latchs once the every 40ms of multiplex pulse signal accumulated counts result according to the order of system software, said the 2nd FPGA is to the every 1ms once sampling of multichannel contact signal; Data latching after the sampling is in the FIFO of FPGA; The every 1ms of contact signal uploads once, and the every 40ms of pulse signal uploads once, all comprises time, address, data message in each Frame; For guaranteeing the reliability in the data upload process, data upload adopts " shaking hands " pattern to carry out.
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