CN102722121A - Matrix digital signal acquisition device - Google Patents
Matrix digital signal acquisition device Download PDFInfo
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- CN102722121A CN102722121A CN2012101960790A CN201210196079A CN102722121A CN 102722121 A CN102722121 A CN 102722121A CN 2012101960790 A CN2012101960790 A CN 2012101960790A CN 201210196079 A CN201210196079 A CN 201210196079A CN 102722121 A CN102722121 A CN 102722121A
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Abstract
The invention discloses a matrix digital signal acquisition device which comprises a direct-current voltage reducing circuit. An output end of the direct-current voltage reducing circuit is respectively and simultaneously connected with a matrix column scanning cache driving circuit, a matrix logic circuit, a matrix row signal readout circuit and a signal input circuit, an output port of the matrix column scanning cache driving circuit is connected with a cascade interface circuit, another output port of the matrix column scanning cache driving circuit is connected with the matrix logic circuit, an output end of the signal input circuit is connected with the matrix logic circuit, and an output end of the matrix logic circuit is connected with the matrix row signal readout circuit. The digital signal acquisition device based on a matrix and synchronous serial column scanning realizes a function of reducing input ports and increasing acquisition points, service efficiency of the input ports is improved, the quantity of configured input points is greatly reduced, limited spaces of the acquisition device are saved, arranged wires are reduced for a distribution acquisition mode, and a low-cost solution is provided.
Description
Technical field
The invention belongs to electronic technology field, belong to the batch digital quantity input technology of the signals collecting field Open Control in the automation control system, be specifically related to a kind of matrix form digital quantity signal collector.
Background technology
The automaticity of plant equipment is increasingly high at present; Control system needs the quantity of state of collection site also more and more; Especially various switching values, a point just need take an input point of controller, and hardware resource is limited especially; When carrying out embedded system development, the IO resource all can not satisfy user demand under a lot of situation.As adopt PLC control to need to add a large amount of load modules, and increase frame and expand, increase hardware cost and require bigger installing space, wiring is also very complicated; In addition, the distributed site acquisition module interface of bus form is open, requires controller to possess the respective bus resource, uses dumb, the increase cost.
Summary of the invention
The purpose of this invention is to provide a kind of matrix form digital quantity signal collector; Solved and had the Hardware I resource-constrained in the prior art, during the quantity of state of dilatation collection site, needed to increase frame and expands; Increase hardware cost and require bigger installing space, wiring is also very complicated; Wiring complicacy when a large amount of quantity that the control system that extensively adopts need be used are imported, the inadequate problem of the IO utilization of resources.
The technical scheme that the present invention adopted is; A kind of matrix form digital quantity signal collector; Comprise direct-current voltage reducing circuit; The output terminal of direct-current voltage reducing circuit is connected with signal input circuit with rectangular array scanning buffer memory driving circuit, matrix logic circuit, row matrix signal read circuits respectively simultaneously, and an output terminal of rectangular array scanning buffer memory driving circuit is connected with the subtending port circuit, and another output terminal of rectangular array scanning buffer memory driving circuit is connected with the matrix logic circuit; The output terminal of signal input circuit is connected with the matrix logic circuit, and the output terminal of matrix logic circuit is connected with the row matrix signal read circuits.
The invention has the beneficial effects as follows; Digital quantity signal collector based on matrix form and synchronous serial column scan; Realize adopting single this equipment of cover, utilize 8 input channels of controller and 3 output channels just can read 64 digital quantities, can this collector be carried out cascade simultaneously; Realize 128 points, 192 points, even reading of multiple spot number more under the situation about allowing in the scan period at 256, thereby practice thrift input channel greatly.Simultaneously wiring is succinct during remote collection, is a kind of low-cost solution of distributed capture.
Description of drawings
Fig. 1 is that the integral body of apparatus of the present invention connects block diagram;
Fig. 2 is rectangular array scanning buffer memory driving circuit 102, direct-current voltage reducing circuit 101 and subtending port circuit 105 schematic diagrams in apparatus of the present invention;
Fig. 3 is row matrix signal read circuits 104 schematic diagrams in apparatus of the present invention;
Fig. 4 is matrix logic circuit 103 schematic diagrams in apparatus of the present invention;
Fig. 5 is first and the 8th group a schematic diagram in the signal input circuit 106 in apparatus of the present invention;
Fig. 6 is the sequential control synoptic diagram of rectangular array control signal of the present invention.
Among the figure, 101. direct-current voltage reducing circuits, 102. rectangular arrays scanning buffer memory driving circuit, 103. matrix logic circuit, 104. row matrix signal read circuits, 105. subtending port circuit, 106. signal input circuits,
In addition, R1, R2 ... R203 representes each resistance respectively;
OU1, OU2 ... OU20 representes each photoelectrical coupler respectively;
NA1, NA2, NA3, NA4 ... NA16 representes each Sheffer stroke gate device respectively;
U1 seals in and the chip that goes out to be shifted;
DI1, DI2 ... DI64 representes the input terminal of each digital quantity signal respectively;
DO1, DO2 ... DO8 representes the batch lead-out terminal of collection point signal respectively;
F1, F2 ... The row output signal of F8 difference representing matrix column scan circuit 104 and the tie point of matrix logic circuit 103;
Q0, Q2 ... The tie point of Q7 difference representing matrix column scan buffer memory driving circuit 102 and matrix logic circuit 103;
P11, P12 ... The tie point of capable signal read circuits 104 of P88 difference representing matrix and signal input circuit 106;
PWR is the 24V power end, and SI, SCK, CLR be the serial data signal of control end respectively, displacement control signal and buffer, register clear signal;
SRCK, SER, QH, RCK, Cache and Q0-Q7 refer to the signal of shift pulse signal, serial data signal, latch pulse signal, serial data output end signal, offset buffer signal and the delivery outlet of 74HC595 respectively.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is elaborated.
With reference to Fig. 1; Matrix form digital quantity signal collector structure of the present invention is; The output terminal of direct-current voltage reducing circuit 101 is connected with signal input circuit 106 with rectangular array scanning buffer memory driving circuit 102, matrix logic circuit 103, row matrix signal read circuits 104 respectively simultaneously; An output terminal of rectangular array scanning buffer memory driving circuit 102 is connected with subtending port circuit 105; Another output terminal of rectangular array scanning buffer memory driving circuit 102 is connected with matrix logic circuit 103, and the output terminal of signal input circuit 106 is connected with matrix logic circuit 103, and the output terminal of matrix logic circuit 103 is connected with row matrix signal read circuits 104.
The 24V voltage that direct-current voltage reducing circuit 101 is used for actual condition is the 5V voltage of logical device needs through DC converter DC-DC step-down, the 5V voltage of exporting is linked into each logical device feeder ear, for each logical device is supplied power.
Rectangular array scanning buffer memory driving circuit 102 is made up of the shifting cache chip for driving and the current-limiting resistance of photoelectric coupled device and one 8 bit serial input and line output, and column selection sequence and control signal are through isolating and reverse back access shifting cache chip for driving.
Row matrix signal read circuits 104 is made up of photoelectrical coupler and current-limiting resistance; The output of gate circuit is arranged according to row; The parallelly connected respectively input end subtending port that is linked into the photoelectric isolating device of capable signal output then of each row; Be a mouthful process photoelectricity coupling to be shifted out in the serial of shifting cache chip for driving guide to lead-out terminal, be used for the column scan signal input of next collector of cascade.
With reference to Fig. 2, be the circuit structure of rectangular array scanning buffer memory driving circuit 102, direct-current voltage reducing circuit 101 and subtending port circuit 105.Direct-current voltage reducing circuit 101 is driving circuit 102 and 105 power supplies of subtending port circuit; Direct-current voltage reducing circuit 101 wherein comprises DC-DC; The DC-DC input end is connected with the 24V power supply with PRW simultaneously, and the DC-DC output terminal is connected with the 5V power supply, and DC-DC also is provided with earth terminal.
Subtending port circuit 105 wherein comprises that two resistance (R9, R10) and photoelectric coupled device OU2 form, and the output terminal of photoelectric coupled device OU2 input side is connected with resistance R 9, and the input end of OU2 input side is connected with the 5V power supply; The direct ground connection of output terminal of photoelectric coupled device OU2 outgoing side, the input end of OU2 outgoing side is connected with Q7 ' terminal with resistance R 10, and resistance R 10 is connected with the 24V power supply again.
Rectangular array scanning buffer memory driving circuit 102 comprises shifting cache chip for driving U1 (model is 74HC595) and a plurality of current-limiting resistance of 1 photoelectric coupled device OU1 (model is TLP521-4), 8 bit serial input and line output.Signal end CLR wherein, SI are connected with the input end of the upper and lower road input side of photoelectrical coupler OU1 respectively; Signal end SCK is connected with the input end of middle the two-way input side of photoelectrical coupler OU1 simultaneously, the output terminal of four road input sides of OU1 contact separately behind the resistance (being respectively R1, R2, R3, R4) distinguish ground connection again; The 5V voltage end is contacted respectively and is inserted three input ends of the signal outgoing side of photoelectrical coupler OU1 behind the resistance (being respectively R5, R6, R7) separately, and the 5V voltage end is direct the 4th input end of the signal outgoing side of access photoelectrical coupler OU1 in addition; The input end of the OU1 outgoing side that CLR is corresponding is connected with the SRCLR pin of U1; SCK wherein one tunnel corresponding OU1 outgoing side input end is connected with the RCK pin of U1; SCK other one tunnel corresponding OU1 outgoing side input end is connected with the SRCK pin of U1; The OU1 outgoing side output terminal that SI is corresponding is connected with the SER pin of U1 through resistance R 8, and the pin VCC of U1 is connected with the 5V power supply; The pin of U1 also comprises eight output terminal Q0 to Q7, and the Q7 ' pin of U1 is connected with input end of OU2 with resistance R 9 series connection backs and isolates the OE pin ground connection of U1.
Above-mentioned circuit carries out electrical isolation through OU1 to CLR, SCK, SI, accomplishes simultaneously CLR, SCK negate, and the high level through control end is accomplished the control that resets of U1 low level, and the output latch of accomplishing displacement and latch through SCK is simultaneously controlled.Through the pulse signal of input SI, import shift pulse then successively, the selection signal of high level just can appear to Q7 at output terminal Q0 successively; Continue to move; Maintenance SI is a low level, and then Q1 just can obtain lowly entirely to Q7, and high level moves to Q7 '; Treat as the SI input signal of another capture card, thereby realized the function of cascade increase-volume.
With reference to Fig. 3, row matrix signal read circuits 104 circuit structures are, comprise that 2 photoelectrical couplers (OU3 and OU4) (model is TLP521-4) form, and wherein 8 input ends of two photoelectrical couplers (OU3 and OU4) input side all directly are connected with the 5V power supply; 8 output terminals of two photoelectrical couplers (OU3 and OU4) input side respectively with a F1, F2 ... F8 is corresponding to be connected; 8 input ends of two photoelectrical couplers (OU3 and OU4) outgoing side are connected with the 24V power supply respectively; 8 output terminals of two photoelectrical couplers (OU3 and OU4) outgoing side respectively with batch lead-out terminal DO0, DO1 ... DO7 is corresponding to be connected.
As F1, F2 ... When low level appearred in F8, two photoelectrical couplers (OU3 and OU4) were switched on, and made its corresponding outgoing side output terminal the 24V high level occur.Control array selecting signal, just can collect the signal of respective column in batches.
With reference to Fig. 4, the circuit structure of matrix logic circuit 103 is that each row comprises 242 input nand gate devices (model is 74SL24); 8 row amount to 16 (NA1 among the figure, NA2 ... NA16), each the Sheffer stroke gate device in every row, wherein one road input end is connected respectively to column select circuit (Q0, Q1 ... Q7); Another road input end be connected respectively to input signal Pxy (wherein x represent row; Value is 1-8, and y representes the position of every row, and same value is 1-8); The output terminal of each Sheffer stroke gate device is connected respectively behind the resistance to connect together according to row value and is outputed to Fy (wherein y representes the position of every row, and value is 1-8 equally).
As Q0, Q1 ... When Q7 is high level; With Q0, Q1 ... The Q7 value of the input signal Pxy of Sheffer stroke gate device altogether oppositely is mapped to F1, F2 ... F8 is last, promptly works as any Qn (n is 0 to 7) for high, representes that the n row are selected; As Pnx when being high; Correspondence is output as low, and the corresponding resistance that connects is pull down resistor, the high level of exporting in all the other each row is also all drawn be low level; As Pnx when being high, outputs of all the other each row are invalid, are always high level, so show high level input, F1, F2 in elected ... The effective low level of the last output of F8.
With reference to Fig. 5; Signal input circuit 106 circuit structures are; Comprise 16 photoelectrical couplers (OU5, OU6 ... OU19, OU20) (selecting for use model to be TLP521-4) connect to form with the corresponding a plurality of current-limiting resistances (R75, R76...R202) that are connected; The size that is limited to accompanying drawing only demonstrates part-structure among the figure.Signal input terminal DI0, DI2 ... The every tetrad of DI63 is directly connected to each photoelectrical coupler (OU5, OU5 ... OU19, OU20) the input end of input side; The output terminal of each photoelectrical coupler input side directly ground connection of a resistance (being respectively R75, R2, R3, R138) back of connecting respectively; Each photoelectrical coupler (OU5, OU5 ... OU19, OU20) the input end of outgoing side be connected with the 5V power supply respectively, the output terminal of each the photoelectrical coupler outgoing side resistance of contacting respectively (is respectively R139, R140 ... R201, R202) after separately with row matrix signal read circuits 104 tie point P11, P12 with signal input circuit 106 ... P88 connects.
With reference to Fig. 6, be the control timing of shifting cache chip for driving U1 (74HC595), SRCK, SER are directly obtained through OU1 by input control signal, and SRCLR is obtained through photoelectrical coupler OU1 by CLR.In first cycle, import 1, rising edge appears in the middle of the one-period in SRCK, deposits the data of SER in buffer first buffering position; First end cycle; Negative edge appears in SRCK, and rising edge appears in the pulse RCK that deposits, and the QO mouth of collector is output as high level; Choose first row, the DO mouth of collector just obtains the signal of first row (DI0-DI7); In second period SI input 0,1 of beginning is displaced to second, and then selected secondary series this moment, and the DO mouth just obtains the signal of secondary series (DI8-DI15), and then 3-8 cycle imports 0, the data that are followed successively by (DI16-DI63) that obtain again; As required, in the displacement of not accomplishing 8 cycles, reset through SCLR and to accomplish the scanning in the specified scope from new scan round.
During cascade, with DO mouth, SRCK, CLR, the parallel connection of each matrix form digital quantity signal collector, Q7 ' connects with SI, increases the train of impulses (cycle period) of scanning then, realizes the signals collecting of each point.So scan round is read in controller step by step with the signal of all accesses.
Matrix form digital quantity signal collector of the present invention pursues the signal that current scan line is read in column scan through the matrix circulation, and the mode that reads in batches realizes the digital data acquisition function of few IO mouth multiple spot.Direct-current voltage reducing circuit is the TTL voltage that logical device needs with the voltage step-down of actual condition, and output is linked into each logical device feeder ear; Gating matrix array selecting signal buffer clear signal CLR, matrix array selecting signal SI and shift pulse signal SCK are connected on the column selection driver after isolating through photoelectricity, and rectangular array selects the output of driver to be connected to the column circuits of matrix logic; The signal input is connected to rectangular array through signal isolation circuit; Output to the row of appointment then by row, be connected to the row matrix signal read circuits, the other end of row signal is directly received lead-out terminal; As long as capable signal DO mouth, SCLR, parallel connection with each matrix form digital quantity signal collector; Serial ports shifts out signal Q7 ' series connection, increases the cycle period of scanning, can realize the function of increase-volume.
In other words; Matrix form digital quantity signal collector of the present invention; Utilize the array selecting signal of the 3DO gating matrix column scan buffer memory driving circuit 102 of controller; Selecteed row are delivered to row matrix signal read circuits 104 with signal by row through matrix logic circuit 103, and the 8DI of controller reads the signal of current selection row, and the mode through the scan round rectangular array is reading of data in batches; The control signal of the capable signal of matrix logic circuit 103 and rectangular array scanning buffer memory driving circuit 102 has been formed subtending port circuit 105; Thereby through cascade can realize 128 points, 192,256 in addition more reading of multiple spot number practice thrift input channel greatly, simplify field wiring; The employing photoelectric coupled device is isolated, and has realized the electrical isolation of signal, has guaranteed the security of system.
Adopt this collector can improve the input port service efficiency of controller, significantly reduce and import the configuration of counting, wiring is reduced for distributed capture in the limited space of practicing thrift controller, and low cost solution is provided; Control interface is open, and controller is not had the bus resource requirement, uses flexibly.
Claims (7)
1. matrix form digital quantity signal collector; It is characterized in that: comprise direct-current voltage reducing circuit (101); The output terminal of direct-current voltage reducing circuit (101) is connected with signal input circuit (106) with rectangular array scanning buffer memory driving circuit (102), matrix logic circuit (103), row matrix signal read circuits (104) respectively simultaneously; An output terminal of rectangular array scanning buffer memory driving circuit (102) is connected with subtending port circuit (105); Another output terminal of rectangular array scanning buffer memory driving circuit (102) is connected with matrix logic circuit (103); The output terminal of signal input circuit (106) is connected with matrix logic circuit (103), and the output terminal of matrix logic circuit (103) is connected with row matrix signal read circuits (104).
2. matrix form digital quantity signal collector according to claim 1; It is characterized in that: described direct-current voltage reducing circuit (101) comprises DC-DC; The input end of DC-DC is connected respectively with the 24V power supply with the PRW terminal simultaneously; The output terminal of DC-DC is connected with the 5V power supply, and DC-DC also is provided with earth terminal.
3. matrix form digital quantity signal collector according to claim 1; It is characterized in that: described rectangular array scanning buffer memory driving circuit (102) comprises shifting cache chip for driving U1 and a plurality of current-limiting resistance of 1 photoelectric coupled device OU1,8 bit serial input and line output
Signal end CLR wherein, SI are connected with the input end of the upper and lower road input side of photoelectrical coupler OU1 respectively; Signal end SCK is connected with the input end of middle the two-way input side of photoelectrical coupler OU1 simultaneously, and the output terminal of four road input sides of OU1 is contacted separately and distinguished ground connection again behind the resistance; The 5V voltage end is contacted respectively and is inserted three input ends of the signal outgoing side of photoelectrical coupler OU1 behind the resistance separately, and the 5V voltage end is direct the 4th input end of the signal outgoing side of access photoelectrical coupler OU1 in addition; The input end of the OU1 outgoing side that CLR is corresponding is connected with the SRCLR pin of U1; SCK wherein one tunnel corresponding OU1 outgoing side input end is connected with the RCK pin of U1; SCK other one tunnel corresponding OU1 outgoing side input end is connected with the SRCK pin of U1; The OU1 outgoing side output terminal that SI is corresponding is connected with the SER pin of U1 through resistance R 8, and the pin VCC of U1 is connected with the 5V power supply; The pin of U1 also comprises eight output terminal Q0 to Q7, and the Q7 ' pin of U1 is connected with input end of OU2 with resistance R 9 series connection backs and isolates the OE pin ground connection of U1.
4. matrix form digital quantity signal collector according to claim 1; It is characterized in that: described row matrix signal read circuits (104) circuit structure is; Comprise photoelectrical coupler OU3 and photoelectrical coupler OU4, wherein 8 of two photoelectrical coupler input sides input ends all directly are connected with the 5V power supply; 8 output terminals of two photoelectrical coupler input sides respectively with a F1, F2 ... F8 is corresponding to be connected; 8 input ends of two photoelectrical coupler outgoing sides are connected with the 24V power supply respectively; 8 output terminals of two photoelectrical coupler outgoing sides respectively with batch lead-out terminal DO0, DO1 ... DO7 is corresponding to be connected.
5. matrix form digital quantity signal collector according to claim 1 is characterized in that: the circuit structure of described matrix logic circuit (103) is that each row comprises 242 input nand gate devices; 8 row amount to 16, each the Sheffer stroke gate device in every row, and wherein one road input end is connected respectively to column select circuit; Another road input end is connected respectively to the Pxy of input signal, and wherein x representes row, and value is 1-8; Y representes the position of every row, and same value is 1-8, and the output terminal of each Sheffer stroke gate device is connected respectively behind the resistance to connect together according to the row value and outputed to Fy; Wherein y representes the position of every row, and same value is 1-8.
6. matrix form digital quantity signal collector according to claim 1 is characterized in that: described subtending port circuit (105) comprises photoelectric coupled device OU2 and resistance R 9, resistance R 10,
The output terminal of photoelectric coupled device OU2 input side is connected with resistance R 9, and the input end of OU2 input side is connected with the 5V power supply; The direct ground connection of output terminal of photoelectric coupled device OU2 outgoing side, the input end of OU2 outgoing side is connected with Q7 ' terminal with resistance R 10, and resistance R 10 is connected with the 24V power supply again.
7. matrix form digital quantity signal collector according to claim 1; It is characterized in that: described signal input circuit (106) circuit structure is; Comprise 16 photoelectrical couplers and the corresponding a plurality of current-limiting resistances that are connected; Signal input terminal DI0, DI2 ... The every tetrad of DI63 is directly connected to the input end of the input side of each photoelectrical coupler; The output terminal of each photoelectrical coupler input side directly ground connection of connecting respectively behind the resistance, the input end of the outgoing side of each photoelectrical coupler is connected with the 5V power supply respectively, and the output terminal of each photoelectrical coupler outgoing side is contacted respectively behind the resistance separately and tie point P11, P12 ... P88 connects.
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| CN201210196079.0A CN102722121B (en) | 2012-06-14 | 2012-06-14 | Matrix digital signal acquisition device |
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| CN201210196079.0A CN102722121B (en) | 2012-06-14 | 2012-06-14 | Matrix digital signal acquisition device |
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| CN102722121A true CN102722121A (en) | 2012-10-10 |
| CN102722121B CN102722121B (en) | 2014-07-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991981A (en) * | 2017-12-05 | 2018-05-04 | 迈普通信技术股份有限公司 | A kind of service board and electronic equipment |
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| EP2117124B1 (en) * | 2008-05-05 | 2010-10-13 | Peter Renner | Data acquisition device and method for its operation |
| CN202679343U (en) * | 2012-06-14 | 2013-01-16 | 宝鸡石油机械有限责任公司 | Matrix type digital quantity signal collector |
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Patent Citations (5)
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| EP0297918A2 (en) * | 1987-07-02 | 1989-01-04 | National Transcommunications Limited | Digital synchronisation |
| CN101453468A (en) * | 2007-12-05 | 2009-06-10 | 中国科学院空间科学与应用研究中心 | Data communication protocol controller suitable for satellite mounted equipment |
| EP2117124B1 (en) * | 2008-05-05 | 2010-10-13 | Peter Renner | Data acquisition device and method for its operation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107991981A (en) * | 2017-12-05 | 2018-05-04 | 迈普通信技术股份有限公司 | A kind of service board and electronic equipment |
| CN107991981B (en) * | 2017-12-05 | 2019-09-20 | 迈普通信技术股份有限公司 | A kind of service board and electronic equipment |
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Effective date of registration: 20201231 Address after: 721002 No.2 Dongfeng Road, Jintai District, Baoji City, Shaanxi Province Patentee after: Baoji Oilfield Machinery Co.,Ltd. Patentee after: CHINA NATIONAL PETROLEUM Corp. Patentee after: CNPC national oil and gas drilling equipment Engineering Technology Research Center Co., Ltd Address before: 721002 No. 2 Dongfeng Road, Shaanxi, Baoji Patentee before: Baoji Oilfield Machinery Co.,Ltd. |
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