CN102709322A - High-threshold voltage gallium nitride enhanced transistor structure and preparation method thereof - Google Patents
High-threshold voltage gallium nitride enhanced transistor structure and preparation method thereof Download PDFInfo
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Abstract
The invention provides a high-threshold voltage gallium nitride enhanced transistor structure and a preparation method thereof and relates to semiconductor technology. The high-threshold voltage gallium nitride enhanced transistor structure comprises a substrate, a GaN layer, an AlGaN layer and an insulating gate dielectric layer from bottom to top and is characterized in that the insulating gate dielectric layer comprises an insulating tunnel layer, a fixed charge layer and an insulating cap layer, wherein the fixed charge layer is arranged above the insulating tunnel layer or is embedded at the upper part of the insulating tunnel layer; the insulating cap layer is arranged above the fixed charge layer; and gate metal is arranged above the insulating cap layer. The high-threshold voltage gallium nitride enhanced transistor structure has the beneficial effects that compared with other technology for manufacturing an enhanced GaN field effect transistor, the controllability of the preparation process is good, and the performance repeatability of researched and developed devices is good; and a researched and developed GaN MlSHEMT device has the advantages of good performance, large threshold voltage, large biggest source leakage saturation current density, small gate current leakage and wide operating voltage range, and the research and development demands of a GaN integrated circuit can be fully satisfied.
Description
Technical field
The present invention relates to semiconductor technology.
Background technology
With compare based on the HEMT (HEMT) of gallium aluminium arsenic/gallium arsenic (AlGaAs/GaAs) heterojunction, have the following advantages based on the HEMT device of aluminum gallium nitride/gallium nitrogen (AlGaN/GaN) heterojunction:
(1), the two-dimensional electron gas of AlGaN/GaN heterojunction boundary (2DEG) concentration higher (can reach 1013cm-2); 2DEG concentration than AlGaAs/GaAs heterojunction boundary exceeds a nearly one magnitude; Therefore, the HEMT based on the AlGaN/GaN heterojunction will have higher output power density.As the product of large-scale production, reached more than the 10W/ millimeter based on the HEMT device power density of AlGaN/GaN heterojunction, exceed nearly 20 times than the power density of GaAs based hemts device.
(2), because GaN belongs to wide bandgap semiconductor, its working temperature is high, can be in operate as normal more than 500 ℃, and be about about 200 ℃ based on the working temperature limit of the HEMT device of AlGaAs/GaAs heterojunction.
(3), because GaN has higher breakdown electric field, therefore, have higher grid-drain breakdown voltage based on the HEMT device of AlGaN/GaN heterojunction, compare with AlGaAs/GaAs heterojunction HEMT device, its operating bias exceeds more than quite a few times.
(4), high by dried GaN materials chemistry bond energy, the physical and chemical performance of material is stable, receives a little less than the influence of external physics, chemical action, therefore, has very strong anti-irradiation ability based on the HEMT of AlGaN/GaN heterojunction.
Because the above characteristics of GaN device; Not only feasible HEMT device based on the AlGaN/GaN heterojunction can be widely used in high frequency power devices field such as radar, communication and Aero-Space; Also has very big application potential in the power electronic device field; Making it becomes the semi-conducting material that application potential is arranged most after silicon (Si), gallium arsenic, and extensively receives the concern and the research of industry and educational circles.
Because GaN is a kind of strong polar semiconductor material; Naturally form the 2DEG of high concentration at the AlGaN/GaN heterojunction boundary, be difficult to exhaust the 2DEG of AlGaN/GaN heterojunction boundary under normal conditions, so; HEMT device based on the AlGaN/GaN heterojunction is depletion type usually; That is: the HEMT device of AlGaN/GaN heterojunction is in normally open under zero-bias, when only on grid, adding a certain size back bias voltage, just can make device be in off state; This is for the application in power electronic device field, and its fail safe will become very big problem.Simultaneously; Even concerning Digital Logic IC design and development,, not only need enhancement device (threshold voltage is greater than zero) in order to ensure the logical security of logical circuit; And require enhancement device to have higher threshold voltage; For this reason, the research worker is not only exploring the manufacturing technology of enhanced AlGaN/GaN HEMT device always, and is exploring the method that improves threshold voltage always.At present, the main method of enhancement mode GaN HEMT device manufacturing is following:
(1), through be with design and shear the 2DEG concentration of reduction AlGaN/GaN heterojunction boundary, thereby realization enhancement mode GaN HEMT device.
The disadvantage of this method is: can't realize the compatibility with depletion type GaN HEMT device; That is to say: can't on one piece material, both make enhancement mode GaN HEMT device; Also develop depletion type GaN HEMT device; Therefore, this method can't satisfy the development needs of GaN Digital Logical Circuits.
(2), the AlGaN barrier layer thickness through the attenuate grid region, reduce the 2DEG concentration in grid region, thereby realize enhancement mode GaN HEMT device.
Though this method is effective; But its maximum problem is: owing to be difficult to the monitoring etch rate; Cause the thickness of grid region AlGaN barrier layer to be difficult to accurate control, therefore, the consistency of performance of the enhancement mode GaN HEMT device of manufacturing and repeatability are difficult to guarantee; This is beyond affordability for the development of GaN Digital Logical Circuits equally.In addition, this method is difficult to realize higher threshold voltage.
(3), grid region AlGaN barrier layer is injected the F ion, exhaust the 2DEG in grid region, thereby realize enhancement mode GaN HEMT device.
Though this method has been avoided the shortcoming of above two kinds of methods; But its maximum problem is: the F ion of grid region AlGaN barrier layer injects and can destroy AlGaN/GaN heterojunction boundary characteristic; Make the performance degradation of GaN enhancement mode HEMT device, thereby make the GaN performance of integrated circuits of being developed relatively poor.And in order further to improve threshold voltage, more serious decline can appear in the electric property of device.
Summary of the invention
Technical problem to be solved by this invention is: a kind of enhancement mode GaN-HEMT device architecture with higher threshold voltage and preparation method thereof is provided; This device architecture can be realized the compatibility of enhancement mode GaN HEMT device and depletion type GaN HEMT device; Can guarantee to greatest extent that again enhancement mode GaN HEMT device is suitable with depletion type GaN HEMT device performance, but also can have high threshold voltage.
The technical scheme that the present invention solve the technical problem employing is: high threshold voltage gallium nitride enhancement transistor structure; Comprise: comprise substrate, GaN and AlGaN layer and insulated gate dielectric layer from bottom to top; It is characterized in that said insulated gate dielectric layer comprises insulating tunnel layer, fixed charge layer and insulator cap layer, the fixed charge layer is arranged at insulating tunnel layer top or is embedded in insulating tunnel layer top; The top of fixed charge layer is provided with the insulator cap layer, and insulator cap layer top is the grid metal.
The material of said insulated gate dielectric layer is Al
2O
3, SiO
2, HfO
2, HfTiO, ZrO
2Perhaps SiNO.
The present invention also provides high threshold voltage gallium nitride enhancement transistor structure preparation method, comprises the steps:
(1), on Sapphire Substrate preparation AlGaN/GaN heterojunction material, i.e. wafer is at crystal column surface deposition one deck Al
2O
3Film is as the insulating tunnel layer;
(2), prepare the metal electrode in source region and drain region;
(3), at crystal column surface spin coating photoresist, and after orienting the position in grid region through the alignment light carving method, wafer is put into reactive ion etching machine, use CF
4As reacting gas, the F ion is carried out in the grid region inject, form the fixed charge layer;
(4), at the thick Al of crystal column surface normal temperature deposition 10nm
2O
3Gate medium is as the insulator cap layer;
(5), at crystal column surface deposition Ni/Au metallic film, the thickness of Ni/Au metallic film is respectively 100nm and 50nm, and forms the grid metal electrode through stripping technology, under blanket of nitrogen, whole wafer is carried out annealing in process again.
The invention has the beneficial effects as follows that with other compared with techniques of making enhancement mode GaN field-effect transistor, preparation technology's controllability of present technique is good, the device performance good reproducibility of being developed.The enhancement mode GaN MISHEMT device performance of being developed is good, and threshold voltage is big, and maximum source leakage saturation current density is big, and the grid leak electricity is little, and the device operating voltage range is wide, can satisfy GaN integrated circuit development needs fully.
Description of drawings
Fig. 1 is the enhancement mode GaN HEMT device architecture sketch map with high threshold voltage.
Fig. 2 is the manufacturing process flow sketch map of using plasma submergence processing and ion injection method manufacturing enhancement mode GaN MISHEMT of the present invention device.
Fig. 3 is the manufacturing process flow sketch map that is employed in the method manufacturing enhancement mode GaN MISHEMT of the present invention device that contains vacuum moulding machine insulated gate dielectric film in F or the Cl atmosphere.
Fig. 4 is the GaN integrated circuit sketch map of enhancement mode GaN MISHEMT of the present invention and the integrated formation of depletion type GaN MESHEMT.
Fig. 5 is the GaN integrated circuit sketch map of enhancement mode GaN MISHEMT of the present invention and the integrated formation of depletion type GaN MISHEMT.
Fig. 6 is the influence curve figure of insulator cap layer of the present invention to enhancement mode GaN MISHEMT device threshold voltage.
Among Fig. 4 and Fig. 5, insulator cap layer below negative electrical charge icon area arranged side by side is represented the fixed charge layer.
Embodiment
The basic structure sketch map of enhancement mode GaN HEMT device of the present invention is as shown in Figure 1; Belong to metal-insulator semiconductor (MIS) field-effect transistor; Compare with common MIS structure GaN field-effect transistor; The characteristics of MIS structure GaN field-effect transistor of the present invention are: this insulated gate medium comprises insulator cap layer, fixed negative charge layer, three part of insulating tunnel layer, and the quantity of electric charge through the fixed negative charge layer exhausts the grid region two-dimensional electron gas, realizes that threshold voltage is greater than zero; Further improve device threshold voltage through introducing the insulator cap layer again; Thereby produce the GaN enhancement type high electron mobility transistor with higher thresholds, wherein, the insulated gate medium mainly adopts Al
2O
3, SiO
2, HfO
2, HfTiO, ZrO
2, SiN
x, SiNO, the fixed negative charge of being introduced is mainly selected high F ion of electronegativity and Cl ion.
Concrete process for making of the present invention is: deposit the insulating tunnel layer film earlier; Introduce a certain amount of fixed negative charge on insulating tunnel layer film surface again; To realize enhancement device, again at fixed negative charge laminar surface deposition insulator cap layer, last plated metal gate electrode.Through the introducing of insulator cap layer, between metal gate and fixed negative charge layer, form an internal electric field, thereby realized higher threshold voltage.
In the present invention; In the insulated gate medium, introducing fixed negative charge can adopt: the plasma immersion that contains F or Cl is handled, is injected F or Cl, containing the methods such as atmosphere vacuum moulding machine insulated gate dielectric film of F or Cl to the gate medium intermediate ion; Wherein, Handle the method for introducing fixed negative charge for the using plasma submergence, regulate and control to enter into the quantity of electric charge of the fixed negative charge of insulated gate medium through control plasma power and Immersion time; For adopting ion to inject the method for introducing fixed negative charge; Inject energy of ions through control; Ion only is injected in the insulated gate medium; Do not have ion to inject in the AlGaN barrier layer, thereby serious degradation does not take place in the performance of guaranteeing the AlGaN/GaN heterojunction boundary characteristic and the device of developing, and inject the quantity of electric charge that ion dose regulates and control to enter into the fixed negative charge of insulated gate medium through control; For the method that is employed in vacuum moulding machine insulated gate dielectric film introducing fixed negative charge in the atmosphere that contains F, Cl, regulate and control to enter into the quantity of electric charge of the fixed negative charge of insulated gate medium through the dividing potential drop that contains F, Cl gas in the control thin film deposition atmosphere.
Make enhancement mode GaN MISHEMT device of the present invention for using plasma submergence processing and ion injection method; Its manufacturing process flow is as shown in Figure 2; Earlier at AlGaN/GaN surface deposition insulating tunnel layer dielectric film; Make source electrode (Source) and drain electrode (Drain) position again by lithography, in source electrode (Source) and drain electrode (Drain) position deposit metal electrodes, and the process short annealing forms ohmic contact in source electrode and drain electrode.After defining the position, grid region through photoetching technique; Again plasma immersion processing or ion injection formation fixed charge layer film are carried out in the grid region; And deposition insulator cap layer is last, and deposit metal electrodes forms gate electrode in the grid region, thereby produces enhancement mode GaN MISHEMT device.
Make enhancement mode GaN MISHEMT device of the present invention for being employed in the method that contains vacuum moulding machine insulated gate dielectric film in F or the Cl atmosphere; Its manufacturing process flow is as shown in Figure 3; Containing under F or the Cl atmosphere at AlGaN/GaN surface deposition insulating tunnel layer dielectric film earlier; And directly in the gate medium deposition process, in gate dielectric membrane, introduce fixed negative charge through atmosphere control, and form the fixed charge layer film, make the source electrode (Source) and (Drain) position that drains again by lithography; In source electrode (Source) and drain electrode (Drain) position deposit metal electrodes, and the process short annealing forms ohmic contact in source electrode and drain electrode.After defining the position, grid region through photoetching technique, the thick insulator cap layer medium of deposition 10nm in the grid region at last, deposit metal electrodes forms gate electrode in the grid region again, thereby produces enhancement mode GaN MISHEMT device.
Both can carry out integrated by enhancement mode GaN MISHEMT device of the present invention with the depletion type GaN field-effect transistor (MESHEMT) of metal-semiconductor structure; Constitute the GaN integrated circuit; As shown in Figure 4; Can also carry out integratedly with depletion type GaN MISHEMT device, constitute the GaN integrated circuit, as shown in Figure 5.
Adopt the present invention's technological process as shown in Figure 2, the Al that adopts the F ion to inject
2O
3(below be abbreviated as: F:Al
2O
3) film successfully developed enhancement mode GaNMISHEMT device as gate medium, its device architecture sketch map is as shown in Figure 1.Concrete steps are following:
(1), on Sapphire Substrate preparation AlGaN/GaN heterojunction material (hereinafter to be referred as wafer), as the material foundation of development GaN field-effect transistor, adopt molecular beam epitaxy (MBE) at the thick Al of the about 10nm of AlGaN/GaN heterojunction material surface deposition one deck
2O
3Film is as the insulating tunnel layer.
(2), be coated with Al
2O
3The AlGaN/GaN heterojunction material surface spin coating photoresist of film through the position that source region (Source) and drain region (Drain) are oriented in photoetching, is used the Al of the HF solution of 1:100 with source region and position, drain region again
2O
3Film etches away.Adopt electron beam evaporation technique depositing Ti/Al/Ni/Au multilayer film metal electrode; The thickness of Ti/Al/Ni/Au multilayer film metal electrode is respectively 20nm/100nm/30nm/50nm; Adopt stripping technology to prepare the metal electrode in source region and drain region; And in blanket of nitrogen, metal electrode is carried out short annealing and handle (825 ℃ of annealing temperatures, annealing time 30s), to form Ohmic electrode.
(3), orient the position in grid region again at crystal column surface spin coating photoresist, and through the alignment light carving method after, wafer is put into reactive ion etching machine, use CF
4As reacting gas, the F ion is carried out in the grid region inject, form fixed charge layer dielectric film, process conditions are: injecting power 60W, operating air pressure 20mTorr, injection length 300s.
(4), again wafer is put into molecular beam epitaxy (MBE), through the thick Al of normal temperature deposition 10nm
2O
3Gate medium is as the insulator cap layer film.
(5), adopt electron beam evaporation at crystal column surface deposition Ni/Au metallic film again; The thickness of Ni/Au metallic film is respectively 100nm/50nm; And through stripping technology formation grid metal electrode; Under blanket of nitrogen, whole wafer is carried out annealing in process (400 ℃ of annealing temperatures, annealing time 10min.) again.
Through above processing step, just can develop this F:Al with high threshold voltage
2O
3The enhancement mode GaN MISHEMT device of gate medium in order to contrast, has also been made the enhancement mode GaN MISHEMT of naked cap layer gate medium, adopts HP4284A LCR appearance that these two kinds of devices of being developed are carried out the electrical properties test.
Fig. 6 has provided the influence of this insulator cap layer to the device transfer characteristic; Can find out: the enhancement mode GaN MISHEMT device threshold voltage of naked cap layer gate medium is+0.5V, and has the enhancement mode GaN MISHEMT device threshold voltage of insulator cap layer gate medium to reach+2.6V.The enhancement device that adopts this patent method to produce not only has higher threshold voltage, and maximum source leaks saturation current and reached 350mA/mm, and the maximum saturation mutual conductance reaches 55mS/mm.
Claims (5)
1. high threshold voltage gallium nitride enhancement transistor structure; Comprise substrate, GaN and AlGaN layer and insulated gate dielectric layer from bottom to top; It is characterized in that said insulated gate dielectric layer comprises insulating tunnel layer, fixed charge layer and insulator cap layer, the fixed charge layer is arranged at insulating tunnel layer top or is embedded in insulating tunnel layer top; The top of fixed charge layer is provided with the insulator cap layer, and insulator cap layer top is the grid metal.
2. as claimed in claim 1 have a high threshold voltage gallium nitride enhancement transistor structure, it is characterized in that the material of said insulated gate dielectric layer is Al
2O
3, SiO
2, HfO
2, HfTiO, ZrO
2Or SiNO.
3. the preparation method of high threshold voltage gallium nitride enhancement transistor structure as claimed in claim 1 is characterized in that, comprises the steps:
(1), on Sapphire Substrate preparation AlGaN/GaN heterojunction material, i.e. wafer is at crystal column surface deposition one deck Al
2O
3Film is as the insulating tunnel layer film;
(2), prepare the metal electrode in source region and drain region;
(3), at crystal column surface spin coating photoresist, and after orienting the position in grid region through the alignment light carving method, wafer is put into reactive ion etching machine, use CF
4As reacting gas, the F ion is carried out in the grid region inject, form the fixed charge layer film;
(4), at the thick Al of crystal column surface normal temperature deposition 10nm
2O
3Gate medium is as the insulator cap layer film;
(5), at crystal column surface deposition Ni/Au metallic film, the thickness of Ni/Au metallic film is respectively 100nm and 50nm, and forms the grid metal electrode through stripping technology, under blanket of nitrogen, whole wafer is carried out annealing in process again.
4. the preparation method of high threshold voltage gallium nitride enhancement transistor structure as claimed in claim 3 is characterized in that said step (2) is: be coated with Al
2O
3The AlGaN/GaN heterojunction material of film surface spin coating photoresist is oriented the position in source region and drain region through photoetching, uses the Al of the HF solution of 1:100 with source region and position, drain region again
2O
3Film etches away; Adopt electron beam evaporation technique depositing Ti/Al/Ni/Au multilayer film metal electrode; The thickness of Ti/Al/Ni/Au multilayer film metal electrode is respectively 20nm/100nm/30nm/50nm; Adopt stripping technology to prepare the metal electrode in source region and drain region, and in blanket of nitrogen, metal electrode is carried out short annealing and handle 825 ℃ of annealing temperatures; Annealing time 30s is to form Ohmic electrode.
5. the preparation method of high threshold voltage gallium nitride enhancement transistor structure as claimed in claim 3 is characterized in that, said step (3) ~ (5) are:
(3), at crystal column surface spin coating photoresist, and after orienting the position in grid region through the alignment light carving method, wafer is put into reactive ion etching machine, use CF
4As reacting gas, the F ion is carried out in the grid region inject, form the fixed charge layer, injecting power 60W, operating air pressure 20mTorr, injection length 300s;
(4), wafer is put into molecular beam epitaxy, through the thick Al of normal temperature deposition 10nm
2O
3Gate medium is as the insulator cap layer film;
(5), adopt electron beam evaporation at crystal column surface deposition Ni/Au metallic film; The thickness of Ni/Au metallic film is respectively 100nm/50nm, and forms the grid metal electrode through stripping technology, under blanket of nitrogen, whole wafer is carried out annealing in process again; 400 ℃ of annealing temperatures, annealing time 10min.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428314A (en) * | 2015-12-26 | 2016-03-23 | 中国电子科技集团公司第十三研究所 | Preparation method for GaN-based HEMT device |
| CN106206309A (en) * | 2015-05-07 | 2016-12-07 | 中国科学院苏州纳米技术与纳米仿生研究所 | Secondary epitaxy p-type nitride realizes method and enhancement mode HEMT of enhancement mode HEMT |
| US9704959B2 (en) | 2013-05-21 | 2017-07-11 | Massachusetts Institute Of Technology | Enhancement-mode transistors with increased threshold voltage |
| CN110571267A (en) * | 2019-08-13 | 2019-12-13 | 中山市华南理工大学现代产业技术研究院 | Having NiOXMIS-HEMT device with protective layer and preparation method |
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| US20020052076A1 (en) * | 2000-09-27 | 2002-05-02 | Khan Muhammad Asif | Metal oxide semiconductor heterostructure field effect transistor |
| WO2007016477A2 (en) * | 2005-07-29 | 2007-02-08 | International Rectifier Corporation | Normally off iii-nitride semiconductor device having a programmable gate |
| CN102184943A (en) * | 2011-04-18 | 2011-09-14 | 电子科技大学 | Enhanced AlGaN/GaN HEMT (High Electron Mobility Transistor) device and manufacturing method thereof |
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| US20020052076A1 (en) * | 2000-09-27 | 2002-05-02 | Khan Muhammad Asif | Metal oxide semiconductor heterostructure field effect transistor |
| WO2007016477A2 (en) * | 2005-07-29 | 2007-02-08 | International Rectifier Corporation | Normally off iii-nitride semiconductor device having a programmable gate |
| CN102184943A (en) * | 2011-04-18 | 2011-09-14 | 电子科技大学 | Enhanced AlGaN/GaN HEMT (High Electron Mobility Transistor) device and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9704959B2 (en) | 2013-05-21 | 2017-07-11 | Massachusetts Institute Of Technology | Enhancement-mode transistors with increased threshold voltage |
| CN106206309A (en) * | 2015-05-07 | 2016-12-07 | 中国科学院苏州纳米技术与纳米仿生研究所 | Secondary epitaxy p-type nitride realizes method and enhancement mode HEMT of enhancement mode HEMT |
| CN105428314A (en) * | 2015-12-26 | 2016-03-23 | 中国电子科技集团公司第十三研究所 | Preparation method for GaN-based HEMT device |
| CN110571267A (en) * | 2019-08-13 | 2019-12-13 | 中山市华南理工大学现代产业技术研究院 | Having NiOXMIS-HEMT device with protective layer and preparation method |
| WO2021027012A1 (en) * | 2019-08-13 | 2021-02-18 | 中山市华南理工大学现代产业技术研究院 | Mis-hemt device having niox protection layer and fabricating method |
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